US 7550761 B2
Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design.
1. A system that programs a passive memory cell array including a switchable diode integrated therewith, each memory cell comprising:
an active layer with a state changeable based on a migration of electrons or holes therefrom when subject to an external electric field or light radiation, the state indicative of information content;
a passive layer that facilitates supply of charges to the active layer, one of the active layer and the passive layer is composed of a P-type material and one of the active layer and the passive layer is composed of an N-type material;
the active and passive layer arrangement form a component with two terminals that exhibits properties of a switchable forward diode element with electrical isolation characteristics,
wherein decreasing voltage of the device in “ON” state to an erase voltage threshold point switches the device to “OFF” state,
increasing the voltage of the device in “OFF” state to a write voltage threshold switches the device to “ON” state, and
wherein a read threshold voltage is intermediate between the erase voltage threshold and write voltage threshold.
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This application is a divisional of U.S. patent application Ser. No. 10/883,350, filed on Jul. 1, 2004, entitled “SWITCHABLE MEMORY DIODE—A NEW MEMORY DEVICE”, the entirety of which is incorporated herein by reference.
The present invention relates generally to memory cells, and in particular to a memory cell with a diode integral therewith.
The proliferation and increased usage of portable computer and electronic devices has greatly increased demand for memory cells. Digital cameras, digital audio players, personal digital assistants, and the like generally seek to employ large capacity memory cells (e.g., flash memory, smart media, compact flash, or the like). Memory cells can be typically employed in various types of storage devices. Storage devices include long term storage mediums such as, for example, hard disk drives, compact disk drives and corresponding media, digital video disk (DVD) drives, and the like. The long term storage mediums typically store larger amounts of information at a lower cost, but are slower than other types of storage devices. Storage devices also include memory devices which are often, but not always, short term storage mediums.
Also, memory cells can generally be subdivided into volatile and non-volatile types. Volatile memory cells usually lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory cells include, for example, random access memory (RAM), DRAM, SRAM and the like. Non-volatile memory cells maintain their information whether or not power is maintained to the devices. Examples of non-volatile memory cells include; ROM, programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash EEPROM the like. Volatile memory cells generally provide faster operation at a lower cost as compared to non-volatile memory cells. Nonetheless, to retain the information, the stored data typically must be refreshed; that is, each capacitor must be periodically charged or discharged to maintain the capacitor's charged or discharged state. The maximum time allowable between refresh operations depends on the charge storage capabilities of the capacitors that make up the memory cells in the array. The memory device manufacturer typically specifies a refresh time that guarantees data retention in the memory cells.
As such, each memory cell in a memory device can be accessed or “read”, “written”, and “erased” with information. The memory cells maintain information in an “off” or an “on” state (e.g., are limited to 2 states), also referred to as “0” and “1”. Typically, a memory device is addressed to retrieve a specified number of byte(s) (e.g., 8 memory cells per byte). For volatile memory devices, the memory cells must be periodically “refreshed” in order to maintain their state. Such memory devices are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states. The devices are often fabricated with inorganic solid state technology, such as, crystalline silicon devices. A common semiconductor device employed in memory devices is the metal oxide semiconductor field effect transistor (MOSFET).
Because of the increasing demand for information storage, memory device developers and manufacturers are constantly attempting to increase speed and storage retrieval for memory devices (e.g., increase write/read speed). At the same time, to reach high storage densities, manufacturers typically focus on scaling down semiconductor device dimensions (e.g., at sub-micron levels). Nonetheless, formation of various transistor type control devices that are typically required for programming memory cell arrays increase costs and reduces efficiency of circuit design.
Therefore, there is a need to overcome the aforementioned deficiencies associated with conventional devices.
The following presents a simplified summary of the invention in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention, nor to delineate the scope of the present invention. Rather, the sole purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented hereinafter.
The present invention provides for systems and methods of forming diode elements integral with a memory, wherein a diode element employs an active layer (e.g. a polymer layer), and a passive layer (e.g. a super-ionic thin film), with asymmetric P/N characteristics to create a diode function. Such diode components can mitigate power consumption for memory cell arrays, and at the same time further provide for isolation of memory cells from one another, to enable an individual programming of a memory cell as part of the array.
According to one aspect of the present invention, the active and passive layer arrangement can form a component with two terminals that exhibits properties of a switchable “ON” or forward diode element with electrical isolation characteristics, which at the same time can be integral with a memory cell. The active layer can comprise: organic (e.g. conjugated polymer and related chemical compounds with N or P type properties), non-organic material, semiconducting material, and various inclusion compounds (e.g. Ti Se2). The passive and active layer can be sandwiched between ohmic contact planes. In addition, the active layer can be doped to achieve desired resistivity properties, and enable a typically precise adjustment of required threshold properties associated with the diode element. Employing the diode elements of the present invention can reduce a number of transistor-type voltage controls. Moreover, an efficient placement of polymer memory cell on a wafer surface can be obtained that increases an amount of die space available for circuit design.
In one exemplary aspect of the present invention, the diode component can be employed as part of an array for memory cells. The active layer can be a polymer layer, and the passive layer a thin film layer of super ionic material that facilitates the supply and acceptance of ions, and/or migration of electrons and holes. The active and passive layer can be sandwiched between ohmic contacts (e.g., linear voltage-current relation), which can additionally supply ions for the passive layer. As such, state change voltages can then be applied to a single memory cell as part of the array for a programming thereof to a desired state. The thickness and composition of the diode element can dictate the required threshold voltage.
In accordance with an aspect of the present invention, the diode component can enable fabrication of passive array of memory cells—wherein a number of transistors required for memory cells is greatly reduced—by enabling individual memory cells to be programmed. Accordingly, size of array employing the diode component of the present invention can be significantly condensed. Like wise, power consumption for such array can be significantly lowered.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described. The following description and the annexed drawings set forth in detail certain illustrative aspects of the invention. However, these aspects are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
To facilitate the reading of the drawings, some of the drawings may not have been drawn to scale from one figure to another or within a given figure.
The present invention is now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It may be evident, however, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the present invention.
As used herein, the term “inference” refers generally to the process of reasoning about or inferring states of the system, environment, and/or user from a set of observations as captured via events and/or data. Inference can be employed to identify a specific context or action, or can generate a probability distribution over states, for example. The inference can be probabilistic—that is, the computation of a probability distribution over states of interest based on a consideration of data and events. Inference can also refer to techniques employed for composing higher-level events from a set of events and/or data. Such inference results in the construction of new events or actions from a set of observed events and/or stored event data, whether or not the events are correlated in close temporal proximity, and whether the events and data come from one or several event and data sources.
The present invention provides for systems and methods of forming a diode element with (e.g. a two terminal diode component) by employing an active layer and a passive layer, wherein the passive layer and the active layer have opposite P/N characteristics to create a diode junction. Referring initially to
In another aspect of the present invention, the active layer 102 can include polymers such as polyaniline, polythiophene, polypyrrole, polysilane, polystyrene, polyfuran, polyindole, polyazulene, polyphenylene, polypyridine, polybipyridine, polyphthalocyanine, polysexithiofene, poly(siliconoxohemiporphyrazine), poly(germaniumoxohemiporphyrazine), poly(ethylenedioxythiophene) and related derivatives with active molecular group. It is to be appreciated that other suitable and related chemical compounds can also be employed including: aromatic hydrocarbons; organic molecules with donor and acceptor properties (N-Ethylcarbazole, tetrathiotetracene, tetrathiofulvalene, tetracyanoquinodimethane, tetracyanoethylene, cloranol, dinitro-n phenyl and so on); metallo-organic complexes (bisdiphenylglyoxime, bisorthophenylenediimine, tetraaza-tetramethylannulene and so on); porphyrin, phthalocyanine, hexadecafluoro phthalocyanine and their derivatives with active molecular group, so long as opposite P/N functionality between the active layer 102, and passive layer 104 is maintained to create the diodic junction 106.
In a related aspect of the present invention, the active layer can comprise; polymer polyphenilacetylene+molecules of chloranil or tetracyano-quino-dimethane or dichlordicyanoquinone, (which can be deposited from solution by spin-coating); copper phthalocyanine (which can be deposited by thermal deposition method to about 30 Å-1000 Å); copper hexadecafluoro phthalocyanine, amorphous carbon or palladium, (which can be deposited on the upper surface of the active layer by magnetron co-sputtering); and polysilanes with N-carbazolylpropyl group; polymer polytiophene with cyclopentadienyl groups, (which can be deposited from solution by spin-coating; polisilanes with N-carbazolylpropyl group); polysilanes with cyclopentadienyl groups; polysilanes with amino groups; polytiophene with alkyl amino groups; polytiophene with cyclopentadienyl alkyl groups; composite containing polydiphenilacetylene containing carbazolyl groups and dinitro-n-phenyl (DNP); polyethylenedioxythiophene, and porous ferroelectric (polyvinyline fluoride) containing Li CF3 SO3 salt, polydiphenilacetylene containing carbazolyl groups dinitro-n-phenyl (DNP); polyethylenedioxythiophene and salt of potassium hexycyanoferrate. As such, so long as opposite P/N functionality between the active layer 102, and passive layer 104 is maintained the diodic junction 106 of the present invention can be created.
As depicted in
In a related aspect of the present invention, the active layer 102 can also be comprised of a conjugated organic material, such as a small organic molecule and a conjugated polymer. If the organic layer is polymer, a polymer backbone of the conjugated organic polymer may extend lengthwise between the ohmic contact plane 101 and 105 (e.g., generally substantially perpendicular to the inner, facing surfaces of the ohmic contact planes). The conjugated organic molecule can be linear or branched such that the backbone retains its conjugated nature. Such conjugated molecules are characterized in that they have overlapping π orbitals and that they can assume two or more resonant structures. The conjugated nature of the conjugated organic materials facilitates control of properties associated with the diode.
In this connection, the conjugated organic material of the active layer 102 has the ability to donate and accept charges (holes and/or electrons). Generally, the conjugated organic molecule has at least two relatively stable oxidation-reduction states. The two relatively stable states permit the conjugated organic polymer to donate and accept charges, when interacting with the oppositely charged passive layer. Moreover when employing CVD techniques, it is not generally necessary to functionalize one or more ends of the organic molecule in order to attach it to the passive layer 104. Sometimes such organic molecules can have a chemical bond formed between the conjugated organic polymer of the active layer 102 and the passive layer 104.
In one particular aspect of the present invention, the organic material employed as part of the active layer can be cyclic or acyclic. For some cases, such as organic polymers, the organic material can self assemble during formation or deposition. Examples of conjugated organic polymers include one or more of polyacetylene (cis or trans); polyphenylacetylene (cis or trans); polydiphenylacetylene; polyaniline; poly(p-phenylene vinylene); polythiophene; polyporphyrins; porphyrinic macrocycles, thiol derivatized polyporphyrins; poly(p-phenylene)s; poly(imide)s; polymetallocenes such as polyferrocenes, polyphthalocyanines; polyvinylenes; polystiroles; and the like. Additionally, the properties of the organic material can be modified by doping with a suitable dopant.
The organic layer, which in one exemplary aspect can form the active layer 102, has a suitable thickness that depends upon the chosen implementations of the diode being fabricated. Some suitable exemplary ranges of thickness for the organic polymer layer, which in part can form the active layer 102, are about 0.001 □m or more and about 5 □m or less, about 0.01 □m or more and about 2.5 □m or less, and about a thickness of about 0.05 □m or more and about 1 □m or less. Similarly, the passive layer 104 can have a suitable thickness that can vary based on the implementation of the diode being fabricated. Some examples of suitable thicknesses for the passive layer 104 can be: a thickness of about 2 Å or more and about 0.1 □m or less, a thickness of about 10 Å or more and about 0.01 □m or less, and a thickness of about 50 Å or more and about 0.005 □m or less.
According to one aspect of the present invention, the passive layer can be deposited upon the ohmic contact layer 105 via vacuum thermal evaporation, sputtering, or plasma enhanced chemical vapor deposition (PECVD) utilizing a metal organic (MO) precursor. The deposition process can be monitored and controlled to facilitate, among other things, depositing the conductivity facilitating compound to a desired thickness.
Additionally, the passive layer 104 facilitates charge carrier (e.g., electrons or holes) and/or metal ion injection into the active layer 102 and increases the concentration of the charge carrier and/or metal ions in the active layer 102 that can modify the conductivity of the active layer 102.
The passive layer 104 contains at least one conductivity facilitating compound that has the ability to donate and accept charges (holes and/or electrons). Generally, the conductivity facilitating compound has at least two relatively stable oxidation-reduction states that can permit the conductivity facilitating compound to donate and accept charges. Passive layer 104 should also be capable of donating and accepting ions. Examples of other conductivity facilitating compounds that can be employed for the passive layer 104 include one or more of the following: tungsten oxide (WO3), molybdenum oxide (MoO3), titanium selenide (Ti Se2), and the like.
The passive layer 104 can in some instances act as a catalyst when forming the active layer 102. In this connection, a backbone of a conjugated organic molecule can initially form adjacent the passive layer 104, and grow or assemble away and substantially perpendicular to the passive layer surface. As a result, the backbones of the conjugated organic molecule can be self aligned in a direction that traverses the two ohmic contact planes (e.g. electrodes.) The passive layer 104 can be formed by a deposition process (e.g. thermal deposition, PVD, non-selective CVD, and the like) or by a complete sulfidation of pre-deposited thin Cu layer.
Turning now to
It is to be appreciated that the subject invention can employ classifiers that are explicitly trained (e.g., via a generic training data) as well as implicitly trained (e.g., via observing system behavior, receiving extrinsic information) so that the classifier(s) is used to automatically determine according to a predetermined criteria which regions to choose. For example, with respect to SVM's—it is to be appreciated that other classifier models may also be utilized such as Naive Bayes, Bayes Net, decision tree and other learning models—SVM's are configured via a learning or training phase within a classifier constructor and feature selection module.
The following discussion relates to typical operation of a diode element that can provide a helpful discussion to understanding various aspects of the present invention. Typically, a diode is a two-region device separated by a junction. It either allows current to pass or prohibits it. Whether the current is allowed to pass, is determined by the voltage level and polarity, referred to as biasing. Generally, when the polarity of the applied voltage matches the polarity of the diode region at the junction, the diode is considered to be forward biased, permitting the current to flow. When the polarities are opposing, the diode is considered to be reverse biased, inhibiting the current flow. Current flow in a reverse biased diode can be achieved by raising the applied voltage to a level that forces the junction into breakdown. The current flow can once again stop when the applied voltage level is reduced below the level required to cause breakdown.
In general, the relationship between the current and voltage can be expressed using the ideal diode equation:
Although a reverse biased diode is ideally non conducting, a small current still flows through the semiconductor junction when the voltage is applied due to the presence of minority carriers. The total reverse current can be approximated by:
The work functions of the two materials used to form a diodic junction determine the potential barrier formed at the junction. The work function is defined as the energy difference between the vacuum level and the Fermi level, EF. As an example, assume a metal layer and an n-type semiconductor layer are used to form the diodic layer of the present invention. Therefore, the work function of the metal layer is denoted by q□m and the semiconductor layer is denoted q(□+Vn), where □ the electron affinity of the semiconductor, is the difference in energy between the bottom of the conduction band, EC, and the vacuum level. Additionally, qVn is the difference between EC and the Fermi level.
For example, when a metal and a semiconductor layer come in contact, a charge can flow from the semiconductor to the metal. Typically, the semiconductor can be n-type, so its work function is smaller than the metal work function. As the distance between the two layers decreases, an increasing negative charge is built up at the metal surface. At the same time, an equal and opposite charge exists in the semiconductor. When the distance between the layers is comparable with the interatomic distance, the gap becomes transparent to electrons. The limiting value for the barrier height q□n is given by:
The barrier height is then the difference between the metal work function and the electron affinity of the semiconductor. It is to be appreciated that the formulas discussed supra provide a basic understanding for various attributes of a diodic layer. One skilled in the art can appreciate that the above discussion provides a basic understanding of diodic properties.
As illustrated, slope of line 501 typically reflects the current limiting resistance of the circuit (e.g., reflecting a load line that can be varied by a combination of the applied voltage and a resistance in series with the memory component.) Such line depicts a typically transitional state when switching the device.
If the voltage is increased in a direction of the arrow 502 by tracing the “OFF” state (solid curve) such that the a write voltage threshold (Vwrite) is obtained, the memory cell with integrated diode device then switches from an “OFF” state of low resistance to an “ON” state of high resistance. Subsequently, a decrease of voltage traces in a direction of arrow 503 into negative voltage values following a path of the ON state (dashed curve) representing diode characteristics, and reverse leakage current. Thereafter, an erase voltage threshold point (Verase) can be obtained that can then switch the device from an “ON” state to an “OFF” state as depicted by arrow 504. Nonetheless, if before reaching such erase threshold voltage the voltage is reversed the I-V trace will retrace back on the “ON” state curve in a direction opposite the arrow 503. Moreover, if the erase threshold is surpassed in the negative voltage direction, any voltage reversal typically will follow the “OFF” state curve, and the corresponding threshold write voltage will be increased. A read threshold voltage can be positioned any place in between Verase and Vwrite, and can be typically positioned such that a low power consumption be required for a read operation. Generally, the write voltage can be between 1 to 10 volts, and the erase voltage between −0.5 to −5 volts depending upon fabrication of the polymer memory cell and programming methodologies. It is to be appreciated that depending upon the load resistance and manner of limiting the current, a family of curves (not shown) can be obtained that pass through predetermined points on line 501, to define other ON states with different resistances, and hence providing for a multi bit operation of the device. Accordingly, a plurality of ON states can be defined for a memory cell.
The operational sequence for the switchable Schottky diode is illustrated in
The thickness of the electrodes can vary depending on the implementation and the memory device being constructed. However, some exemplary thickness ranges include about 0.01 □m or more and about 10 □m or less, about 0.05 □m or more and about 5 □m or less, and/or about 0.1 □m or more and about 1 □m or less. The electrodes can be placed in an alternating fashion among various layers of for example semiconductor layers, polymer layers, and passive layers.
Such memory cells with integral diodes can be employed in typically any device requiring memory. For example, the memory devices with integral diodes are useful in computers, appliances, industrial equipment, hand-held devices, telecommunications equipment, medical equipment, research and development equipment, transportation vehicles, radar/satellite devices, and the like. Hand-held devices, and particularly hand-held electronic devices, achieve improvements in portability due to the small size and light weight of the memory devices. Examples of hand-held devices include cell phones and other two way communication devices, personal data assistants, palm pilots, pagers, notebook computers, remote controls, recorders (video and audio), radios, small televisions and web viewers, cameras, and the like.
Initially, at 1102 a control component circuitry, as described in detail supra can be deposited on a wafer surface. Such control component can facilitate a programming of various memory cells employed as part of an array of memory cell of the present invention. Next, and at 1104 a bottom ohmic contact layer is being deposited, e.g., as part of an interconnect line as described in detail supra, which can act as a lower electrode for memory cells as part of the array. Next at 1106 various layers of: passive media, active media, with asymmetrical pn characteristics are deposited to form a diode junction integral to the memory cell. At 1108, and over such stacked layer, a top ohmic contact layer can be deposited, e.g., as part of an interconnect line to connect such memory cell with other parts of a memory cell array circuit.
Although the invention has been shown and described with respect to certain illustrated aspects, it will be appreciated that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure, which performs the function in the herein illustrated exemplary aspects of the invention. In this regard, it will also be recognized that the invention includes a system as well as a computer-readable medium having computer-executable instructions for performing the acts and/or events of the various methods of the invention. Furthermore, to the extent that the terms “includes”, “including”, “has”, “having”, and variants thereof are used in either the detailed description or the claims, these terms are intended to be inclusive in a manner similar to the term “comprising.”