|Publication number||US7557607 B1|
|Application number||US 11/803,522|
|Publication date||Jul 7, 2009|
|Filing date||May 14, 2007|
|Priority date||May 14, 2007|
|Publication number||11803522, 803522, US 7557607 B1, US 7557607B1, US-B1-7557607, US7557607 B1, US7557607B1|
|Inventors||Dai D. Tran, Jerry A. Case|
|Original Assignee||Xilinx, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (21), Non-Patent Citations (6), Referenced by (4), Classifications (5), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is related to the following co-pending U.S. patent applications: U.S. patent application entitled “Interface Lane Device Configuration,” by Patrick C. McCarthy, et al., U.S. patent application entitled “Configurable Interface,” by Paige A. Kolze, et al., U.S. patent application entitled “Hard Macro-to-User Logic Interface,” by Laurent Stadler, and U.S. patent application entitled “Reconfiguration of a Hard Macro via Configuration Registers,” by Jerry A. Case, each of which was filed on the same day as the present application and each of which is assigned to the assignee of the present application. The entire contents of each of the above-referenced co-pending patent applications are incorporated herein by reference for all purposes.
One or more aspects of the invention relate generally to integrated circuits, and, more particularly, to reset of an interface device of an integrated circuit.
Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex™ FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Heretofore, performance of a design instantiated in programmable logic of an FPGA (“FPGA fabric”) using a Peripheral Component Interconnect (“PCI”) Express (“PCIe”) internal to such FPGA was limited to performance of a PCIe design for instantiation in FPGA fabric (“soft core”). Additional details regarding examples of PCIe soft cores are available from Xilinx, Inc. of San Jose, Calif. and are described in “PCI Express PIPE Endpoint LogiCORE Product Specification,” DS321 (v1.1), Apr. 11, 2005 and in “PCI Express Endpoint Cores v3.4 Product Specification,” DS506, Feb. 15, 2007, both available from Xilinx, Inc.
PCIe soft cores have been implemented as an “Endpoint” architecture. Target applications for such Endpoint architecture include: test equipment, consumer graphics boards, medical imaging equipment, data communication networks, telecommunication networks, broadband deployments, cross-connects, workstation and mainframe backbones, network interface cards, chip-to-chip and backplane interconnect, crossbar switches, wireless base stations, high bandwidth digital video, and high bandwidth server applications, among other known add-in cards, host bus adapters, and other known applications.
Accordingly, it would be desirable and useful to provide a PCIe Endpoint internal to an FPGA having enhanced performance over that of a PCIe soft core instantiated in FPGA fabric.
One or more aspects of the invention generally relate to integrated circuits, and, more particularly, to reset of an interface device of an integrated circuit.
An aspect of the invention is a programmable logic device that includes a Peripheral Component Interconnect Express core instantiated as an application specific circuit block in the programmable logic device. The core has a reset block configurable to be in either a hierarchical reset mode or a hierarchical/separate reset mode. In the hierarchical reset mode, the reset block is configured to assert a reset signal selected of a plurality of reset signals and to automatically assert each and every other reset signal of the plurality of reset signals lower in a reset hierarchy than the reset signal selected.
Another aspect of the invention is a method for resetting an integrated circuit with an application specific circuit block, namely a Peripheral Component Interconnect Express core. A reset block of the core is configured to be in either of a first reset mode or a second reset mode. A power-on reset state is coupled to a first reset input of the reset block. The first reset input is associated with a highest-level reset signal of a reset hierarchy associated with the core. The reset hierarchy includes a plurality of reset signals. The highest-level reset signal is one of the plurality of reset signals. The power-on reset state for the integrated circuit is initiated causing the highest-level reset signal to be asserted. The core is reset, and each of the plurality of reset signals is asserted responsive to assertion of the highest-level reset signal.
Yet another aspect of the invention is a method for resetting an integrated circuit with an application specific circuit block, namely a Peripheral Component Interconnect Express core. A reset block of the core is configured to be in either of a hierarchical reset mode and a hierarchical/separate reset mode, the reset block being associated with a plurality of reset signals in a reset hierarchy. In the hierarchical reset mode, a selected reset signal of the plurality of reset signals is asserted. Each and every other reset signal of the plurality of reset signals lower in the reset hierarchy than the selected reset signal is automatically asserted. At least a portion of the core is reset responsive to the asserting.
Accompanying drawing(s) show exemplary embodiment(s) in accordance with one or more aspects of the invention; however, the accompanying drawing(s) should not be taken to limit the invention to the embodiment(s) shown, but are for explanation and understanding only.
In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative embodiments the items may be different.
In some FPGAs, each programmable tile includes a programmable interconnect element (“INT”) 111 having standardized connections to and from a corresponding interconnect element 111 in each adjacent tile. Therefore, the programmable interconnect elements 111 taken together implement the programmable interconnect structure for the illustrated FPGA. Each programmable interconnect element 111 also includes the connections to and from any other programmable logic element(s) within the same tile, as shown by the examples included at the right side of
For example, a CLB 102 can include a configurable logic element (“CLE”) 112 that can be programmed to implement user logic plus a single programmable interconnect element 111. A BRAM 103 can include a BRAM logic element (“BRL”) 113 in addition to one or more programmable interconnect elements 111. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as four CLBs, but other numbers (e.g., five) can also be used. A DSP tile 106 can include a DSP logic element (“DSPL”) 114 in addition to an appropriate number of programmable interconnect elements 111. An IOB 104 can include, for example, two instances of an input/output logic element (“IOL”) 115 in addition to one instance of the programmable interconnect element 111. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element 115 are manufactured using metal layered above the various illustrated logic blocks, and typically are not confined to the area of the I/O logic element 115.
In the pictured embodiment, a columnar area near the center of the die (shown shaded in
Some FPGAs utilizing the architecture illustrated in
Within PCIe core 210, TLM 301 is coupled to DLM 303 for bidirectional communication, and DLM 303 is coupled to PLM 305 for bidirectional communication. Additionally, each of TLM 301, DLM 303, and PLM 305 is coupled to CMM 307 for bidirectional communication. Reset block 309 is coupled to TLM 301, DLM 303, PLM 305, CMM 307, and management block 302, though not illustratively shown in
PLM 305 is coupled to Root Complex 321 via PCIe interface 318. Additionally, PLM 305 may be coupled to system resources 323 for receiving a clock signal. Reset block 309 may be coupled to system resources 323 for receiving reset signaling. Management block 302 may be coupled to system resources 323 for dynamic configuration and status monitoring. Configuration interface 314 may couple host interface 325 to management block 302, and host interface 325 may thus be coupled to CMM 307 via configuration interface 314 and management block 302. User logic 327, which may be instantiated in FPGA fabric, is coupled to TLM 301 via transaction interface 312.
With continuing reference to
Host interface 325 may be an interface to a processor of a processor block 110 of
Root Complex 321 includes I/O blocks 401-0 and 401-1. I/O block 401-0 is directly coupled to I/O block 401-2 of Endpoint 322-1. With reference to FPGA 100 of
Having this understanding of a PCIe network 400, and a PCIe hard core 210 of
The six pins may be associated with six separate reset signals. These reset signals, illustratively shown emanating from reset multiplexer 510, are reset signals 511 through 516. Reset signal 511 is provided to management block 302. Reset signal 512 is provided to configuration flip-flops 501 of CMM 307. Reset signal 512 may be referred to as a non-volatile reset to indicate that configuration flip-flops 501 are being reset. Alternatively to or in combination with flip-flops, other known storage devices which are resettable may be used. Reset signal 513 is provided to a media access controller (“MAC”) 502 of PLM 305. Reset signal 514 is provided to DLM 303 and TLM 301. Reset signal 515 is provided to a user clock domain portion 503 of TLM 301. Lastly, reset signal 516 is provided to a user clock domain portion 504 of CMM 307.
MAC 502 may include a state machine, as is known for a PCIe MAC. Accordingly, reset signal 513 may be used for resetting state of such state machine. Reset signal 515 may be used to reset TLM 301 including a user clock domain portion 503 thereof. It should be noted that reset signal 514, while resetting DLM 303 and TLM 301, does not reset a user clock domain portion 503 of TLM 301. Thus, in order to reset all of TLM 301, including user clock domain portion 503, reset signal 515 may be used.
With continuing reference to
Notably, there is a hierarchical relationship generally among reset signals 511 through 516. At the highest level is reset signal 511. This is because reset signal 511 is associated with resetting state control of PCIe core 500. Accordingly, it follows that all other affected internal states may be reset to a known default state for correspondence with resetting of management block 302. Next, below management block 302 are flip-flops 501 of CMM 307, and thus reset signal 512 is the second in the hierarchy. Notably, it is not necessary to assert reset signals 513 through 515 responsive to assertion of reset signal 512. However, generally once flip-flops 501 have been reset to different states, resetting other possibly affected internal states may be desirable. Next in the hierarchy is reset signal 513 as associated with PLM 305. Notably, of the physical, datalink, and transaction layers, respectively associated with PLM, 305, DLM 303, and TLM 301, the physical layer is the lowest. However, a lowest communication layer may be higher than other communications layers with respect to a reset hierarchy. If the state of DLM 303 is reset, then in order for correspondence of state with TLM 301, TLM 301 may also be reset. Thus, reset signal 514 is for resetting DLM 303 and TLM 301. Reset signals 513 and 514 may be asserted together. A separate user CMM reset signal 516 may be used to reset a user clock domain portion 504 of CMM 307 without resetting the remainder of CMM 307.
Reset block 309 may include a memory cell 523. Memory cell 523 may be set to select a reset mode, which will cause associated logic of reset block 309 to be configured for either a hierarchical reset mode or a hybrid hierarchical/separate reset mode. The hybrid hierarchical/separate reset mode is a hybrid of hierarchical and individual or separately set resets. The state of memory cell 523 may be set during configuration of an FPGA, such as FPGA 200 of
In a hierarchical reset mode 600, there is an association between reset inputs and affected internal resets. In the table diagram of
For power-on reset condition 701, an FPGA, such as FPGA 200 of
For a non-volatile reset condition 702, the reset pin associated with non-volatile reset signal 512 has a reset event asserted thereon, and the reset pins associated with reset signals 511 and 513 through 516 do not have reset events asserted thereon. However, in a hierarchical reset mode, even though the reset pins associated with reset signals 513 through 516 do not have reset events asserted thereon, reset signals 513 through 516, in addition to reset signal 512, are asserted in accordance with the table diagram illustratively shown in
If a user during configuration sets configuration memory cell 523 of reset block 309 of
However, reset events associated with reset signals 512 through 516 are individual or separate events. Thus, for example, if a reset event is asserted for an input pin associated with non-volatile reset signal 512, as indicated by row 512 of rows 801, then only non-volatile reset signal 512 is asserted when in hybrid reset mode 800, as indicated by an X appearing only in column 512 of columns 802. Furthermore, when a reset event is asserted with an input pin associated with MAC reset signal 513, then only MAC reset signal 513 is asserted. The same is equally true for reset signals 514 through 516, namely when a reset event is asserted for any of those pins, then only the corresponding reset signal is asserted. Notably, in hybrid reset mode 800, it is not necessary to assert only a single reset signal, and any combination of one or more of reset signals 512 through 516 may be asserted.
For a power-on reset condition, the table diagram of
The above examples are merely a few of the examples that may be implemented, and accordingly it should be appreciated that other examples of reset events to be asserted or not asserted may be used. It should further be appreciated that by having a hierarchical reset mode and a hierarchical/separate reset mode, flexibility as between using either of such modes is provided. Furthermore, it should be appreciated that the hierarchical reset mode does not require a user to have an in depth understanding of the hierarchy internal to a PCIe hard core, as the user need only understand the highest level to which such PCIe hard core is to be reset. Furthermore, a power-on reset condition may be coupled to a reset input pin associated with a management reset signal, and thus the PCIe hard core may be completely reset regardless of which reset mode is selected.
By having separate reset selection capability, as in a hybrid reset mode, a user may control reset inputs for applications involving more flexibility. However, in applications that do not require such flexibility, the hierarchical reset mode may be used to simplify complexity of the reset use model. Furthermore, by having both reset modes, compatibility between different versions of an FPGA is enhanced.
While the foregoing describes exemplary embodiment(s) in accordance with one or more aspects of the invention, other and further embodiment(s) in accordance with the one or more aspects of the invention may be devised without departing from the scope thereof, which is determined by the claim(s) that follow and equivalents thereof. Claim(s) listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.
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|U.S. Classification||326/39, 326/41|
|May 14, 2007||AS||Assignment|
Owner name: XILINX, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TRAN, DAI D.;CASE, JERRY A.;REEL/FRAME:019380/0480;SIGNING DATES FROM 20060915 TO 20070514
|Jan 7, 2013||FPAY||Fee payment|
Year of fee payment: 4