|Publication number||US7559061 B1|
|Application number||US 12/049,338|
|Publication date||Jul 7, 2009|
|Priority date||Mar 16, 2008|
|Publication number||049338, 12049338, US 7559061 B1, US 7559061B1, US-B1-7559061, US7559061 B1, US7559061B1|
|Inventors||Martin Bernard Gustafson, Kenneth Eugene Yates, Craig Lee Kuhlman|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (21), Non-Patent Citations (2), Referenced by (2), Classifications (20), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Simultaneous multithreading is a processor design that combines hardware multithreading with superscalar processor technology to allow multiple threads to issue instructions each cycle. Unlike other hardware multithreaded architectures, in which only a single hardware context (i.e., thread) is active on any given cycle, SMT permits all thread contexts to simultaneously compete for and share processor resources. Unlike conventional superscalar processors, which suffer from a lack of per-thread instruction-level parallelism, simultaneous multithreading uses multiple threads to compensate for low single-thread. The performance consequence is significantly higher instruction throughput and program speedups on a variety of workloads
The IBM/R6000 Power 5 and 6 architectures support running multiple threads on a single processor. This is possible because of the “Simultaneous Multi-Threading” (SMT) processor design. SMT enables several process threads to coexist on a single physical processor at one time. This technology maximizes the use of otherwise unused processor cycles increasing the overall work throughput (TPT) of the processor.
One embodiment would provide for maximum throughput thus increasing capacity during times when only low and medium priority work is running while allowing for the shorter turn around times required by critical work. While this idea targets the IBM/R6000 Power 5 and 6 architectures, it could be easily extended to other multi-threading architectures provided the target architecture has a mechanism for dynamically disabling and enabling multi-threading on the system.
One embodiment is to create a “SMT Control Monitor” (SCM) which would examine the type of work running on the machine. This monitor would turn ON/OFF SMT feature, and suspend/resume job threads as the work load demanded. This idea is different than other SMT control disclosures because it incorporates information from the batch system. This additional information will be used to better manage the state of SMT and the job threads.
To maximize the use of SMT, it is desirable to fully saturate the available threads. This is done by turning SMT ON, and scheduling multiple threads for each physical processor. This increases the total number of jobs completed over time at the expense of the individual job turn around time (TAT). A solution is needed to ensure the time sensitive critical work gets the shortest possible turn around time while still increasing the overall capacity by enabling SMT.
The chart in
The chart in
Table 1, shows how systems would be configured to run multiple low priority suspendable threads (usually 2) for each physical processor and either 1 non-suspendable med or 1 high priority job thread for each processor. This table shows a maximum processor load of 4 with SMT turned on and a processor load of 2 with SMT turned off.
Power5—2 physical processors
note 1: the total number of combined med and high priority threads should never exceed the number of physical processors, in this case 2.
note 2: 2 of the low priority threads would be suspended.
note 3: SMT would not be on, when high priority job threads are present.
Table 2 shows how the different job queues would control SMT and react to one another. Unless a high priority job is present, the low and med priority job queues would normally run with SMT on and maintain high processor loads. The presence of a high priority queue would cause SMT to be turned off, and the processor load levels dropped to a level equal to the number of physical processors. Low priority jobs would be suspended back to the processor load levels indicated for SMT off.
on unless high present
on unless high present
In summary the combination of toggling SMT and suspending and resuming job threads maximizes both throughput and turn around time as demanded by the jobs active on the machine. This idea allows for a higher level of throughput efficiency/capacity while still accommodating the critical work demands for shorter turn around times because it understands the importance of the work being preformed on the system.
An embodiment of the invention is a method for maximizing throughput and minimizing job turn-around-time in a multi-processing multi-threading system, the system comprises of one or more physical processors, dynamically enabling and disabling simultaneous multi-threading control. The method is comprised of the following steps:
A system, apparatus, or device comprising one of the following items is an example of the invention: multiprocessor, processor, multi-thread, jobs, prioritizing module, applying the method mentioned above, for the purpose of multithreading and management.
Any variations of the above teaching are also intended to be covered by this patent application.
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|US9218185||Mar 27, 2014||Dec 22, 2015||International Business Machines Corporation||Multithreading capability information retrieval|
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|U.S. Classification||718/100, 712/226, 712/229, 718/103, 718/102|
|International Classification||G06F9/44, G06F9/46|
|Cooperative Classification||G06F11/3476, G06F11/3433, G06F9/4818, G06F9/485, G06F9/5083, G06F11/1438, G06F9/3851|
|European Classification||G06F9/38E4, G06F9/48C2P, G06F9/48C4P, G06F9/50L, G06F11/34T4, G06F11/34C|
|Mar 16, 2008||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GUSTAFSON, MARTIN BERNARD;YATES, KENNETH EUGENE;KUHLMAN,CRAIG LEE;REEL/FRAME:020657/0089;SIGNING DATES FROM 20080313 TO 20080314
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