|Publication number||US7564057 B1|
|Application number||US 09/295,607|
|Publication date||Jul 21, 2009|
|Filing date||Apr 22, 1999|
|Priority date||Mar 17, 1992|
|Also published as||US6964890|
|Publication number||09295607, 295607, US 7564057 B1, US 7564057B1, US-B1-7564057, US7564057 B1, US7564057B1|
|Inventors||Shunpei Yamazaki, Hongyong Zhang, Yasuhiko Takemura|
|Original Assignee||Semiconductor Energy Laboratory Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (109), Non-Patent Citations (19), Referenced by (3), Classifications (22), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a Divisional of application Ser. No. 09/255,777, filed Feb. 23, 1999, now U.S. Pat. No. 6,964,890, which is itself a Divisional of application Ser. No. 08/757,616, filed Nov. 29, 1996, now U.S. Pat. No. 5,946,561, which is itself a Continuation of application Ser. No. 08/085,931, filed Jul. 6, 1993, now abandoned, which is itself a Continuation-in-part of application Ser. No. 07/853,690, filed Mar. 17, 1992, now U.S. Pat. No. 5,313,076.
1. Field of the Invention
The present invention relates to a low-temperature process for fabricating an insulated gate semiconductor device at a temperature as low as 450° C. or even lower, and to a process for fabricating, at good yield, an integrated circuit (IC) comprising said devices at a high degree of integration. The present invention also relates to a semiconductor device having fabricated by the above process. It further relates to a highly reliable semiconductor device. The semiconductor devices according to the present invention are suited for use in, for example, active matrix-driven liquid crystal displays, driver circuits of image sensors, etc., as well as thin film transistors for SOI integrated circuits and for conventional semiconductor integrated circuits (e.g., microprocessors, microcontrollers, microcomputers, semiconductor memories, etc.).
2. Prior Art
Recently, much effort is paid on the study of fabricating insulated gate semiconductor devices on insulator substrates (MOSFETs). Such devices comprising semiconductor integrated circuits on insulator substrates are advantageous for driving circuits at high speed. In contrast to the conventional semiconductor ICs whose speed is limited by the presence of a stray capacitance attributed principally to the capacitance between the connection and the substrate, the new type of semiconductor integrated circuits do not suffer such stray capacitance. The above MOSFET having a thin film active layer on an insulator substrate is denoted as a thin film transistor (TFT). The TFT can be found also in the conventional semiconductor ICs as, for example, a load transistor for SRAMs.
More recently, there is a demand for fabricating semiconductor ICs on a light-transmitting substrate, for example, as driver circuits in optical devices such as liquid crystal displays and image sensors. TFTs are also useful in such application fields. The circuits for use therein should, however, be formed over a large area. The process is therefore required to be conducted at a ever lower temperature. Furthermore, for example, when there is a need of connecting a semiconductor IC to the terminals of a device having a plurality of terminals on an insulator substrate, it is proposed to form monolithically the entire semiconductor IC or to form at least the initial stages thereof monolithically on the same insulator substrate.
Conventionally, TFTs have been fabricated by annealing an amorphous, a semi-amorphous, or a microcrystalline semiconductor film in the temperature range of from 450 to 1,200° C. to obtain a crystalline film having an improved crystallinity and having a sufficiently high mobility. TFTs include amorphous TFTs using an amorphous material as the semiconductor film, however, such TFTs are not useful as they are because they yield a mobility as low as 5 cm2/Vs or even lower, and in general, the mobility falls to a value of about 1 cm2/Vs or lower. The use of amorphous TFTs as they are is confined to a narrow range of application because of its low operation speed and its limited applicability to N-channel type TFTs. Accordingly, these TFTs were annealed in the aforementioned temperature range to attain a mobility of 5 cm2/Vs or higher. Only after annealing, these TFTs can provide P-channel TFTs (PTFTs).
A thermal process as described in the foregoing has, however, strict limitations on the material to be used as the substrate. In a so-called high temperature process which comprises a step of heating to a temperature in the range of from 900 to 1,200° C. at maximum, a thermally oxidized film of superior quality can be used as the gate dielectric. Thus, expensive substrates such as those made of quartz and sapphire and spinel were the only candidates applicable to such high temperature processes. Moreover, large area substrates were rarely obtained with such expensive materials.
In contrast to the case of a high-temperature process, variety of substrate materials can be selected for use in a low temperature process which is conducted at temperatures which do not exceed the range of from 450 to 750° C. However, a low temperature process requires annealing for a long time, and the substrates resulting therefrom suffer strain and shrinking due to the heat effect.
Furthermore, it is extremely difficult in a MISFET, i.e., an insulated gate semiconductor device having formed on an insulated surface established by incorporating a thick insulator film between a semiconductor substrate and the device to isolate the device from the semiconductor substrate, to obtain an element having favorable crystallinity as in the case using a single crystal semiconductor. Accordingly, a non-single crystalline semiconductor, i.e., a crystalline semiconductor other than a single crystal semiconductor, had been used generally in MISFETs.
The non-single crystalline semiconductors comprise defects at high density, and are usually neutralized previously with an element such as hydrogen to use them in a practically defect-free state. The neutralization process can be carried out by, for example, hydrogenation. The bond between hydrogen and the semiconductor element such as silicon is generally weak, and would easily undergo breakage to cause decomposition of the resulting compound on applying a thermal energy corresponding to a mere several tens of degrees Centigrade. Accordingly, when electric voltage or current is applied for a long duration of time, hydrogen readily undergoes desorption due to the local heat up of the semiconductor. This phenomena remarkably causes degradation of the semiconductor.
The present invention has been achieved in the light of the aforementioned circumstances. An object of the present invention is, therefore, to provide a process which can be conducted at a temperature not higher than 450° C., which suffer no limitations on the substrate material, and which has no problems of strain and shrinkage. Another object of the present invention is to provide a semiconductor device having such a structure that the heat generated during its usage can be rapidly released, and also to a process for fabricating the device.
A first embodiment of the present invention provides a thin film semiconductor device comprising a substrate having provided thereon a film comprising aluminum nitride as the principal component, having directly or indirectly formed thereon a semiconductor film comprising silicon as the principal component, and having further established directly or indirectly thereon a wiring made of a material such as a metal and a semiconductor.
The present invention also provides a process for fabricating a thin film semiconductor device having the above structure. Accordingly, a second embodiment of the present invention provides a process which comprises forming a film containing aluminum nitride as the principal component, forming thereon either directly or indirectly a semiconductor film comprising silicon as the principal component, and further establishing thereon either directly or indirectly a wiring made of a material such as a metal and a semiconductor.
Aluminum nitride is a superior conductor of heat and is suited for applications in which light transmitting properties are required, because it has an optical gap of 6.2 eV and is thereby transparent to visible light and near ultraviolet light. The aluminum nitride film is formed by deposition processes such as sputtering, reactive sputtering, and MOCVD (metal-organic chemical vapor deposition). In obtaining an aluminum nitride film by a reactive sputtering process, the process is preferably conducted under nitrogen gas atmosphere using an aluminum target. For achieving sufficient heat emission with the aluminum nitride film in accordance with the object of the present invention, the aluminum nitride film is preferably deposited at a thickness of from 100 to 5,000 Å. An aluminum nitride film 5,000 Å or more in thickness was not practically feasible because the deposited film could be easily peeled off.
The thus obtained aluminum nitride film exerts a blocking effect against mobile ions such as sodium. Accordingly, the film protects the semiconductor device against the intrusion of such mobile ions.
The aluminum nitride film need not contain nitrogen and aluminum at a stoichiometric ratio so long as the thermal conductivity of the film is not impaired. Typically, a preferred aluminum to nitrogen ratio (aluminum/nitrogen) is in the range of 0.9 to 1.4, and the thermal conductivity of the film is preferably 0.6 W/cm·K or higher. This value can be contrasted to 2 W/cm·K for single crystal aluminum nitride.
The tension of the film may be controlled optimally by changing the compositional ratio of nitrogen and aluminum. Otherwise, a trace amount of boron, silicon, carbon, oxygen, etc., may be incorporated to optimally control the strain. The film containing aluminum nitride as the principal component may be either crystalline or amorphous.
In general, a high thermal conductivity can be achieved by incorporating a diamond material such as a thin film of polycrystalline diamond, a hard carbon film, or a diamond-like carbon film. When a small area as the one in the device according to the present invention is considered, however, a satisfactory effect cannot be obtained because a tight adhesion cannot be obtained between a diamond material and a silicon oxide material. A silicon nitride film which is frequently used in a semiconductor process as a blocking layer and a passivation layer is not suited in that the thermal conductivity thereof is low. The characteristics of the well known materials for thin films were evaluated, and the results are summarized below for comparison.
Δ or X
1)AlN: Aluminum nitride,
2)DLC: Diamond-like carbon,
3)SnO2: Tin oxide, and
4)SiNx: Silicon nitride.
5)“Adhesibility” signifies adhesibility to silicon oxide.
The symbols ◯, Δ, and x in the evaluation represent “good,” “fair,” and “poor,” respectively.
In the device according to the present invention, the heat having generated from the metallic or semiconductor wiring (e.g., gate wiring, etc.) is transferred to the underlying semiconductor films (e.g., active layers, etc.), and the semiconductor films themselves generate heat by the electric current applied thereto. Accordingly, the semiconductor films are heated to a higher temperature, but the heat is rapidly transferred to an aluminum nitride film provided under the semiconductor film to prevent heat accumulation from occurring on the semiconductor film. In this manner, the temperature of the wiring and the semiconductor film can be suppressed to avoid hydrogen desorption.
It is not preferred in the present invention to deposit the semiconductor film directly on the aluminum nitride film. If the semiconductor film were to be deposited directly on an aluminum nitride, not only the adhesion results insufficient, but also an unfavorable influence is cast on the electric properties of the semiconductor film. Accordingly, it is preferable to provide, between the semiconductor film and the aluminum nitride film, a material effective for stress relaxation and yet having favorable electric and chemical properties.
Alternatively, a silicon nitride film may be formed with an aluminum nitride film thereon, and a silicon oxide film may be further formed thereon. In the device according to the present invention, the gate contact may be made from single elements such as silicon (inclusive of an impurity-doped one having an improved conductivity), aluminum, tantalum, chromium, tungsten, and molybdenum, or from an alloy or a multilayered film thereof. Furthermore, the surface thereof may be oxidized as described in the Examples referred hereinafter.
Aluminum nitride may be used positively as an etching stopper, because it would not be etched by any etching method commonly used for etching silicon oxide, silicon, aluminum, etc., in an ordinary fabrication process for semiconductor devices.
The process according to the present invention is also characterized by that the crystallinity of the semiconductor film is ameliorated not by a conventional process in thermal equilibrium, but by the irradiation of an intense light such as a pulsed laser beam or an intense light equivalent thereto. By employing this method, it can be seen that the maximum temperature of the process depends on the temperature of the step other than the annealing of the semiconductor film, that is, on the steps such as the hydrogenation annealing and the annealing of gate dielectric. Accordingly, the substrate for use in the device according to the present invention can be selected from a wider range of materials. More specifically, a soda-lime glass or an alkali-free glass (e.g., #7059 glass from Corning Incorporated), which were regarded conventionally unapplicable to substrates for operating TFTs thereon due to the low softening point thereof, can be used for driving TFTs after applying a pertinent treatment to the glass.
The process according to the present invention comprises forming a semiconductor film on an insulator substrate; forming a film capable of transmitting a laser beam or an intense light equivalent to the laser beam on said semiconductor film; irradiating a pulsed laser beam or an intense light equivalent to the laser beam to said layered film to thereby improve the crystallinity of the semiconductor film; removing said film capable of transmitting the laser beam or the intense light to expose a surface of the semiconductor film; forming a gate insulating film on said semiconductor film; forming a wiring or a gate contact on said gate insulating film; introducing impurities into said semiconductor film in a self-aligned manner with the wiring or the gate contact as a mask by processes such as ion irradiation and ion implantation and ion doping; and irradiating a pulsed laser beam or an intense light equivalent thereto to said semiconductor film with the wiring or the gate contact as a mask after the introducing step to thereby recover the crystallinity of the semiconductor film which was once destroyed in the step of introducing the impurity elements. The last two steps may be replaced by laser doping process disclosed in the application of the present inventors (see, for example, Japanese Patent Application No. Hei-4-100479). In the present invention, metallic materials having low resistivity, such as aluminum, are preferred for use as the materials for gate contact and connection. The pulsed laser beam for use in the present invention is generated preferably from ultraviolet-light emitting lasers such as excimer lasers using KrF, ArF, XeCl, and XeF gases. Preferably, an insulator film of a material selected from silicon nitride, aluminum oxide, and aluminum nitride, or a layered film composed of the same with silicon oxide film is provided between said insulator substrate and said semiconductor film. The silicon oxide film is provided at a thickness of from 300 to 3,000 Å, and more preferably, at a thickness of from 500 to 1,500 Å. The insulator film of a material selected from silicon nitride, aluminum oxide, and aluminum nitride is provided at a thickness of from 300 to 3,000 Å, and preferably, at a thickness of from 1,000 to 2,000 Å. Otherwise, a halogen infrared light-emitting lamp may be used for irradiating an intense light. An intense light (or a pulsed light) equivalent to a laser beam signifies an optical energy or a combination thereof with an auxiliary thermal energy, which is applied for a sufficiently short period of time, in general, for a duration of within 5 minutes, to the semiconductor film for recovering the crystallinity thereof.
The present invention is characterized by that after removing the previously established protective layer used for irradiation of a laser beam or an intense light equivalent thereto to the active layer to recover the crystallinity of the active layer, a film other than the protective layer may be used as the gate insulating film. This step considerably improves the characteristics of the resulting TFT. The reason for the improvement in the characteristics of a TFT is believed as follows. In the crystallization from an amorphous state, a considerable amount of non-stoichiometric compounds are often found to develop at the interface, and particularly, silicon-rich silicon oxide tend to form at the vicinity of the interface. Those non-stoichiometric compounds, however, function insufficiently either as insulators or semiconductors. It can be seen accordingly that the presence of non-stoichiometric silicon oxide hinders the achievement of preferred characteristics since it is well established that the interface plays an important role in an insulated gate element.
If a laser beam or an intense light equivalent thereto is irradiated directly onto the film without using any protective film, however, an irregular surface is developed thereon. Such an uneven surface as a consequence provides an element having poor characteristics. The step of removing the once provided protective layer corresponds to the removal of the aforementioned non-stoichiometric silicon oxide to give pure silicon with favorable crystallinity. In particular, it is found that favorable results can be obtained by removing the protective layer by wet etching using hydrofluoric acid and the like. A dry etching process causes damage to the silicon film, but wet etching provides an extremely stable surface by terminating the dangling bonds with fluorine and hydrogen before double bonds are formed among the silicon atoms.
In the present invention, the depth of the region which form upon annealing with a laser beam or an intense light equivalent thereto can be set and controlled freely as desired according to the invention of the present inventors as disclosed in Japanese Patent Application No. Hei-3-50793. In this manner, a structure comprising a double-layered active layer can be obtained to reduce the leak current between the source and the drain.
The annealing process using a laser beam or an infrared (IR) light from an IR lamp according to the present invention is preferably conducted while heating additionally the substrate to a temperature of from 100 to 500° C., and representatively, to 300 to 400° C. In this manner, a film with improved homogeneity can be obtained.
A first example for the application according to the present invention provides a peripheral circuit for an active-matrix (AM) driven liquid crystal display (LCD) device using an amorphous silicon (a-Si) TFT. The a-Si TFT-AMLCD can be obtained by establishing an a-Si TFT generally at a temperature range of 400° C. or lower on a substrate made from an alkali-free glass such as Corning #7059 glass (produced by, Corning Incorporated). An a-Si TFT has a high OFF resistance and is thereby best suited for a switching element, however, as mentioned earlier, it cannot provide a CMOS and it suffers a low operation speed. Accordingly, the peripheral driver circuit is generally established with a single crystal IC and the terminals of the matrix are connected to the terminals of the IC by methods such as tape-automated bonding (TAB). However, this type of mounting confronts more difficulty in reducing size of the pixels, and thereby the cost for mounting increases as to account for a larger percentage of the module cost.
It had been difficult by the conventional process to establish the peripheral circuit on the same substrate for the matrix due to thermal constraints. In the present invention, however, a TFT having a larger mobility can be established at a temperature equivalent to that at which a conventional a-Si TFT has been formed.
A second example for the application of the present invention comprises forming a TFT on a material such as soda-lime glass, i.e., a glass further reduced in cost as compared with an alkali-free glass. In this case, preferably, an insulator coating is first applied to the glass to avoid direct contact of the TFT with the soda-lime glass, because the mobile ions such as sodium ions intrude from the glass into the TFT. The insulator coating may be such containing silicon nitride, aluminum oxide, or aluminum nitride as the principal component. Then, a base insulator film made from silicon oxide and the like is formed on the resulting insulator coating, and the process according to the present invention is applied to establish a TFT. Furthermore, failure of the device can be avoided by preferentially using PTFTs over NTFTs as the matrix TFTs. When mobile ions intrude into an NTFT from the substrate, a channel is always formed to realize an ON state on the NTFT. However, a PTFT would not suffer formation of a channel in such a case.
A third example for the application of the present invention comprises a peripheral circuit of a liquid crystal display (LCD) of a direct multiplexing drive type, i.e., a static simple-matrix driven LCD. A ferroelectric liquid crystal (FLC), for instance, has a memory function, and it thereby provides a display of high contrast even when it is simple-matrix driven. Conventionally, however, the peripheral circuit therefor has been established in the same manner as in the a-Si TFT AMLCDs by connecting the ICs by a TAB process and the like. Similarly, the peripheral circuit for a static operation LCD which takes advantage of the phase transition from a cholesteric phase to a nematic phase has been conventionally established by TAB connection. A static drive LCD which comprises a combination of a nematic liquid crystal and a ferroelectric polymer is proposed in JP-A-61-1152 (the term “JP-A-” as referred herein signifies “an unexamined published Japanese patent application), however, this also comprises a TAB-connected peripheral circuit.
All of the LCDs enumerated above are of direct multiplexing drive and they therefore provide a large area display with high precision using a low cost substrate. A fine display can be obtained by reducing the pitch between the terminals, but only at the expense of making the IC mounting difficult. It can be seen, accordingly, that the present invention provides monolithically a peripheral circuit using a low cost substrate and yet free from concerns on the problem of heat.
A fourth example for the application of the present invention provides a so-called three-dimensional IC which comprises forming TFTs on semiconductor ICs having established thereon metallic connections. Still other and a variety of applications are available taking advantage of the present invention.
The present invention is illustrated in greater detail referring to a non-limiting example below. It should be understood, however, that the present invention is not to be construed as being limited thereto.
A peripheral circuit for an active matrix (AM)-driven liquid crystal device (LCD) using a-Si TFT was established according to the present invention. As mentioned in the foregoing, conventional AMLCDs based on a-Si TFTs had been fabricated by TAB connection because it was not possible to form the peripheral circuit monolithically with the matrix. However, a TAB process is costly due to the high cost of connection which is necessary in addition to the cost of the ICs. The total cost of the ICs and the connection amounted to account for 20% or more of the cost for the entire panel module. A low cost panel module was realized according to the present invention, by establishing the matrix and the peripheral circuit monolithically on a single glass substrate.
First, a silicon oxide film 102 as a base oxide film was formed to a thickness of from 100 to 300 nm on a Corning #7059 glass substrate 101 (either 300 mm×300 mm or 100 mm×100 mm in area) by sputtering in an oxygen atmosphere or by decomposing TEOS and depositing silicon oxide by plasma CVD, which was followed by annealing in the temperature range of from 450 to 650° C.
Then, an amorphous silicon film 103 was deposited by plasma CVD or LPCVD at a thickness of from 30 to 150 nm, preferably from 50 to 100 nm, and a silicon oxide or a silicon nitride film was deposited thereon as a protective layer 104 at a thickness of from 20 to 100 nm, preferably, at a thickness of from 50 to 70 nm. A KrF excimer laser pulse being operated at a wavelength of 248 nm and at a pulse width 20 nsec was irradiated to the amorphous silicon film 103 through the silicon oxide or silicon nitride film to improve the crystallinity of the silicon film 103. This step is shown in
Subsequently, the protective layer 104 was removed to expose the silicon layer 103, and the exposed surface was patterned into an island-like shape to establish an NTFT region 105 and a PTFT region 106. Furthermore, a film having obtained by sputtering in an oxygen atmosphere or by decomposing TEOS and depositing using plasma CVD process was further annealed at a temperature range of from 450 to 650° C. to form a gate oxide film 107. Sufficient care should be taken in treating a large area substrate by the latter process, i.e., the plasma CVD process, because strain and shrinkage may form on the substrate during the process depending on the heating temperature. If such a strain and shrinkage should generate on the substrate, difficulties should be found in the mask alignment process which is to be conducted in the later fabrication step. In the sputtering process, on the other hand, the substrate can be maintained at a temperature of 150° C. or lower. It is preferred, however, that an annealing is conducted at about 450° C. in hydrogen to reduce the dangling bonds and the like inside the film to thereby prevent the gate oxide film from being influenced by the fixed charges.
An aluminum film was further deposited thereafter to a thickness of from 200 nm to 5 μm by electron beam vapor deposition process, and was thereafter patterned to obtain gate contact 108 and 109 as illustrated in
Impurities were introduced into the island-shaped silicon film of each of the TFTs by ion doping process in a self-aligned manner using the gate contact portion (i.e., the gate contact and the surrounding anodic oxide film) as the mask. In carrying this process, phosphorus was implanted first over the entire surface using phosphine (PH3) as the doping gas, and then boron was implanted using diborane (B2H6) as the doping gas while covering the island portion 105 alone with a photoresist, so that boron may be introduced only into the island portion 106. Phosphorus and boron in this step were introduced at a dose of from 2×1015 to 8×1015 cm−2 and from 4×1015 to 10×1015 cm−2, respectively, so that the dose of boron may be higher than that of phosphorus.
The resulting structure was then subjected to laser beam irradiation using a KrF excimer laser emitting a light at a wavelength of 248 nm and being operated at a pulse width of 20 nsec as shown in
Thus was obtained N-type regions 114 and 115, and P-type regions 116 and 117. The sheet resistivity of the regions was found to be in the range of from 200 to 800 Ω/sq.
Then, a 300 nm thick silicon oxide film was deposited over the entire surface by sputtering as an interlayer insulator 118. This silicon oxide film may be replaced by a silicon nitride film having deposited by plasma CVD. The film thus obtained functions as a mere interlayer insulator in a peripheral circuit, but care must be taken in its fabrication when it is brought into an active matrix portion, because then it functions as a gate insulator for TFTs.
An amorphous silicon layer 119 was then deposited on the gate contact 110 of the active matrix portion at a thickness of from 20 to 50 nm, and a microcrystalline silicon layer which serves as the source/drain of the a-Si TFT was deposited by plasma CVD at a thickness of from 50 to 100 nm. The resulting microcrystalline silicon film was patterned to obtain source/drain 120 and 121.
Contact holes were then perforated on the source/drain of the TFTs of the peripheral circuit portion to establish aluminum connection 122, 123, and 124. It can be seen in this case that an inverter circuit is formed by the NTFT and the PTFT in the left hand side. Furthermore, a pixel electrode 125 was formed with a light-transmitting electrically conductive material such as an ITO on the TFT in the active matrix portion. Finally, the resulting structure was annealed in hydrogen for 2 hours at 350° C. to reduce the dangling bonds in the silicon film to obtain a peripheral circuit being integrated monolithically with the active matrix circuit. In the present example, a reverse-staggered type TFT was used as the a-Si TFT of the active matrix to prevent incident light to enter the channel portion, because the electric conductivity of an a-Si easily changes upon irradiation of light. Needless to say, a planar TFT can be applied as well if an effective countermeasure would be taken to shield the TFT from the external light irradiation.
An illustrative example of the characteristics of a TFT assembled in a peripheral circuit having fabricated according to the present example is shown in
The present example provides an active matrix having formed on a soda-lime glass substrate. Because a soda-lime glass is rich in sodium, a silicon nitride coating 202 was deposited by plasma CVD at a thickness of from 5 to 50 nm, preferably, at a thickness of from 5 to 20 nm, over the entire surface of a soda-lime glass substrate 201 having a thickness of 1.1 mm and an area of 300×400 mm. The silicon nitride coating above prevents sodium from diffusing into the TFT from the soda-glass substrate. This technology of providing a blocking layer on a substrate by coating the substrate with a silicon nitride or an aluminum oxide film is disclosed in Japanese Patent Application Nos. Hei-3-238710 and Hei-3-238714 filed by the present inventors. In addition, the coating 202 may otherwise be an aluminum nitride film.
Then, after forming a silicon oxide film as a base oxide film 203, a silicon film 204 was deposited by plasma CVD or LPCVD process at a thickness of from 30 to 150 nm, preferably from 30 to 50 nm, and a silicon oxide film was deposited thereon as a protective layer 205. The resulting structure was then subjected to the irradiation of a KrF excimer laser as shown in
Subsequently, the protective layer was removed to expose the silicon layer, and the exposed surface was patterned into an island-like shaped region 206 to establish thereon a gate oxide film 207 at a thickness of from 50 to 300 nm, preferably, at a thickness of from 70 to 150 nm by sputtering. An aluminum film was deposited and patterned thereafter in the same manner as in Example 1 to obtain a gate contact 208, and the gate contact was surrounded with an anodic oxide 209. The resulting structure is shown in
Boron was then introduced as a P-type impurity into the silicon layer in a self-aligned manner by ion doping, to thereby form source/drain 210 and 211 of the TFT. Subsequently, as illustrated in
Thus was obtained a TFT comprising an active layer having small field mobility, but best suited for use in an active matrix. More specifically, the TFT obtained in this example has a high ON resistance, however, the OFF resistance thereof is still sufficiently higher than the ON resistance. Accordingly, an additional capacitance which was conventionally necessary is no longer required. In particular, the source of a leak current in an N-channel MOS, i.e., the mobile ions such as sodium, casts no problem in a P-channel type device as referred in the present example.
The process according to the present example can be conducted at low temperatures with 350° C. being the maximum limit. The highest allowable temperature is attained at the fabrication of a silicon nitride film or a silicon oxide film. If the temperature were to be elevated as to exceed the maximum limit, the soda-lime glass would soften. In a process of such a low temperature, the defects in the gate oxide film sometimes causes problems. In the case of Example 1, the gate oxide film was annealed at a temperature lower than 450° C. because the substrate had a relatively high heat resistance to allow thermal annealing at such a high temperature. In the present Example using soda-lime glass substrate, however, such thermal annealing cannot be applied. Consequently, a large number of fixed charges, which are principally positive ones, would remain inside the gate oxide film. It follows that the resulting structure is not applicable to N-channel type MOS due to the excessively large leak current which generates by the presence of those fixed charges. In a P-channel type MOS, however, though the fixed charge certainly affects the threshold voltage, the leak current can be suppressed low so that the essential characteristic for an active matrix operation can be achieved. Furthermore, the source/drain were annealed with a high energy density laser beam to yield a low sheet resistance. This leads to the suppression of signal delay.
An interlayer insulator 212 was formed with polyimide thereafter. This step was followed by the formation of pixel electrode 213 using ITO. A contact hole was then established to form aluminum contacts 214 and 215 in the source/drain regions of the TFT. One 215 of the thus formed contacts was connected to the ITO. Finally, the hydrogenation of silicon was completed by annealing the resulting structure in hydrogen at 300° C. for 2 hours.
Four active matrices were formed on the resulting single substrate, and the entire structure was cut into four pieces to obtain four active matrix panels. The thus obtained active matrix has no peripheral circuit, and it can be driven only after connecting a driver IC thereto by a TAB process and the like. However, since a low cost soda-lime glass substrate is used in the place of an alkali-free glass substrate conventionally employed in an a-Si TFT AMLCD, the total cost is well comparable to those of the conventional panels. In particular, the panel according to the present Example was found best suited for large area fine displays. The active matrix thus obtained is shown schematically in
An a-Si TFT, for instance, has a mobility in the range of about 0.5 to 1.0 cm2/Vs, and was not applicable to large scale matrices which would exceed 1,000 lines. In contrast, the TFT according to the present example has a mobility as high as 3 to 10 times that of the conventional TFTs that it can be applied to such large scale matrices without any problem. Moreover, it would satisfactorily respond to analog-like gradation displays.
Furthermore, since the gate lines and the data lines are both made from aluminum, signal delay and attenuation can be considerably reduced even in a large display exceeding 20 inches in diagonal.
The present example provides a high contrast LCD taking advantage of both the diode characteristics and the memory function of a ferroelectric polymer, using a process having the fabrication cost being reduced by integrating the peripheral circuit monolithically on a single substrate. The LCDs having similar structures can be found disclosed in, for example, Japanese Patent Application No. Sho-61-1152.
This type of LCD allows a semi-static operation. Accordingly, a display of an extremely high contrast can be obtained despite a TN liquid crystal is operated in a direct multiplexing drive. Moreover, in contrast to MIM type non-linear elements, no problems are encountered in the fabrication process. The principle of its operation is illustrated in
In general, the E (electric field)-(electric flux density) characteristics of a ferroelectric exhibits a hysteresis curve as illustrated in
When a voltage of −V0 or 0 is applied to one of the facing electrodes while applying a voltage of 0 or +V0 to the other, the voltage of the cell results in one of ±2V0, ±V0, and 0. If the voltage results in either +2V0 or −2V0, as illustrated in
A cell is schematically shown in
In the same manner as generally adopted simple matrix liquid crystals, transparent stripe-shaped electrodes 505 and 506 made of ITO or another similar material are arranged so as to intersect each other at right angles. The difference with an ordinary simple matrix structure is that a transparent conductive coating of ITO or another similar material taking the form of islands is formed over one electrode 506 with a ferroelectric polymer 507 therebetween. Orientation films 509 and 510 are formed so as to cover these electrodes. This structure is described in detail in Japanese Patent Application No. 1152/1986.
The LCD constructed in this way is driven by a TAB connection of ICs in a conventional manner. This configuration has some limitations. First, in the LCD of this system, the voltage applied to the liquid crystal assumes value 1 or 0. This voltage is kept applied throughout substantially one whole frame to achieve high contrast, which is one feature of this system. Accordingly, when an image is displayed at various gray levels, it is difficult to accomplish an analog gray-scale display, which is usually done in TFT LCDs. Also, neither the pulse modulation method nor the frame modulation method, which are employed in STN LCDs, can be adopted. As a result, the LCD relies on a two-dimensional gray scale. This greatly increases the number of pixels.
The above itself is not an intrinsic difficulty with this LCD. That is to say that a large-capacity matrix can be rather easily attained due to the simple structure of this kind of LCD. In practice, however, where the density of connected terminals reaches 20 lines/mm, it is no longer possible to cope using the TAB system. Furthermore, it is difficult to fabricate the LCD by the COG (chip-on-glass) method. Therefore, it has been required that a peripheral driver circuit be formed monolithically on the same substrate.
For example, in order to achieve a two-dimensional gray scale with 64 gray levels, 6 subsidiary pixels are needed per pixel. Hence, the number of rows needed is two or three times as many as the number of rows in a normal matrix structure. If the present system is adopted in a high-definition screen in compliance with XGA standards, the number of rows reaches 1500 to 3000. Even in the case of a 15-inches. diagonal large-sized screen, a density of 10 to 15 lines/mm is needed. As the screen is narrowed, a higher-density packing is required. Especially, where a projection-type display is built using both the present system of LCD and a high-transmittance liquid crystal PDLC, the diagonal of the substrates is less than 5 inches.
At this time, high-speed IC operation is necessitated in addition to high-density packing. In this case, a circuit on an insulating substrate is less liable to loss than a circuit on a semiconductor substrate of a single crystal and can operate at a higher speed. However, if the field mobility is less than 10 cm2/V·s as in Example 2, problems occur using that configuration. Therefore, it is required that the mobility be more than 30 cm2/V·s, preferably more than 50 cm2/V·s.
For this reason, a low-temperature process using laser annealing or intense light similar to laser is desired. A process for fabricating a peripheral circuit described in
Subsequently, the silicon layer is photolithographically patterned into islands to form NTFT regions 305 and PTFT regions 306 and a gate oxide film 307 is fabricated from silicon oxide. As shown in
Thereafter, N-type dopant or phosphorus ions is/are implanted into regions 310 and 311. P-type dopant or boron ions is/are introduced into regions 312 and 313. As shown in
Finally, as shown in
The present example is illustrated in
First, an oxide film 702 forming a base layer is deposited by sputtering on a substrate 701 of Corning 7059 up to a thickness of 20 to 200 nm. A substantially amorphous silicon film of monosilane or disilane is deposited on the oxide film 702 by plasma CVD to a thickness of 50 to 150 nm. At this time, the substantially amorphous silicon film is required to function directly as amorphous silicon TFTs and to withstand laser irradiation. We have discovered that if the substrate temperature is set to 300-400° C. during fabrication of a substantially amorphous silicon film, then the characteristics of this substantially amorphous silicon film are improved. A protective silicon oxide film 705 having a thickness of 10 to 50 nm was formed on this substantially amorphous silicon film again by sputtering. Subsequently, the active-matrix circuit region is coated with a photoresist 706, and only the peripheral circuit is irradiated with laser radiation to heighten a crystallinity of the substantially amorphous silicon film of the peripheral circuit.
Under this condition, laser irradiation is performed as shown in
Subsequently, the silicon film is patterned into islands to form island region 707 for the peripheral circuit and island region 708 for the active-matrix region, as shown in
Then, as shown in
Finally, a silicon oxide film is deposited as an interlayer insulator 719 to a thickness of 400 to 1000 nm by TEOS plasma CVD. Then an ITO film 720 having a thickness of 100 to 300 nm is formed in the active-matrix region. This ITO film is patterned to form pixel electrodes. Contact holes are formed in the interlayer insulator. Metal wiring layers 721-724 are formed on the interlayer insulator. Thus, a TFT active-matrix liquid-crystal display is fabricated.
In this liquid-crystal display, the active regions of the thin-film transistors in the active-matrix circuit have lower crystallinity than the active regions of the thin-film transistors in the peripheral circuit. The active regions of the thin-film transistors in the active-matrix circuit are a substantially amorphous silicon film which exhibits a resistivity of 109 Ω·cm or more in the dark.
In the present example, the TFTs forming the pixels are made of amorphous silicon TFTs which show a high resistivity in an OFF condition, in the same manner as in Example 1. However, the TFTs used in Example 1 are of the reverse-staggered type. In the present example, the TFTs are of the top-gate type. In Example 1, the step for fabricating TFTs of a peripheral circuit and the step for fabricating the TFTs of the active-matrix circuit are different except for the process for fabricating the gate electrodes. In consequence, the number of steps is increased. In the present example, the TFTs of the peripheral circuit and the TFTs of the active-matrix circuit are built at the same time. Hence, the number of manufacturing steps can be reduced.
A silicon film suitable as an amorphous silicon TFT is required to contain a large amount of hydrogen. However, the hydrogen content must be reduced as much as possible to crystallize the TFT by laser irradiation. Since these two requirements are in conflict with each other, a silicon film satisfying both conditions to a considerable extent must be formed. For example, where plasma CVD is used, if a silicon film is formed by the use of a high-energy plasma such as ECR plasma or microwave plasma, numerous crystallized clusters are contained in the film. This is ideal for the purpose of the present example. However, it presents the problem that resistivity in the OFF condition is somewhat low.
The present example is illustrated in
First, a silicon oxide film 802 forming a base layer is deposited on an insulating substrate 801. A substantially amorphous silicon film having a thickness of 50 to 150 nm or a silicon film having low crystallinity comparable to the crystallinity of the substantially amorphous silicon film is formed on the silicon oxide film 802. In the present example, it is necessary that the substantially amorphous silicon film sufficiently withstand laser irradiation and exhibit high resistivity. Therefore, the substantially amorphous silicon film is fabricated under the same conditions as in Example 4. Then, a silicon oxide film (an insulating film) having a thickness of 10 to 500 nm, preferably 10 to 50 nm, is formed over the entire surface of the substantially amorphous silicon film by plasma CVD. The silicon oxide film (insulating film) is selectively etched to obtain a region having removed therefrom the silicon oxide film (insulating film) or having thinned therein the silicon oxide film (insulating film). Thick silicon oxide film regions 805 and thin silicon oxide film regions 806 are then formed. At this time, if isotropic etching techniques are used, smoothly sloping steps are formed as shown in
Under this condition, the laminate was lightly doped with boron ions and irradiated with laser light to crystallize the silicon film. As a result, as shown in
This step may be carried out by a method as illustrated in
As shown in
As shown in
The present example is illustrated in
First, a silicon oxide film 902 forming a base layer is deposited on an insulating substrate 901. A substantially amorphous silicon film having a thickness of 50 to 150 nm or a silicon film having low crystallinity comparable to that of the substantially amorphous silicon film is formed on the silicon oxide film 902. In the present example, it is also necessary that the substantially amorphous silicon film sufficiently withstand laser irradiation and exhibit a high resistivity. Therefore, the substantially amorphous silicon film is fabricated under the same conditions as in Example 4. Then, a protective film 905 of silicon oxide having a thickness of 20 to 100 nm is formed on the substantially amorphous silicon film. This silicon oxide film 905 can be left behind and subsequently form gate-insulating films for TFTs. As mentioned previously, it is to be noted that these TFTs have low mobility. Then, a coating having a thickness of 20 to 500 nm and made of a laser light-reflective material such as aluminum, titanium, chromium or the like, or a material which does not transmit laser light is formed on the silicon oxide film. This coating is photolithographically patterned. As shown in
Then, as shown in
Using the photoresist and the gate electrode as masks, an N-type impurity is implanted into the silicon film. In this condition, the laminate is irradiated with laser radiation to activate these implanted regions 912. At this time, the amorphous silicon would be crystallized unless the photoresist remains in regions other than the implanted regions. Where a relatively thick oxide film cannot be used to isolate elements as in the present example, leakage between the elements would undesirably result.
Similarly, with respect to P-channel TFTs, a photoresist 910 is applied. A P-type impurity is implanted while exposing only the P-channel TFTs, to form P-type doped regions 913. Then, as shown in
Then, as shown in
An example in which an active-matrix circuit is formed on a soda-lime glass substrate is given below. A soda-lime glass substrate having a thickness of 1.1 mm and measuring 300 mm by 400 mm is used as a substrate 201. A SiO2 film 216 is formed on the substrate 201, as shown in
As shown in
Then, the protective film is removed, and the silicon film is patterned into island regions 206. A gate oxide film 207 having a thickness of 50 to 300 nm, preferably 70 to 150 nm, is formed by sputtering. In the same way as in Example 1, aluminum gate electrodes 208 are formed. These gate electrodes 208 are coated with an anodic oxide 209, as shown in
Boron ions are then implanted as P-type dopant ions into the silicon layer by self-alignment techniques to form the source/drain 210 and 211 of each TFT. As shown in
Although the field mobility of the active layer is small, this small mobility is advantageous when it is used as an active-matrix TFT. In particular, the ON resistivity is high but the OFF resistivity is higher still. This makes it unnecessary to provide an auxiliary capacitance as in the prior art techniques. Especially, moving ions such as sodium ions causes a leakage current from an N-channel MOS. In the present example, problems do not occur because it is of the P-channel type.
In the present example, the highest process temperature available is 350° C. during fabrication of the silicon nitride film or silicon oxide film. The soda-lime glass softens at higher temperatures. Where such a low-temperature process is needed, defects in the gate oxide film pose problems. In Example 1, the heatproofness of the substrate is relatively good and so the gate oxide film can be annealed up to a temperature of 450° C. This is impossible to achieve in the case of soda-lime glass substrates. The result is that numerous fixed charges are left in the gate oxide film. In this case, the fixed charges are primarily positive charges. Therefore, an N-channel MOS produces a large amount of leakage between the source and drain under the influence of the fixed charges and so the N-channel MOS cannot be employed in practice. However, in a P-channel MOS, fixed charges affect the threshold voltage but the low-leakage property essential for the operation of an active-matrix circuit is maintained. Since the sources/drains are annealed by a high-energy laser beam, sheet resistance is low, and the delay of signals is suppressed.
Thereafter, an interlayer insulator 212 is fabricated from polyimide. Pixel electrodes 213 are formed from ITO, and contact holes are formed. Electrodes 214 and 215 of aluminum are formed on the source/drain regions of TFTs. One electrode 215 is also connected with the ITO electrodes. Finally, the laminate is annealed within a hydrogen atmosphere at 300° C. for 2 hours, thus completing hydrogenation of the silicon.
Four active-matrix circuits are formed on one substrate fabricated in this way. The substrate is divided into four active-matrix panels. In the present example, the active-matrix circuits have no peripheral circuits. Therefore, driving ICs must be connected with peripheral circuits by TAB or the like. Since the substrate is made of soda-lime glass which is cheaper than the non-alkaline glass substrate used in the prior art amorphous silicon TFT-AMLCD, the substrate in the present example is sufficiently profitable. Especially, the panel fabricated in the present example is suited for a large-sized, high-definition panel. The obtained active matrix is schematically shown in
In the prior art amorphous silicon TFT, the mobility is on the order of 0.5 to 1.0 cm2/V·s. Hence, it has been impossible to apply this TFT to a large-sized matrix having more than 1000 rows. In the present example, the mobility is 3 to 10 times the mobility of the amorphous silicon and therefore problems do not occur. In addition, TFTs in the present example can sufficiently respond to analog gray-scale representation. Further, the gate lines and data lines are made of aluminum. In a large-sized screen having a diagonal exceeding 20 inches, delay and attenuation of signals can be greatly reduced.
An example of the fabrication of a TFT according to the present invention is illustrated in
The aluminum nitride film 1102 is formed on both faces of the substrate to confine foreign elements such as sodium, either contained in the substrate or adhered to the surface after shipment, for preventing deterioration in the characteristics of the TFTs. The aluminum nitride film 1102 also serves to reinforce the surface of the substrate, for preventing the surface from being scratched. Especially, where TFTs are used in an active-matrix liquid-crystal display, the surface having no TFTs is exposed to the external environment and easily scratched. If scratches are formed, they reflect light irregularly, thereby darkening the screen. After the formation of the aluminum nitride film, an oxide film 1103 acting as a base layer and having a thickness of 1000 to 3000 Å is formed on the surfaces on which TFTs are to be formed. To form this oxide film, sputtering may be performed in an oxygen atmosphere. Alternatively, TEOS may be decomposed and deposited by plasma CVD in an ambient of oxygen, and the resulting film may be annealed at 450 to 650° C.
Then, an amorphous silicon film is deposited to a thickness of 300 to 1500 Å, preferably 500 to 1000 Å, by plasma CVD or LPCVD. This film is photolithographically patterned into island silicon regions 1104. A silicon oxide film having a thickness of 200 to 1500 Å, preferably 500 to 1000 Å, is then formed. This silicon oxide film serves also as a gate-insulating film. Therefore, sufficient care must be paid in fabricating this film. In the present example, the film is fabricated from TEOS. TEOS is decomposed and deposited together with oxygen at a substrate temperature of 150 to 400° C., preferably 200 to 250° C., by RF plasma CVD. The ratio of the pressures of TEOS and oxygen is 1:1 to 1:3. The pressure is 0.05 to 0.5 torr. The RF power is 100 to 250 W. Alternatively, the film can be fabricated from TEOS together with ozone gas by low-pressure CVD or atmospheric pressure CVD at a substrate temperature of 150 to 400° C., preferably 200 to 250° C. After the formation of the film, the laminate is annealed at 300-500° C. for 30 to 60 minutes in an atmosphere of oxygen or ozone.
Then, as shown in
Subsequently, an aluminum film having a thickness of 2000 Å to 5 μm is formed by electron-beam evaporation and patterned photolithographically to form gate electrodes 1106. The aluminum can be doped with 0.5 to 2% silicon. The substrate is immersed in an ethylene glycol solution of 1-3% tartaric acid having a pH of about 7. The substrate is anodized while using a platinum plate as a cathode and this gate electrode of aluminum as an anode. At the beginning of anodization, the applied voltage is increased up to 220 V with a constant current. This condition is maintained for 1 hour and then the process is ended. In the present example, the appropriate rate at which the voltage is increased is 2 to 5 V/min. under the constant-current state. In this way, an anodic oxide 1107 having a thickness of 2000 Å is formed (
Subsequently, impurity ions, or phosphorus ions, are implanted into the island silicon regions of TFTs by a self-aligning ion doping process (also known as a plasma doping process) while using the gate electrodes as a mask. Phosphine (PH3) is used as the doping gas. The dose is 2 to 8×1015 ions/cm2.
Then, as shown in
Then, a silicon oxide film is deposited as an interlayer insulator 1110 having a thickness of 3000 Å over the whole surface by plasma CVD using both TEOS and oxygen or by low-pressure or atmospheric-pressure CVD using TEOS and ozone. The substrate temperature is 150 to 400° C., preferably 200 to 300° C. After the formation of the film, this silicon oxide film is mechanically polished to flatten the surface. Furthermore, ITO is deposited by sputtering and patterned photolithographically to form pixel electrodes 1111 (
As shown in
An example of fabrication of an TFT according to the invention is illustrated in
Then, a silicon oxide film having a thickness of 1000 to 3000 Å is formed as an oxide film 403 forming a base layer. To form this oxide film, sputtering may be carried out in an oxygen atmosphere. Alternatively, TEOS may be decomposed and deposited by plasma CVD in an ambient of oxygen, and the resulting film may be annealed at 450 to 650° C.
Thereafter, an amorphous silicon film having a thickness of 1000 to 3000 Å, preferably 1000 to 1500 Å, is deposited by plasma CVD or LPCVD. The laminate is annealed at 600° C. for 48 hours in a nitrogen atmosphere. The obtained crystalline silicon film is patterned photolithographically into island silicon regions 404. Silicon oxide is deposited as a gate-insulating film 407 having a thickness of 200 to 1500 Å, preferably 500 to 1000 Å.
An aluminum film having a thickness of 2000 Å to 5 μm is formed by electron-beam evaporation and photolithographically patterned. The laminate is anodized under the same conditions as in Example 8 to form gate electrodes 409 and wiring layers 408. Then, dopant ions, or phosphorus ions, are implanted into the island silicon regions of TFTs by a self-aligning ion doping process (also known as a plasma doping process) while using the gate electrodes as a mask. Phosphine (PH3) is used as doping gas. The dose is 2 to 8×1015 ions/cm2.
The laminate is irradiated with KrF excimer laser radiation having a wavelength of 248 nm and a pulse width of 20 nsec to improve the crystallinity of the silicon film, which deteriorates due to ion doping. The energy density of the laser radiation is 150 to 400 mJ/cm2, preferably 200 to 250 mJ/cm2. In this way, N-type doped regions 405 and 406 are formed. The sheet resistance of these regions is 200 to 800 Ω/cm2 (
Then, silicon oxide is deposited as an interlayer insulator 410 having a thickness of 3000 Å over the entire surface by plasma CVD, LPCVD, or atmospheric pressure CVD. A photoresist 411 is selectively applied. It is better to apply this photoresist at the intersections of wiring layers or at locations where contacts are attached to the wiring layers (
As shown in
A titanium film having a thickness of 2000 Å to 5 μm is formed as a conductive interconnect material. This titanium film is patterned photolithographically to form wiring layers 412 and 413 connected with the source and drain of a TFT. ITO is selectively formed to produce pixel electrodes 414. Finally, the laminate processed in this way is annealed in a hydrogen at 350° C. for 30 minutes at 1 atm., thus completing hydrogenation of the laminate. In this way, one TFT is completed. Numerous TFTs manufactured at the same time were arranged in rows and columns to build an active-matrix liquid-crystal display.
An example of fabrication of a TFT according to the invention is illustrated in
Then, a silicon oxide film is deposited as an oxide film 603 having a thickness of 1000 to 2000 Å and forming a base layer. To form this oxide film, sputtering may be carried out in an ambient of oxygen. Alternatively, TEOS may be decomposed and deposited by plasma CVD in an ambient of oxygen, and the resulting film may be annealed at 450 to 650° C.
Subsequently, an amorphous silicon film having a thickness of 1000 to 3000 Å, preferably 1000 to 1500 Å, is deposited by plasma CVD or LPCVD. The laminate is annealed at 600° C. for 48 hours in a nitrogen atmosphere. The obtained crystalline silicon film is patterned photolithographically into island silicon regions 604. Silicon oxide is deposited as a gate-insulating film 605 having a thickness of 200 to 1500 Å, preferably 500 to 1000 Å.
An aluminum film having a thickness of 2000 Å to 5 μm is formed by electron-beam evaporation and photolithographically patterned. The laminate is anodized under the same conditions as in Example 8 to form gate electrodes 606 and a wiring layer 607 (
Then, impurity ions, or phosphorus ions, are implanted into the island silicon regions of TFTs by a self-aligning ion doping process (also known as a plasma doping process) while using the gate electrodes as a mask. Phosphine (PH3) is used as doping gas. The dose is 2 to 8×1015 ions/cm2 (
The silicon oxide film 603 acting as a base layer is etched. The etching is terminated by the aluminum nitride film 602 acting as a stopper. Under this condition, the laminate is irradiated with KrF excimer laser radiation having a wavelength of 248 nm and a pulse width of 20 nsec to improve the crystallinity of the silicon film, which deteriorates due to ion doping. The energy density of the laser radiation is 100 to 400 ml/cm2, preferably 100 to 150 mJ/cm2. Since a silicon oxide film containing phosphorus or boron absorbs ultraviolet radiation, where laser annealing is conducted subsequent to through-doping as in Example 8, intense laser light is needed. In the present example, however, if the silicon oxide film, or gate-insulating film, is removed after doping, less laser energy suffices. This can improve the throughput of the laser processing. In this way, N-type phosphorus-doped regions 608 and 609 are formed. The sheet resistance of these regions is 200 to 800 Ω/cm2 (
Then, silicon oxide is deposited as an interlayer insulator 610 having a thickness of 2000 to 3000 Å over the entire surface by plasma CVD, LPCVD, or atmospheric pressure CVD. An aluminum film having a thickness of 2000 Å to 5 μm is formed as a wiring layer material. This aluminum is photolithographically patterned to form wiring layers 611 and 612 connected with the source and drain of a TFT. As shown, the wiring layer 612 crosses the wiring layer 607 (
Finally, the laminate processed in this way is annealed in a hydrogen at 350° C. for 30 minutes at 1 atm., thus completing hydrogenation of the laminate. In this way, a TFT is completed. At the same time, the doped region is doped with boron to fabricate a P-channel TFT. A CMOS is fabricated. Typical field mobilities of the N-channel and P-channel types are 80 to 150 cm2/Vs and 40 to 100 cm2/Vs, respectively. We have confirmed that a shift register constructed from these TFTs operated at 11 MHz when the drain voltage was 17 V.
Although a high voltage exceeding 20 V is applied to the gate and the drain for a long time (about 96 hours), the characteristics deteriorate only slightly. This is because heat generated locally in the TFTs is quickly dissipated, suppressing liberation of hydrogen atoms from the interface with the semiconductor coating and from the interface with the gate-insulating film.
An active-matrix circuit is formed on a soda-lime glass' substrate 201 by the steps illustrated in
Then, a silicon oxide film 203 forming a base layer is formed in the same way as in Example 2. Subsequently, a TFT illustrated in
A laser-crystallized silicon TFT for forming a peripheral circuit and an amorphous silicon TFT for an active-matrix circuit are formed on a substrate 701 of Corning 7059 by the steps illustrated in
A TFT is formed by the steps shown in
A TFT is formed by the steps illustrated in
The present invention permits fabrication of a TFT which shows high reliability even if a voltage is applied for a long time. In this way, the present invention is industrially very advantageous. Especially, where TFTs are formed on a substrate having a large area and used as an active-matrix circuit or as a driver circuit, great industrial advantages can be attained.
In accordance with the present invention, TFTs can be manufactured at low temperatures with a quite high production yield. Various LCD structures can be produced according to the invention as described in the above examples, because characteristics required by TFTs can be set at will in the present invention.
Although not described in the above examples, the invention can be applied to a three-dimensional IC structure where a semiconductor circuit is built on a single-crystal IC or the like. The above-described examples principally pertain to the use of the invention in various LCDs. Obviously, the invention may also be utilized in other circuits which are required to be formed on an insulating substrate such as an image sensor.
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|U.S. Classification||257/72, 257/347, 257/59, 257/66|
|International Classification||H01L29/04, H01L29/49, H01L21/84, H01L21/20, H01L29/423, H01L29/76, H01L21/77, H01L31/036|
|Cooperative Classification||H01L29/4908, H01L29/42384, H01L27/1214, H01L29/04, H01L21/2026|
|European Classification||H01L27/12T, H01L29/49B, H01L29/423D2B8, H01L29/04, H01L21/20D2|
|Mar 4, 2013||REMI||Maintenance fee reminder mailed|
|Jul 21, 2013||LAPS||Lapse for failure to pay maintenance fees|
|Sep 10, 2013||FP||Expired due to failure to pay maintenance fee|
Effective date: 20130721