|Publication number||US7566364 B2|
|Application number||US 11/483,586|
|Publication date||Jul 28, 2009|
|Filing date||Jul 11, 2006|
|Priority date||Jul 12, 2005|
|Also published as||US20070017439|
|Publication number||11483586, 483586, US 7566364 B2, US 7566364B2, US-B2-7566364, US7566364 B2, US7566364B2|
|Inventors||Wenxu Xianyu, Young-soo Park, Takashi Noguchi, Hans S. Cho, Xiaoxin Zhang, Huaxiang Yin|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Non-Patent Citations (9), Referenced by (13), Classifications (14), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2005-0062923, filed on Jul. 12, 2005, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.
Example embodiments of the present invention relate to a method of fabricating a single-crystalline wire, for example, a method of fabricating a higher quality single-crystalline wire in which the uniformity and size of the diameter are easily controlled, and a method of fabricating a transistor having the same.
2. Description of the Related Art
The continuous downscaling of conventional CMOS semiconductor devices has been limited by the rapid increase of the integration level thereof. In order to provide highly-integrated devices having higher-performance and lower power consumption in downscaling conventional CMOS semiconductor devices, the widths and lengths of gate electrodes may be reduced, the isolation regions between unit elements may be reduced, and the thicknesses and junction depths of gate insulation layers may be thinned. Because these changes should essentially ensure gate controllability, the ratio of an on-current to an off-current (Ion/Ioff) in transistors may be increased. In the conventional art, in order to enhance a driving current, ultra-thin body fully depleted (UTB-FD) silicon-on-insulator (SOI) transistors using SOI substrates and band-engineered transistors which use strained silicon channels to enhance electron mobility and/or the like, have been explored. In addition, various 3-dimensional silicon transistors, for example, vertical transistors, Fin-FETs, and double-gate transistors, have been researched. However, the gate structure of silicon transistors, having 3-dimensional gate structures, may not increase the field effects of the gate. Because a channel should be formed as a silicon substrate or a silicon layer with a 3-dimensional structure determined by deposition and patterning processes, the processes for forming a 3-dimensional gate structure may become complicated.
Recently, as an approach to overcome the downscaling limitation of a silicon device, transistors, using carbon nanotubes (CNTs) as channels, have been developed, for example, a CNT transistor operated at room temperature, a technique of horizontally growing CNTs and/or techniques of vertically growing CNTs from nanoholes.
Example embodiments of the present invention may provide a method of fabricating a horizontal single crystalline nanowire, which may provide improved gate controllability and fabrication, and a method of fabricating a transistor having the same.
According to an example embodiment of the present invention, there may be provided a method of fabricating a crystalline wire, including: forming a template layer on a substrate, the template layer having a first lateral surface and a second lateral surface facing the first surface; forming pores in the template layer, the pores being disposed between the first lateral surface and the second lateral surface in the template layer and having first apertures in the first lateral surface; forming a single-crystalline material layer contacting the first apertures disposed on the first lateral surface of the template layer; and forming second apertures connecting pores in the second lateral surface, supplying gaseous crystal growth materials through the second apertures, and forming crystalline nanowires in the pores by crystal growth from the single-crystalline material layer.
According to another example embodiment of the present invention, there may be provided a method of fabricating a transistor in which nanowires are used as channels, the method including: forming a template layer on a substrate, the template layer having a first lateral surface and a second lateral surface facing the first surface; forming pores in the template layer, the pores disposed between the first lateral surface and the second lateral surface in the template layer and having first apertures in the first lateral surface; forming a single-crystalline material layer contacting the first apertures disposed on the first lateral surface of the template layer; forming second apertures connecting pores disposed in the second lateral surface, supplying gaseous crystal growth materials through the second apertures, and forming the crystalline nanowires in the pores by crystal growth from the single-crystalline material layer; and forming a gate which forms an electric field toward the crystalline nanowires, and a source and drain electrically connected to ends of the wires.
The crystalline nanowires may be formed of Si, SiGe, and/or the like. The substrate may be formed of Si, sapphire (SiGe), and/or the like.
The forming of the template layer may further include: forming the template layer of aluminum; and forming the pores in the template layer and parallel to the substrate by anodic oxidation.
The method may further include: forming a capping layer on the template layer except for the first lateral surface and the second lateral surface before the forming of the pores.
A buffer layer, made of an insulation material, may be formed on the substrate, and the forming of the single-crystalline material layer may include: forming a window in a portion near the first apertures of the buffer layer, the window exposing the surface of the substrate; and epitaxially growing the single-crystalline material from the surface of the substrate exposed through the window to contact the apertures.
The buffer layer may be formed on the substrate, and the forming of the single-crystalline material layer may include: forming a window in a portion near the first apertures of the buffer layer, the window exposing the surface of the substrate; epitaxially growing the single-crystalline material from the surface of the substrate exposed through the window; forming amorphous silicon on a stacked structure having the first lateral surface of the template layer; and inducing crystallization of the amorphous silicon from the contact portion to the single-crystalline material by annealing, and then transforming the amorphous silicon contacting to the apertures into single-crystalline silicon.
The above and other features and advantages of example embodiments of the present invention will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings in which:
Hereinafter, example embodiments of the present invention will be described more fully with reference to the accompanying drawings, in which example embodiments of the invention are shown. A crystalline nanowire of the present invention is formed of a semiconductor material, for example, Si and/or SiGe, however, other crystalline material may be used. Example embodiments of the present invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments of the present invention.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the example embodiments of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Example embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures) of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fabrication of Nanowires
The anodic oxidation of the template layer 200 b in an electrochemical bath is illustrated in
In order to obtain uniform pores and the straighter template layer 200 formed by the anodic oxidation, some of the pores having a given length, and initially formed during the anodic oxidation, may be removed, and then an additional anodic oxidation may be performed, thereby obtaining improved pores.
When the single-crystalline seed layer 400 contacts the first lateral surface 200 a as shown in
A transistor having single-crystalline nanowires as an electron moving channel may be fabricated by changing some of the above-described processes of forming the nanowires and adding other processes.
Hereinafter, a method of fabricating a transistor will be described.
The transistors in
According to an example embodiment of the present invention, higher quality nanowires, whose orientation may be controlled and are made of crystalline materials, e.g., Si, SiGe, and/or the like, may be formed parallel to a substrate. In addition, a higher quality transistor may be formed on a substrate by applying a method of fabricating the nanowires.
A method of fabricating nanowires, according to an example embodiment of the present invention, may be used to fabricate multi-layer nanowires and may be employed to fabricate a multi-layer transistor.
The foregoing is illustrative of example embodiments of the present invention and is not to be construed as limiting thereof. Although a few example embodiments of the present invention have been described, those skilled in the art will readily appreciate that many modifications may be possible in the example embodiments without materially departing from the novel teachings and advantages of example embodiments of the present invention. Accordingly, all such modifications are intended to be included within the scope of example embodiments of the present invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of example embodiments of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. Example embodiments of the present invention are defined by the following claims, with equivalents of the claims to be included therein.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6914256 *||Jan 20, 2004||Jul 5, 2005||North Carolina State University||Optoelectronic devices having arrays of quantum-dot compound semiconductor superlattices therein|
|US20030215865 *||Apr 25, 2003||Nov 20, 2003||The Penn State Research Foundation||Integrated nanomechanical sensor array chips|
|US20040144985 *||Jan 20, 2004||Jul 29, 2004||Zhibo Zhang||Optoelectronic devices having arrays of quantum-dot compound semiconductor superlattices therein|
|US20050156180 *||Feb 24, 2005||Jul 21, 2005||Zhibo Zhang||Optoelectronic devices having arrays of quantum-dot compound semiconductor superlattices therein|
|US20050276743 *||Jan 13, 2005||Dec 15, 2005||Jeff Lacombe||Method for fabrication of porous metal templates and growth of carbon nanotubes and utilization thereof|
|US20070113779 *||Nov 2, 2006||May 24, 2007||The Research Foundation Of State University Of New York||Metal oxide and metal fluoride nanostructures and methods of making same|
|1||"50 nm Vertical Replacement-Gate (VRG) pMOSFETs". Sang-Hyun Oh et al. Bell Laboratories, IEEE, pp. 3.6.1-3.6.4, 2000.|
|2||"Electric-Field-Directed Growth of Aligned Single-Walled Carbon Nanotubes". Yuegang Zhang et al. Applied Physics Letters, vol. 79, No. 19, Nov. 5, 2001.|
|3||"FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm". Digh Hisamoto et al. IEEE Transactions on Electron Devices, vol. 47, No. 12, pp. 2320-2325, Dec. 2000.|
|4||"Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate". Jack P. Denton et al. IEEE Electron Device Letters, vol. 17, No. 11, pp. 509-511, Nov. 1996.|
|5||"Highly Ordered Monocrystalline Silver Nanowire Arrays". G. Sauer et al. Journal of Applied Physics, vol. 91, No. 5, pp. 3243-3247, Mar. 1, 2002.|
|6||"Mobility Enhancement in Strained Si NMOSFETS with HfO2 Gate Dielectrics". K. Rim et al. IBM T.J. Watson Research Center, IEEE, pp. 12-13, 2002.|
|7||"Preparation and Lithium Insertion Properties of Mesoporous Vanadium Oxide". Ping Liu et al. Advanced Materials, 14, No. 1, Jan. 4, 2002.|
|8||"Room-Temperature Transistor Based On a Single Carbon Nanotube". Sander J. Tans et al. Nature, vol. 393, pp. 49-52, May 7, 1998.|
|9||"Statistical Model for Stress-Induced Leakage Current and Pre-Breakdown Current Jumps in Ultra-Thin Oxide Layers". R. Degraeve et al. IEEE, pp. 6.2.1-6.2.4, 2001.|
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|US9012284 *||Jul 27, 2012||Apr 21, 2015||Intel Corporation||Nanowire transistor devices and forming techniques|
|US9040363||Mar 20, 2013||May 26, 2015||International Business Machines Corporation||FinFET with reduced capacitance|
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|US9536979||Dec 9, 2015||Jan 3, 2017||International Business Machines Corporation||FinFET with reduced capacitance|
|US20070187668 *||Nov 13, 2006||Aug 16, 2007||Takashi Noguchi||Crystal substrates and methods of fabricating the same|
|US20120068156 *||Sep 20, 2011||Mar 22, 2012||University Of South Carolina||InN Nanowire Based Multifunctional Nanocantilever Sensors|
|US20130161756 *||Jul 27, 2012||Jun 27, 2013||Glenn A. Glass||Nanowire transistor devices and forming techniques|
|U.S. Classification||117/84, 117/90, 117/94, 117/95, 117/91|
|Cooperative Classification||C30B29/06, C30B29/60, C30B29/08, C30B25/005|
|European Classification||C30B25/00F, C30B29/60, C30B29/06, C30B29/08|
|Oct 3, 2006||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
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Effective date: 20060911
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