|Publication number||US7576013 B2|
|Application number||US 10/710,662|
|Publication date||Aug 18, 2009|
|Filing date||Jul 27, 2004|
|Priority date||Jul 27, 2004|
|Also published as||US20060024921|
|Publication number||10710662, 710662, US 7576013 B2, US 7576013B2, US-B2-7576013, US7576013 B2, US7576013B2|
|Original Assignee||United Microelectronics Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (1), Classifications (13), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a semiconductor fabrication process. More particularly, the present invention relates to a method of relieving wafer stress.
2. Description of the Related Art
At present, most semiconductor devices are fabricated on silicon wafers. To increase productivity and lower production cost, the diameter of wafers has been increased steadily from 4, 5, 6, 8 inches to 12 inches so that more chips can be fabricated from a single wafer.
In most semiconductor fabrication processes, a continuous film layer first deposited over a wafer before performing a photolithographic and etching process to pattern the film. For example, in the process of fabricating metallic interconnects, a dielectric layer is formed over a wafer and then patterned to form a via opening or a trench before depositing metallic material into the via opening or the trench. When the deposited film induces stress in the wafer due to some processing factors (such as a chemical-mechanical polishing operation), the entire wafer may warp. If such wafer stress is not relieved in time, subsequently processing operations is likely to be affected.
As shown in
As shown in
In the aforementioned process, the patterned photoresist layer 108 is formed over a warped dielectric layer 106. Because the wafer 100 will return to its warp-free state as soon as the opening 110 is formed in the dielectric layer 106, the openings 110 may shift relative to the intended positions. As a result, misalignment of the contacts/vias 104 occurs quite frequently.
Furthermore, the misalignment problem aggravates from the warping center towards the edge of a wafer. Hence, the misalignment problem is particularly serious for a wafer with a larger diameter. For a chips lying in the peripheral region of a wafer, the situation may be so serious that the metallic interconnect process fails to link up a metallic line with a corresponding contact or via. When this happens, performance of the device will deteriorate and yield of the chip will drop.
Accordingly, at least one objective of the present invention is to provide a stress relieving method for a wafer capable of relieving internal stress within a highly stressed film layer above the wafer.
At least a second objective of this invention is to provide a stress relieving method for a wafer capable of preventing any misalignment after a photolithographic process due to a warping of the wafer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a stress relieving method for a wafer. A wafer is provided, wherein at least a dielectric layer has already formed over the wafer and the wafer having a first and a second area. At least no circuits are formed on the dielectric layer within the first area. Thereafter, openings are formed in the dielectric layer within the first area. A material layer is formed over the dielectric layer, wherein the material layer is fabricated from a dielectric material or a metal material. Thus, pits are formed on the surface of the material layer at locations above the first opening. Through the pits on the material layer, stress within the material layer is relieved and hence the amount of stress conferred to the wafer is reduced.
This invention also provides an alternative stress relieving method for a wafer. A wafer is provided, wherein at least a dielectric layer has already formed over the wafer and the-wafer having a first area and a second area. At least no circuits are formed on the dielectric layer within the first area. Thereafter, a material layer is formed over the dielectric layer, wherein the material layer is fabricated from a dielectric material or a metal material. A plurality of openings is formed in the material layer within the first area. These openings absorb stress within the material layer so that the amount of stress conferred to the wafer is reduced.
Accordingly, by breaking up the high stress film layer (the material layer) into a sheet with discontinuous surface and height difference, this invention relieves the stress within the film layer and prevents the warping of the wafer. Therefore, misalignment of photoresist pattern after a photolithographic process is avoided. Furthermore, no additional photomask is required and hence there is no added complexity to the fabrication process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
As shown in
As shown in
As shown in
The aforementioned stress relieving method for wafer includes forming a plurality of openings 212 in the area 204 without any circuits so that a material layer 216 deposited over the wafer contains pits 218. Hence, the material layer 216 no longer forms a continuous smooth surface. Through the pits 218, internal stress within the material layer 216 is relieved so that the wafer is prevented from warping. As a result, misalignment of the patterns formed by a subsequent photolithographic and etching processes due to warping can be avoided.
Furthermore, the openings 212 for relieving stress and the openings 210 for fabricating semiconductor devices may be formed in a single photolithographic/etching process. Therefore, the same number of masks as in a conventional process is used. In other words, this invention can be implemented to relieve stress within a film layer and prevent the wafer from warping without adding any complexity to the fabricating process.
In another embodiment of this invention, different steps are carried out to foster the same stress relieving function. Similarly, to simplify description and prevent the incorporation of any unnecessary restrictions to this invention, some structure components and their description are omitted below. Furthermore, any elements identical to the first embodiment are labeled identically.
As shown in
As shown in
The second embodiment of this invention uses a series of steps that differs from the first embodiment. However, they both use the same idea of breaking up the continuous material layer 216 to reduce stress within the material layer 216. With the internal stress within the material layer 216 removed, the wafer is prevented from warping. As a result, misalignment of the patterns formed by a subsequent photolithographic and etching processes due to warping is similarly avoided.
In the first embodiment, each opening 212 exposes a film layer (the wafer 200 in
Although a metallic interconnect fabrication process is used as an example in both embodiments, the applications of this invention is not limited as such. This invention can be applied to fabricate the bit lines of a memory device or some other semiconductor devices. In any case, the stress relieving method of this invention can be applied whenever a high stress film layer is formed over a wafer.
Accordingly, by breaking up the high stress film layer (the second dielectric layer) into a sheet with discontinuous surface and height difference, this invention relieves the stress within the film layer and prevents the warping of the wafer. Thus, misalignment of photoresist pattern after a photolithographic process is avoided.
Furthermore, no additional photomask is required. Hence, there is no added complexity to the fabrication process.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5189505 *||Aug 22, 1991||Feb 23, 1993||Hewlett-Packard Company||Flexible attachment flip-chip assembly|
|US5401683 *||Sep 13, 1988||Mar 28, 1995||Agency Of Industrial Science And Technology||Method of manufacturing a multi-layered semiconductor substrate|
|US5447884 *||Jun 29, 1994||Sep 5, 1995||International Business Machines Corporation||Shallow trench isolation with thin nitride liner|
|US5622899 *||Apr 22, 1996||Apr 22, 1997||Taiwan Semiconductor Manufacturing Company Ltd.||Method of fabricating semiconductor chips separated by scribe lines used for endpoint detection|
|US5798568 *||Aug 26, 1996||Aug 25, 1998||Motorola, Inc.||Semiconductor component with multi-level interconnect system and method of manufacture|
|US6181569 *||Jun 7, 1999||Jan 30, 2001||Kishore K. Chakravorty||Low cost chip size package and method of fabricating the same|
|US6571485 *||Nov 30, 2001||Jun 3, 2003||United Microelectronics Corp.||Structure of an overlay mark and its dosimetry application|
|US6828211 *||Oct 1, 2002||Dec 7, 2004||Taiwan Semiconductor Manufacturing Co., Ltd.||Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|CN102709233A *||Jun 21, 2012||Oct 3, 2012||上海华力微电子有限公司||Formation method for copper double-Damask structure and manufacturing method for semi-conductor device|
|U.S. Classification||438/761, 257/E21.598, 257/E21.599|
|International Classification||H01L21/469, H01L21/31|
|Cooperative Classification||H01L2924/0002, H01L23/562, H01L2924/3511, H01L21/76801, H01L21/76822|
|European Classification||H01L23/562, H01L21/768B, H01L21/768B8|
|Jul 27, 2004||AS||Assignment|
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HUANG, JUI-TSEN;REEL/FRAME:014904/0108
Effective date: 20040204
|Jan 20, 2013||FPAY||Fee payment|
Year of fee payment: 4
|Jan 13, 2017||FPAY||Fee payment|
Year of fee payment: 8