Publication number  US7584449 B2 
Publication type  Grant 
Application number  US 11/271,323 
Publication date  Sep 1, 2009 
Filing date  Nov 10, 2005 
Priority date  Nov 22, 2004 
Fee status  Paid 
Also published as  US8051396, US20060120189, US20090217232 
Publication number  11271323, 271323, US 7584449 B2, US 7584449B2, USB27584449, US7584449 B2, US7584449B2 
Inventors  Peter Beerel, Andrew Lines, Michael Davies 
Original Assignee  Fulcrum Microsystems, Inc. 
Export Citation  BiBTeX, EndNote, RefMan 
Patent Citations (41), NonPatent Citations (41), Referenced by (28), Classifications (4), Legal Events (5)  
External Links: USPTO, USPTO Assignment, Espacenet  
The present application claims priority under 35 U.S.C. 119(e) to each of U.S. Provisional Patent Applications No. 60/630,336 filed on Nov. 22, 2004, No. 60/683,397 filed on May 20, 2005, and No. 60/717,073 filed on Sep. 13, 2005, the entire disclosure of each of which is incorporated herein by reference for all purposes.
The present invention relates to the design of asynchronous circuits and systems. More specifically, the present invention provides techniques for the synthesis and optimization of multilevel domino asynchronous pipelines.
Synchronous design using a global clock is the mainstream design style for VLSI circuits, e.g., ASICs. Implementing this methodology, however, is becoming more difficult as CMOS technology scales into deep submicron, and as process spread, leakage power, and wire delays are all on the rise. Consequently, the gap between fullcustom and semicustom performance is increasing, motivating the investigation of alternative methodologies. In particular, asynchronous design has been shown to dramatically improve performance because of the lack of a global clock, the ability to easily borrow time from one pipeline stage to another, and the advantages of domino logic. Moreover, asynchronous design has also demonstrated other potential benefits in terms of low power and reduced electromagnetic interference. These advantages have recently renewed interest in the development of design techniques for highperformance asynchronous circuits. However, the quality or outright lack of appropriate synthesis and optimization tools presents an obstacle to the wide spread application of such techniques.
While several approaches have been proposed for the design automation of asynchronous circuits, few have been successful in realizing the performance benefits promised by asynchronous designs.
According to embodiments of the invention, techniques for optimizing a circuit design are provided. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a first number of buffers is added to selected stages of the pipelines such that the pipelines are balanced, at least one performance constraint is satisfied, and an objective function characterizing the circuit design is minimized.
According to other embodiments of the invention, a design flow is provided which enables asynchronous circuit designers to employ a conventional synchronous computer aided design (CAD) tool (e.g., tools from Synopsys or Cadence) and transform the gatelevel result into a multilevel domino logic asynchronous design. According to specific embodiments, methods and apparatus are provided for synthesizing a circuit which includes asynchronous logic from a netlist generated by a synchronous computeraided design tool. Synchronous logic gates represented by the netlist are converted to asynchronous logic gates. Clock circuitry represented by the netlist is replaced with asynchronous control circuitry and completion control circuitry thereby generating a plurality of asynchronous pipelines including the asynchronous logic gates. A plurality of buffers corresponding to a specific design template is inserted into selected ones of the asynchronous pipelines to normalize path lengths through the asynchronous pipelines thereby achieving a level of performance. Selected ones of the buffers are removed in a manner dependent on the specific design template to reduce overhead associated with the asynchronous logic with substantially no impact on the level of performance.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
Reference will now be made in detail to specific embodiments of the invention including the best modes contemplated by the inventors for carrying out the invention. Examples of these specific embodiments are illustrated in the accompanying drawings. While the invention is described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In addition, well known features may not have been described in detail to avoid unnecessarily obscuring the invention.
Currently there are no commercially available design tools specifically intended for asynchronous circuits. That is, asynchronous circuits are typically designed using fully custom flows. Specific embodiments of the present invention enable asynchronous circuit designers to employ conventional synchronous design tools (e.g., such as those available from Synopsys or Cadence) and then transform the gatelevel result into an asynchronous design based on multilevel domino logic. According to specific embodiments, synchronous logic (represented by a netlist generated using a synchronous CAD tool) is transformed to domino logic, adding asynchronous control and completion detection, and performing slack matching to optimize the design.
According to various implementations, transformation techniques implemented according to the present invention may be integrated with synchronous CAD tools to varying degrees. That is, for example, the synchronous CAD tool may be employed up until the point at which a synchronous netlist is generated with all steps of the subsequent transformation being conducted outside of the synchronous tool in an independent translator CAD environment. Such an approach is advantageous in that no augmentations or special features need to be introduced into the synchronous CAD tool. In addition, this enables the technique to be simultaneously compatible with a variety of synchronous CAD tools. Alternatively, at least some of the transformation may be conducted within the synchronous CAD tool environment by leveraging exposed APIs to provide extensions which are operable read the tool's database and perform the transformations described herein.
In addition, as will become clear, the slack matching techniques described herein are not limited to the logic synthesis techniques described herein. That is, the slack matching techniques described herein may be applied in a wide variety of contexts to optimize asynchronous circuit designs. Broadly speaking, slack matching takes a gate level circuit (not necessarily multilevel domino logic) and creates an optimization problem which, subject to some set of constraints, generates a slackmatched circuit (i.e., a circuit in which pipelines in a given level are balanced) with a minimum number of additional buffers. According to specific implementations, the optimization problem is solved using linear programming (LP) or mixed integer linear programming (MILP) solutions. As a first pass, buffers are added so that the length of the different paths through a given level are equal. Then, unnecessary buffers are removed while ensuring that there are no “wire throughs.” The LP/MILP approach to slack matching described herein is to be contrasted with socalled “branch and bound” algorithms which have been used to optimize asynchronous circuits, but are too computationally expensive for large circuits. The LP/MILP techniques described herein are less computationally expensive because, while “branch and bound” algorithms are exponential algorithms, LP/MILP algorithms may be accomplished, in some cases, in polynomial time.
Specific embodiments of the present invention will now be described which apply synchronous logic synthesis tools to produce multilevel domino asynchronous pipelines. Initially, standard logic synthesis tools are applied to a standard register transfer language (RTL) specification using a special image library comprising singlerail gates with timing arcs corresponding to their dualrail equivalents. Slack matching is applied to produce a levelized singlerail netlist. The levelized singlerail netlist is translated into a dualrail multilevel domino circuit by expanding each singlerail gate into its dualrail equivalent, and adding pipeline control.
Synchronous RTL specifications are useful in that they allow designers to ignore timing when considering system function. The resulting circuits are generally small and efficient, but due to the limitations of static CMOS circuits have limited performance. Asynchronous circuits such as dualrail domino pipelines offer higher performance, but must properly order the sequence of precharge and evaluate phases of each stage. A specific embodiment of the invention strikes a balance between these benefits of synchronous and asynchronous circuits.
The starting place of a design flow in accordance with a specific embodiment of the invention is the same as many synchronous design flows as illustrated in
According to a specific embodiment, a singlerail image of a dualrail library of gates is generated and used with a conventional synchronous logic synthesis technique. To create a gate image, map dualrail timing arcs are mapped to synchronous equivalents, taking the maximum of multiple dualrail arcs where necessary. This mapping is described in further detail below.
During levelization, the maximum distance to all of the loads for each output pin of a gate is calculated and a buffer chain with one buffer per stage is generated to create a fully balanced pipeline.
A pipeline is a linear sequence of functional stages where the output of one stage connects to the input of the next stage. For synchronous pipelines, the tokens usually advance through one stage on each clock cycle. For asynchronous pipelines, there is no global clock to synchronize the movement. Instead, each token moves forward down the pipeline when there is an empty cell in front of it. Otherwise, it stalls. A deterministic pipeline is generally partitioned into a set of stages each controlled by a different control signal. In order to ensure correct operation, it is necessary to insert buffers along paths that would otherwise constitute a wire going through an entire pipeline stage. In
According to various embodiments of the invention, slack matching is used to analyze logic gates and identify which paths (also referred to herein as channels), if any, need additional buffers (dynamic slack). Many approaches recently proposed for slack matching are applicable only to linear structures even though real systems typically have nonlinear structures such as forkjoin and loop structures in their systems. One implementation of the present invention counts stages and makes sure they always match up along forking and rejoining paths, and around state loops.
According to this implementation, it is assumed that a circuit does not have any handshake bottlenecks to begin with and all channels are unconditional, which may overslackmatch cells with conditional channels. All cell types in the hierarchy are processed, adding the minimum amount of slack to each local channel. The cell types are processed from the lowest level to the highest. Extensions to handle conditional behaviors are described below.
As each cell is processed, the subcells and channels are used to formulate a linear programming problem which minimizes the total cost of additional slack subject to constraints on the timing of all channels. For a linear programming solver, the constraints on each channel are as follows:
(dstCell.time+dstTime)−(srcCell.time+srcTime)=slack (Eq.1),
where dstCell.time, srcCell.time, and slack are independent variables, and dstTime and srcTime are constant time offsets specified on the ports of leaf cells. In addition, all primary inputs and outputs are constrained to have the same time stamp which is necessary to ensure the result can be mapped to a multilevel domino pipeline as discussed below. For each midlevel cell in the hierarchy, the time offset (in stages) of all input and output ports and slack depth, the number of stages between the earliest input and the latest output, which is the longest latency of the cell, are generated by slack matching.
If a channel generates tokens after reset (i.e., a Token Buffer), this is declared with ‘initial_tokens’. Channels with initial tokens are treated as if they have a latency of ‘cycle_{13 }slack*initial_tokens’, since the first output token actually leaves before the first input token arrives.
The slack helps identify the number of buffers that must be added to the channel to achieve the target cycle time subject to the specific asynchronus design template. In the multilevel domino style, the restriction is that no feed through wires in a pipeline stage are allowed. Thus, for each nonzero slack that spans a pipeline stage, one buffer is needed to be added in that pipeline stage.
Moreover, in the multilevel domino pipeline, channels can share buffers, unlike in other channelbased design styles, including those consisting of half and fillbuffers described later in this document. In particular, if two channels need slack eminating out of one gate, the slack required in these channels can share the same buffers. In particular, a chain of buffers can be created and forked off to different fanouts depending on how much slack is needed to that fanout.
The basic idea for dualrail conversion is that every singleoutput combinational gate is translated to an equivalent dualrail gate as illustrated by the example in
The asynchronous library can be quite small because inverters on the inputs and outputs come for free so that many gates typical in a synchronous library need no counterpart in the asynchronous library. For example, NAND gates in
Assuming the number of levels of logic per pipeline stage is 2 as shown in
The Completion Detection circuits make a tree of AND gates using 8input trees as shown in
Thus, specific embodiments of the present invention provide an efficient logic design flow for asynchronous circuits supported by commercial CAD tools, e.g., tools from Cadence, Synopsys, Magma. Synchronous circuits are translated into asynchronous circuits after logic synthesis using any of the wellknown logic synthesizers. Slack matching is applied for the levelized pipeline which is then expanded into dualrail multilevel domino circuits.
According to various embodiments, a variety of approaches to slack matching may be employed. According to one set of embodiments, a mixed integer linear programming (MILP) solution is employed. It should be noted that, while the ILP solution described herein may be used with the logic synthesis technique described above, it is not limited to that technique. To the contrary, the slack matching technique described below is widely applicable and may be employed in the context of a wide variety of asynchronous and more generally, latencyinsensitive design flows. The class of asynchronous designs particularly useful are those slackelastic designs in which the addition of pipeline buffers does not affect functional correctness.
As described above, slack matching is the problem of adding pipeline buffers to an asynchronous pipelined design in order to prevent stalls and improve performance. The MILP solution described below addresses the problem of minimizing the cost of additional pipeline buffers needed to achieve a given performance target.
According to one set of embodiments, the asynchronous design style context of this sizing tool is characterized by the communication of data between blocks via channels instead of by clocking data into shared registers. Data wires run from the sender to the receiver, and an enable (an inverted acknowledge) wire goes backward for flow control. A fourphase handshake between neighboring blocks (processes) implements a channel. The four phases are in order: 1) Sender waits for high enable, then sets data valid; 2) Receiver waits for valid data, then lowers enable; 3) Sender waits for low enable, then sets data neutral; and 4) Receiver waits for neutral data, then raises enable.
The asynchronous design style is further characterized by the partitioning of asynchronous datapaths into bitslices and pipelining between bitslices to achieve higher throughput. It employs a set of leaf cell template that are the smallest components that operate on the data sent using the above asynchronous handshaking style and are based upon a set of design templates with low latency and high throughput. Examples of such leaf cell templates include the Precharged HalfBuffer (PCHB), the WeakCondition Half Buffer (WCHB), and the Precharged Full Buffer (PCFB). These templates all have one or two completion detection units, domino logic for the computation of output data, and asynchronous control circuitry dictating when to precharge/evaluate the domino logic and when to raise and lower the enables for the input channels. Each leaf cell may operate on 18 bits of data and when combined with standard pipelining between functional boundaries, this creates a complex 2dimensional pipeline which must be balanced to guarantee optimal performance.
For further detail regarding this design style and these templates please refer to the following papers: A. J. Martin, “Compiling Communicating Processes into DelayInsensitive Circuits,” Distributed Computing, Vol. 1, No. 4, pp. 226234, 1986; U. V. Cummings, A. M. Lines, A. J. Martin, “An Asynchronous Pipelined Lattice Structure Filter.” Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, 1994; A. J. Martin, A. M. Lines, et al, “The Design of an Asynchronous MIPS R3000 Microprocessor.” Proceedings of the 17th Conference on Advanced Research in VLSI, IEEE Computer Society Press, 1997; and A. M. Lines, “Pipelined Asynchronous Circuits.” Caltech Computer Science Technical Report CSTR9521, Caltech, 1995; the entire disclosure of each of which is incorporated herein by reference for all purposes. See also U.S. Pat. No. 5,752,070 for “Asynchronous Processors” issued May 12, 1998, and U.S. Pat. No. 6,038,656 for “Pipelined Completion for Asynchronous Communication” issued on Mar. 14, 2000, the entire disclosure of each of which is incorporated herein by reference for all purposes.
It should also be understood that the various embodiments of the invention may be implemented in a wide variety of ways without departing from the scope of the invention. That is, the processes and circuits described herein may be represented (without limitation) in software (object code or machine code), in varying stages of compilation, as one or more netlists, in a simulation language, in a hardware description language, by a set of semiconductor processing masks, and as partially or completely realized semiconductor devices. The various alternatives for each of the foregoing as understood by those of skill in the art are also within the scope of the invention. For example, the various types of computerreadable media, software languages (e.g., Verilog, VHDL), simulatable representations (e.g., SPICE netlist), semiconductor processes (e.g., CMOS, GaAs, SiGe, etc.), and device types (e.g., FPGAs) suitable for the processes and circuits described herein are within the scope of the invention.
This task of balancing pipelines is complicated because the designs are often organized and layed out hierarchically to manage complexity. A very simple WCHB buffer is a buf1of1 which pipelines a simple synchronization channel. Its input channel data (enable) is L (Len), while the output channel data/enable is R (Ren).
The performance a leaf cell can be measured in terms of latency and local cycle time. The latency of a leafcell is the delay through the leaf cell when the output channel is empty. For a buf1of1 circuit the latency is through the Celement and inverter and can be approximated as two gate delays. When several leaf cells form a linear pipeline the throughput of the system is the reciprocal of the worstcase cycle time of any set of neighboring leaf cells. In particular, the handshaking protocol between neighboring leaf cells dictates the frequency that the leaf cells can generate new tokens and is referred to as the local cycle time. In particular, typical leafcells have local cycle times of 618 transitions depending on the specific leafcell template and the amount of processing the leafcell implements. It is important to note that unlike in synchronous systems, the local cycle time is often larger than the latency of a given leafcell as it takes some time for the handshaking protocol to reset. In particular, typical leaf cells have a forward latency of only 2 transitions. The difference between the local cycle time and the forward latency is often referred to as the backward latency.
In nonlinear pipelines leaf cells can have more than one input and output channels. Fork stages have multiple output channels and join stages have multiple input stages. In a join stage, the leaf cell waits for all tokens to arrive before generating the output tokens and thus acts as a synchronization point. A nonlinear pipeline stage is unconditional if it reads a token from every input channel and generates a token on every output channel in every cycle. It is conditional otherwise, that is, if it can read a subset of input channels or generate tokens on a subset of output channels depending on local state or the token value read among other channels.
To gain intuition to the slack matching problem, consider the special homogeneous case that all leafcells have the same latency l_{c }and local cycle time τ_{c }and the goal is to obtain a global cycle time that is equal to the local cycle time. This will then be generalized this to the nonhomogeneous case.
A key observation is that if tokens arrive at a join stage at different times, the early token will stall and the stall will propagate backwards and slow the entire system down. This may be illustrated with the classic unbalanced forkjoin pipeline structure shown in
This intuition is a necessary condition for the global cycle time to be equal to the local cycle of the channels. It is not however sufficient. To see this, consider another important case when a token can propagate around a loop of leaf cells faster than the local cycle time. In this case a token will be stalled while the local channel resets. Like the above case, this stall will propagate backward and increase the global cycle time. In particular, it is the backward propagation of empty places for tokens to move into (so called bubbles) that becomes the throughput bottleneck. As an example, consider the simple 4stage ring illustrated in
Alternatively, if the latency around a onetokenloop is larger than τ, the cycle time will necessarily be greater than τ. Consequently, another necessary condition is that for onetoken loops the propagation delay along every cycle is equal to local cycle time. Multitoken loops, with multiple token buffers, yield a generalization of this condition. Specifically, for the global cycle time to equal the local cycle time, the latency along any mtokenloop must be m τ.
Together these two conditions are necessary and sufficient under a reasonably general performance model.
Now consider the case in which one channel can reset faster than others, i.e., it has a smaller backward latency. If a token is stalled in this channel by a small amount, the channel may still be able to reset in time to accept the next token within the desired global cycle time. If the forward latency+stall time+backward latency=the desired global cycle time, then this stall will not bottleneck the design. Consider the modified forkjoin example in
In addition, to meet the desired global cycle time, stalls caused by the backward propagation of bubbles must be less than the sum of the free slack around the cycle. To illustrate this, consider the modified 4stage ring in
While there is no way to avoid long latency loops, in all remaining cases, the throughput of the design can be increased by adding pipeline buffers to the system such that tokens and bubbles are not overly stalled.
The following description introduces a mixed integerlinear programming (MILP) framework which may be used to solve the slackmatching problem for nonhierarchical systems as well as extensions to support hierarchy.
The general approach of the MILP is to constrain the relative timing of arrival times of tokens at leafcells and allow pipeline buffers to be added to channels that effectively increase the latency between leaf cells in terms of added latency and freeslack. The cost of the added slack can then be minimized subject to these constraints as follows:
Where l_{ij}, τ_{ij}, and f_{ij }are the latency local cycle time, and free slack of channel c between leaf cell instances i and j; a_{i }are free variables representing the arrival time of tokens at leaf cells, where there are as many ai variables as leafcell instances; s_{ij }are independent variables that identify the amount of slack added to channel c between leaf cell instances i and j; l_{s }and τ_{s }is the latency and local cycle time of a pipelined buffer; m=1 if this channel upon reset has a token and 0 otherwise; and c(s_{ij}) represents the cost of one pipeline buffer added to channel c between leaf cell instances i and j.
The channel constraints guarantee that the density of data tokens along a loop of leaf cells is sufficiently low such that no token is stalled waiting for any channel to reset and that the latency along the loop is not too high such that leaf cells are never starved. In particular, for any loop of leaf cells, the equations guarantee that the latency+free slack around the loop is equal to the number of tokens in the loop times the desired cycle time as calculated by the sum of m τ along the loop. Because the free slack is greater than 0, the equations are not feasible in the case that the throughput is less than τ, as expected. In addition, the constraints guarantee that the sum of the freeslack along the short path of a forkjoin path is sufficient to balance the two paths. Notice that the freeslack of a channel, as constrained by the freeslack constraints, is upper bounded by the sum of two components. The first of the two components is the freeslack associated with the difference in the cycle time of the channel and the target cycle time, τ−τ_{c}. The second component of the freeslack is the slack obtained by adding s_{ij }number of pipeline buffers, each contributing τ−τ_{s }amount of slack. Note that we restrict s_{ij }to be integral because there is no such thing as a fraction of a pipeline buffer that can be added to a channel. Finally, note that c(s_{ij}) may depend on the physical size of the pipeline buffer and/or the width (i.e., number of rails) of the channel.
As an example, the MILP for the nonhomogeneous forkjoin pipeline is as follows:
In the example illustrated in
In either case, the set of free variables in the MILP includes one slack variable for each unique location that slack can appear in the hierarchical design and one time variable for each leafcell instance. There is also one channel and freeslack constraint for each channel instance. The channel constraints are instance based rather than type based because the timing of different instances of the same type of leafcell will often be very different. In addition, the freeslack constraint is instance specific because the amount of slack each channel needs to absorb may also vary from instance to instance.
Referring now to the flowchart of
There are many formats for which MILP problems can be defined, including CPLEX LP and MPS formats. CPLEX LP has a variety of key words, including minimize and subject to with their standard meanings that makes specification of the MILP problem natural. Pseudocode that takes as input a hierarchical design and writes out the CPLEX LP formulation of the MILP problem as follows.
WriteILP(design, CPLEXfile) {  
WriteObjFunction(design,CPLEXfile);  
WriteConstraints(design,CPLEXfile);  
}  
WriteConstraints(design,CPLEXfile) {  
allChannels = design.getAllChannelInstances( );  
CPLEXfile.write(“subject to\n”);  
foreach (channel chan in allChannels) {  
// emit channel constraint a_{i }= a_{j }− m τ + f_{c }+ l_{ij }s_{ij}  
CPLEXfile.write(“a” + chan.dstCell.timeIndex + “=”);  
CPLEXfile.write(  
“ a” + chan.srcCell.timeIndex +  
“− ” + chan.initialTokens*τ );  
foreach (subchannel sc in chan) {  
CPLEXfile.write(  
“ + f” + sc.freeSlackIndex  
“ + ” + sc.slackLatency + “ s” + sc.slackIndex);  
}  
CPLEXfile.write(“\n”);  
// emit freeslack constraint f_{c }≦ τ − τ_{ij }+ s_{ij}(τ − τ_{s})  
CPLEXfile.write(  
“f” + chan.freeSlackIndex + “ ≦ ” + chan.freeSlack)  
foreach (subchannel sc in chan) {  
CPLEXfile.write(  
“ + ” + sc.freeSlack + “ s” + sc.slackIndex );  
}  
CPLEXfile.write(“\n”);  
// constrain slack to be nonnegative  
foreach (subchannel sc in chan) {  
CPLEXfile.write(  
“0 ≦ s” + sc.slackIndex + “\n”);  
}  
// constrain slack to be integral  
CPLEXfile.write(“General\n”);  
foreach (subchannel sc in chan) {  
CPLEXfile.write(  
“s” + sc.slackIndex + “\n”);  
}  
CPLEXfile.write(“End\n”);  
}  
}  
WriteObjFunction(design,CPLEXfile) {  
allChannels = design.getAllChannelInstances( );  
CPLEXfile.write(“minimize\n”);  
foreach (channel chan in allChannels) {  
foreach (subchannel sc in chan) {  
CPLEXfile.write(“ + ” + sc.cost + “ s” +  
sc.slackIndex +“\n”);  
}  
}  
Notice the object oriented nature of the design. Channel, and subchannel data structures which implicitly contain their associated freeslack, latency, and local cycletimes, are assumed available through the “dot” notation. Finally notice that it is implicit in the file that all independent variables are nonnegative. Once the MILP problem file is generated, the main program calls an external MILP solver and reads the results file to automatically add slack to the design.
The domain of the latency and cycle time values must be somewhat constrained in order for an integral solution to exist. In particular, if the pipeline buffers do not have sufficient freeslack or have arbitrary realvalued latency and cycle times, there may be no integral number of added pipeline buffers which satisfies all constraints. One way to increase the probability an integral solution exists is to replace fixed latency of the pipeline buffers with bounded latencies that can then be controlled by transistor sizing while maintaining a worstcase cycle time τ_{s}. Conditions in which the integer condition can be dropped and linear programming approaches can be used to solve this problem will be discussed below.
Note that as a sideproblem of the MILP minimization problem is the problem of performance verification of a channelbased asynchronous circuit in which we set all slack variables to 0 and determine if the set of equations are feasible. Our first result is that we can verify that a circuit satisfies the cycle time by checking if the above system of linear equations has a feasible solution. There exists a plethora of existing tools and techniques that solve this problem, including the wellknown Simplex algorithm applicable to the LP system as described below, and we believe that these solutions may be at times faster than applications of Karp's theorem.
Similarly, another related problem is the problem of performance analysis of a channelbased asynchronous circuit in which we set all slack variables to 0, make the constant τ an independent variable, and minimize r subject to the modified set of constraints. Notice that the freeslack constraints f_{ij}≦τ−τ_{ij}+s_{ij}(τ−τ_{s}) reduces to f_{ij}≦τ−τ_{ij }and the approach reduces to a linear programming (LP) problem. This LP problem can be solved with many wellknown algorithms and may yield faster runtimes than the traditional approach using Karp's theorem.
The performance analysis of asynchronous designs has commonly used Petri Nets. The following provides a background on Petrinets such that we can then formulate the pipeline optimization problem in terms of subclasses of Petrinets called Marked Graphs. After defining timed Marked Graphs, the theoretical relationship between the performance of the system and the nonnegative solution is developed to a proposed linear system of equations. For a more general introduction to Petri Nets we refer the reader to J. L. Peterson, Petri Net Theory and the Modeling of Systems, PrenticeHall, 1981, and T. Murata, Petri nets: properties, analysis and application, Proc. of the IEEE, vol. 77, no. 4, pp. 541579, 1989, the entire disclosures of which are incorporated herein by reference for all purposes.
A Petri net is a fourtuple N=(P, T, F, m_{0}) where P is a finite set of places, T is a finite set of transitions and F⊂(P×T)∪(T×P) is a flow relation, and m_{0}ε
^{P} is the initial marking. A Petri net is usually represented as a bipartite graph in which P and Tare the nodes. For any two nodes x and y, if (x, y)εF then there is an arc from x to y.A marking is a token assignment for the place and it represents the state of the system. Formally, a marking is a Pvector m, where the number of tokens in place p under marking m, denoted by m(p), is a natural number. We say for an element xεP∪T, that •x is the preset of x defined as •x={yεP∪T(y, x)εF} and x• is the postset of x defined as x•={yεP∪T(x, y)εF}. A transition t is enabled at marking m if each place in •x is marked with at least one token. When a transition t is enabled, it can fire by removing one token from each place •x and adding one token to each place x•.
A marking m′ is reachable from m if there is a sequence of firings t_{1 }t_{2 }. . . t_{n }that transforms m into m′, denoted by m[t_{1 }t_{2 }. . . t_{n}>m′. A sequence of transitions t_{1 }t_{2 }. . . t_{n }is a feasible sequence if it is firable from m_{0}. The set of reachable markings from m_{0 }is denoted by [m_{0}>. By considering the set of reachable markings as the set of states of the system, and the transitions among these markings as the transitions between the states, a reachability graph can be obtained representing the underlying behavior of the PN. A PN is mbounded if no marking in [m_{0}>assigns more than m tokens to any place of the net. It is safe if it is 1bounded.
A marked graph (MG) is a type of Petri net in which every place has at most one input and output transition, i.e., •p≦1
p•≦1, ∀pεP. A timed MG is a MG in which delays are associated with transitions. We instead associate a delay with every place d(p) because the models are more intuitive for our purposes and less constrained. That is, every MG with delays associated with transitions can be translated into one in which this delay is instead associated with all places in its preset •t. Because each place has at most one transition in its postset no ambiguity in place delays exist. A cycle c is a sequence of places p1 p2 . . . p1 connected by arcs and transitions whose first and last place is the same.The cycle metric (CM(c)) is the sum of the delays of all associated places along the cycle c, d(c), divided by the number of tokens that reside in the cycle, m(c), i.e., CM(c)=d(c)/m_{0}(c). The cycle time of a MG is defined as the largest cycle metric among all cycles in the timed MG, i.e., max ∀cεC [CM(c)], where C is the set of all cycles in the timed MG. The intuition behind this wellknown result is that the performance of any computation modeled with a timed MG is dictated by the cycle time of the timed MG and thus the largest cycle metric. There are many algorithms and approaches to solve this problem and we refer the reader to A. Dasdan. “Experimental Analysis of the Fastest Optimum Cycle Ratio and Mean Algorithms”, ACM Transactions on Design Automation of Electronic Systems, Vol. 9, No. 4, October 2004, Pages 385418 for a detailed review and comparison.
We first present properties of timed marked graph which are the theoretical basis of our slack matching algorithms. In particular, we define a set of equations which captures a feasible schedule of the timed marked graph by defining the arrival time of all transitions and the freeslack of every place.
We first define cycles in their vector format and prove a related lemma. A simple cycle is a {0, 1} vector c of length P for which cA_{T}=0 where A_{T }is the first T columns of A. A cycle is a nonnegative vector d of length P for which dA_{T}=0. Notice that all simple cycles are also cycles and that a cycle can always be represented as a positively weighted sum of simple cycles. Let C represent the set of all simple cycles of A in matrix form, one cycle per row. Then notice that all cycles have cycle metrics less than τ is equivalent to saying in matrix form Cb≦0.
Lemma 1 If wC=y for some w and y≦0, then there exists ŵ≦0 s.t. ŵC=y.
Proof: We use a negative form of the theorem of the separating hyperplane applied to the system of linear equations C^{T}w=y which states that either there exists a nonpositive solution to C^{T}ŵ=y or there exists a z such that zC^{T}≦0 and zy<0. Our approach is to assume zC^{T}≦0 and prove that zy≧0. We first decompose y=wC into the subtraction of two cycles y=d_{p}−d_{n }where d_{p }is the sum of the cycles corresponding to the positive elements of w and d_{n }is the sum of the cycles corresponding to the negative elements of w and observe that since y≦0 we must have d_{n}≧d_{p}. We then observe that zy=z(d_{p}−d_{n})=zd_{p}−zd_{n}. Finally, because d_{n}−d_{p}=d must be a cycle, that zd_{n}=zd_{p}+zd and because zC^{T}≦0 we must have zd≦0. We conclude that zd_{n}≦zd_{p }and thus that zy≧0. QED.
The above lemma states that any nonpositive vector y that is a (possibly mixed) weighted sum of cycles can also be expressed as a nonpositive weighted sum of simple cycles. This lemma will be useful in proving our first theorem.
Theorem 1. Cb≦0 if and only if A x=b has a nonnegative solution.
Proof: We will proof each half of the if and only if aspects of this theorem separately.
(if) Assume A x=b has a nonnegative solution. Then consider a cycle c in vector form. cb equals the sum of d(p)−τm_{0}(p) for all pεP along the cycle c, i.e., d(c)−τm_{0}(c). In addition, cAx equals the negative sum of the free slack x(p) along c. Because each free slack variable x(p) must be nonnegative, this sum must be less than or equal to 0, i.e., cAx≦0. Since Ax=b, we know that cAx=cb and conclude cb≦0.
(only if) We use the theorem of the separating hyperplane which states that either there exists a nonnegative solution to Ax=b or there exists a y such that yA≧0 and yb<0. In particular, we show that if Cb≦0 for any y for which yA≧0 yields yb≧0. To do this, partition A such that yA=[yA_{T }yA_{P}] and observe that for yA≧0, we must have that yA_{T}≧0. For yA_{T}≧0, y must represent a possibly mixed linear combination of simple cycles y=wC because otherwise an odd edge would cause the entry in yA_{T }corresponding to the source transition of the edge to be negative. Using Lemma 1 we conclude that y can also be expressed as a nonpositive linear combination of cycles y=ŵC, where ŵ≦0. This implies that yb equals the negative of the linear combination of cycle freeslack—Σ_{i}ŵ_{i}f(c_{i}) because yb is the sum of d(c_{i})−τm_{0}(c_{i}) weighted by the nonpositive value ŵ_{i }for each cycle c_{i}. Since Cb≦0 implies that all cycle free slacks are nonnegative, we conclude that yb≧0. QED.
The above theorem implies that the cycle metrics are all less than the desired target cycle time if and only if there exists a nonnegative set of arrival times and freeslacks which satisfies the arrival time equation. The arrival times represent a periodic schedule for all transitions which meets the dependency constraints of the system and the target cycle time. The nonnegative freeslack on a place indicate by how much the token in the place should be delayed before firing. Notice that this schedule may imply that some transitions may be delayed past the time when all tokens are available at its input places.
Note that a similar linear programming model was originally proposed by Magott to determine the minimum cycle time of a timed marked graph. In Magott's LP model, the freeslack variables were removed and the arrival time equation was reduced to the following inequality:
a _{j} ≧a _{i} +d(i)−τm _{0}(p)
This is a simpler and more efficient linear program when minimizing τ. For our purposes, however, it is critical to explicitly include the freeslack variables which can then be further constrained. We also note that in Magott gave no formal proof of the correctness of the LP problem and thus include Theorem 1 for completeness.
In the following discussion, we assume that each leafcell is a full buffer. We define a specific form of a Timed Marked Graph to model the system and identify the relationship between the cycle time of this system and a constrained system of linear equations in which the impact of additional pipeline buffers (slack) can be modeled. With this model we justify the MILP formulation of the slack matching problem. These results will be generalized to systems with a mixture of half and full buffers.
We model the hierarchical network of leaf cells with a novel Timed Marked Graph called a Full Buffer Channel Net (FBCN) defined as follows N=(P∪
The performance of the network is represented by modeling the performance of the channels as they are connected to the leafcells. In our model, the local cycle time is attributed to the output channels to which the leafcell is connected. d(p) represents the forward latency of a channel while the corresponding d(
As an example, we illustrate two channels in
We model the hierarchical nature of the design by associating a celltype with each transition celltype(t). Channels of course may cross cellhierarchy as illustrated in
The cycle time of the circuit is captured by the maximum cycle metric of the corresponding FBCN. The throughput of the circuit is the reciprocal of this value. Very often the additional buffers, also known as slack, must be added to the model to improve the cycle time to balance the pipelines. We model the addition of slack between by creating new transitions that represent buffer leafcells and corresponding channels in such a way to improve the performance of the design.
As an example, consider a homogeneous nonlinear pipeline forkjoin channel structure in which there are three buffers in one path and one buffer in the other path. The FBCN model of this structure is illustrated in
If a second buffer was inserted in the short forked path as illustrated in
Theorem 1 can directly be applied to our FBCN because the FBCN is a Timed Marked Graph. It implies that the complete slack linear system of equations applied to the FBCN are necessary and sufficient conditions for the global cycle time to also be less than the target cycle time. While an important result, it by itself does not directly yield an algorithm for slack matching because it is not easy to model the addition of slack to resolve performance bottlenecks within this framework. Fortunately, this system of linear equations can be simplified in such a way that allows modeling the impact of additional slack within a linear programming framework. In particular, this complete slack linear system can be reduced by omitting all constraints specific to the backward places
for all pεP A_{r}(p, t_{i})=−1 and A_{r}(p,t_{j})=1 and A_{r}(p,p)=−1
Theorem 2: Cb≦0 if and only if A_{r}x_{r}=b_{r }has a nonnegative solution in which ∀pεP x_{r}(p)≦τ−c(p∘
Proof: We will proof each half of the if and only if aspects of this proof separately.
As an example of this theorem, the reduced slack linear system for our nonn homogeneous unbalanced forkjoin pipeline in
Please note that the fact that this matrix is square is a coincidence. If, for example, the fifth channel had no free slack it would be an overconstrained system with more rows than columns. As is, this system of linear equations does have a nonnegative solution x_{r}=[8 0 2 4 6 0 4] which also satisfies the constraints f_{5}≦4 and thus the system has a cycle time of no more than 10. This is consistent with our intuitivebased analysis of this example.
The importance of Theorem 2 is that the backward places and corresponding freeslack can be removed from the formulation which makes representing the impact of additional freeslack straightforward. In particular, note that the set of constraints proposed above is the same but applied to a parameterized system A_{p}x_{p}=b_{p }in which slack can be added to each channel. Each possible slack configuration has an associated FBCN model and thus must adhere to the constraints of Theorem 2 in order to meet the global cycle time. Consequently, Theorem 2 shows that, under the fullbuffer model of computation, the proposed MILP constraints are necessary and sufficient for the parameterized system to satisfy the global cycle time. More simply this means that the proposed MILP framework yields the optimum slack matching result when all leaf cells are full buffers.
The FBCN model assumes that each leaf cell is a full buffer. However, some of the most common leaf cell templates are in fact so called half buffers. Unlike full buffers, half buffers cannot have a token at the output and input channels simultaneously. Thus, a linear pipeline of N half buffers can hold a maximum of N/2 tokens. In this section we describe a mixed channel net (MCN) model of the circuit and describe changes to the theory and MILP that properly take into consideration circuits made up of both half buffers and full buffers. In particular we show that each halfbuffer in the model yields an additional constraint on the sum of the free slacks of the associated input and output channels.
Petri net models for pipelines with half buffers are shown in
More formally, a Mixed Channel Net (MCN) is defined as a timed Petri Net N=(P∪
We first define an enhanced full system of linear equations which define the performance of the mixedbuffer design. For each halfbuffer place
a _{i} =a _{j} +d(
The enhanced matrix representation be A_{m}x_{m}=b_{m }and let C_{m }represent all simple cycles in the mixed graph. With straight forward modifications to the proof of Theorem 1, we conclude a similar statement for this enhanced system of linear equations:
Theorem 3: C_{m}b≦0 if and only if A_{m}x_{m}=b_{m }has a nonnegative solution.
Moreover, the halfbuffer equation can be simplified by summing the other forward constraints on a_{j }and a_{i}.
a _{k} =a _{i} +d(p _{ik})−τm _{0}(p _{ik})+f _{p} _{ ik }
a _{j} =a _{k} +d(p _{kj})−τm _{0}(p _{kj})+f _{p} _{ kj }
to get
a _{j} =a _{i} +d(p _{ik})−τm _{0}(p _{ik})+f _{p} _{ ik } +d(p _{kj})−τm _{0}(p _{kj})+f _{p} _{ kj }
and realizing that this reduces to the following constraint on the sum of the free slacks on the two channels:
f _{p} _{ ik } +f _{p} _{ kj } =−d(
where the last simplification follows from the halfbuffer constraint on the initial marking. This means that requiring that the local cycle involving three neighboring buffers meet the target cycle time (i.e., that a positive f_{ p } exists) can be achieved by simply constraining the sum of the two component freeslacks as follows
f _{p} _{ ik } +f _{p} _{ kj } ≧τ−[d(p _{ik})+d(p _{kj})+d(
As an example, consider the three weakconditioned halfbuffer buf1of1 cells shown in
To formalize this analysis, we extend Theorem 2 to the MCN model. We define C_{ml }to be all local cycles in the mixed matrix model, including the local cycles representing the handshaking loop between three consecutive halfbuffers. We then extend our assumption that all local cycles satisfy the global cycle time to all cycles in C_{ml}. With this assumption, the enhanced system of linear equations that includes this halfbuffer timing equation represent necessary and sufficient conditions for satisfying the global cycle time as follows (the proof follows the same approach as in the proof of Theorem 2):
Theorem 4: C_{m}b≦0 if and only if A_{mr}x_{mr}=b_{mr }has a nonnegative solution in which
∀pεP x _{mr}(p)≦τ−c(p∘
∀
Theorem 4 provides the basis of a modified MILP program to support mixedbuffer systems. One issue associated with this solution is how to properly model the impact of additional pipeline buffers on the set of slack constraints and in particular the d(
Consider the case where there are s_{ij }identical halfbuffer slack cells on the channel connecting two stages i and j, followed by some stage k. The MCN model is shown in
l_{xy }= d(p_{xy})  Forward latency of some stage x along the 
channel connected to stage y.  

Firstorder (singlecell) backwards handshake delay from some stage y to the 
preceding stage x. In the fully general  
case, this delay depends on the properties  
of the stage k that follows y, so we will  
express it as a function of the sequence of  


order backwards handshake delay between  
a slack buffer and stage j, followed by k.  

Secondorder (doublecell) backwards handshake delay through some stage z, 
then y, then x. This parameter also  
depends on the timing properties of the  
three sequential stages, but no others. For  


order arc connecting stage j to stage i in  
the s_{ij }= case.  

Maximum free timing slack on the channel between stages x and y (followed by z) 
due to the firstorder handshake constraint.  

Maximum sum of the free timing slack between stages x and z due to the second 
order handshake constraint.  
S_{max}  Maximum number of slack buffers 
allowed on any channel in the system.  
That is, s_{ij }≦ S_{max}.  
f_{ij }(n)  Free timing slack on the nth slack stage 
between cells i and j, for n = 0 . . . s_{ij}.  

Total free timing slack on the channel between stage i and j. 
a_{i}, a_{j}  Arrival times of stages i and j. 
m_{ij }= τ · m_{0}(p_{ij})  Initial token count on the channel 
connecting stages i and j (expressed in  
units of the timing slack provided by the  
initial token, for notational clarity.) Either  
0 or τ.  
This MILP formulation gives the exact linear constraints relating variables a_{1}, a_{j}, f_{ij}(n), f_{jk}(0), s_{ij}, and s_{jk }to constant circuit properties such as l_{ij},
This formulation does not make any attempt to reduce the S_{max }f_{ij}(n) variables to a more manageable number. A variety of exact analytical simplifications and conservative approximations can be made to reduce the complexity of this formulation; one such approximation is described later.
The forward latency equality, relating a_{j }and a_{i}, requires the least modification from the full buffer model. It can be written directly as the sum of arrival time differences across the linear chain of buffers:
Note that since all slack buffer stages reset empty, there are no m_{s }terms to include.
All firstorder, singlestage cycles between neighboring stages x and y impose the following general constraint:
f _{xy} +l _{xy} +
Expressed in terms of the nomenclature defined above, this can be written more concisely as
f _{xy}≦μ(x,y,z).
Applying this to the first singlestage cycle in the array of slack buffers between i and j (labelled A in
The subsequent firstorder cycles (those labeled B in
Note that for n>s_{ij}, the corresponding slack buffers do not exist, so their free slack variables f_{ij}(n) are unused. The above constraint forces them to be zero so that the sum F_{ij }may be calculated over the unconditional set n=0 . . . S_{max}.
The secondorder, doublestage cycles spanning neighboring stages x, y, and z impose the following general constraint:
f _{xy} +f _{yz} +l _{xy} +l _{yz} +
which once again can be represented in a more abbreviated manner:
f _{xy} +f _{yz}≦λ(x,y,z).
Applying this to the first internal doublestage cycle beginning at stage i, illustrated in
Note that in the s_{ij}=0 case, the associated doublestage cycle does not exist, so this constraint must have no effect. Constraint B1B_C will ensure that f_{ij}(1)=0 when s_{ij}=0, so in this case B2A_C indeed reduces to the vacuous constraint f_{ij}(0)≦τ.
Next, the secondorder constraints imposed by the internal slacktoslack secondorder cycles can be written as follows (for n=1 . . . S_{max}):
Note that once again the constraint becomes vacuous for all nonexistent cycles.
Finally, the last secondorder cycle in the slack array between stages i and j must be constrained together with the first f_{jk}(0) term of the subsequent channel.
The above system of constraints exactly represents all timing relationships in the parameterized MCN circuit model presented above. However, the nonlinear conditional terms present in F_C, B1A_C, B1B_C, B1C_C, B2A_C, B2B_C, and B2C_C make the system unsuitable for MILP optimization. These nonlinear conditions must be reexpressed in a linear manner by introducing additional integer utility variables.
In particular, for each channel s_{ij }we will define binary slack enumeration variables, e_{ij}(n)ε{0,1}, constrained as follows:
The first constraint imposes that only a single e_{ij}(n) can be 1, with e_{ij}(m)=0 for m≠n, and the second constraint ensures that n=s_{ij}. With these enumeration variables, all constant conditional terms guarded by expressions such as s_{ij}=c can be represented as a multiplication of that constant by e_{ij}(c). Similarly, conditions such as s_{ij}>0 can be expressed as a multiplication by (1−e_{ij}(0)). Since such greaterthan conditions are common, we will define the following terms for notational clarity:
Next, inequalities B1A_C, B1C_C, and B2C_C involve crossdependencies between s_{ij }and s_{jk }which suggest a nonlinear product of e_{ij }and e_{jk }variables. Specifically, these inequalities reference four mutually exclusive cases:
Case 0: s_{ij}=0
s_{jk}=0Case 1: s_{ij}=0
s_{jk}>0Case 2: s_{ij}>0
s_{jk}=0Case 3: s_{ij}>0
s_{jk}>0Fortunately these cases can be represented in a linear manner by defining the binary variables c_{ij}(p)ε{0,1} for p=0 . . . 3 with the following constraints:
Another product of system variables arises in constraint F_C, in the l_{ss}(s_{ij}−1) expression guarded by the condition s_{ij}>0. A straightforward multiplication of (s_{ij}−1)l_{s}×g_{ij}(0) gives the product of variables s_{ij}·e_{ij}(0). We can work around this problem by applying the following general relation:
With these utility terms, we are now prepared to eliminate all nonlinear conditional expressions in constraints F_C, B1A_C, B1B_C, B2A_C, and B2B_C. However, constraints B1C_C and B2C_C involve a remaining unresolved nonlinearity: the variable indexing of f_{ij}(s_{ij})) To linearize this term, we must introduce an additional free slack variable f_{ij}′ which will be constrained such that it always equals the s_{ij}th free slack variable. Then we will use this f_{ij}′ variable in place of f_{ij}(s_{ij}). Specifically, f_{ij}′ is constrained as follows, for n=0 . . . S_{max}:
Together these two constraints ensure that f_{ij}′=f_{ij}(n) for n=s_{ij }and have no effect when n≠s_{ij }(since all f_{ij}(n)≦τ.)
With these results we can now formulate a linear system of constraints involving integer and real variables that exactly represents the timing behavior of the parameterized MCN circuit model:
All other utility variables are constrained as specified above.
We can also obtain a simpler MILP by replacing the individual f_{jk}′(n) variables with a single variable slack f_{ij}′. Both exact and approximate simplifications are possible. Exact simplifications are mathematically equivalent but use fewer variables. In particular, by avoiding f_{jk}′(n) variables the number of variables does not depend on the maximum slack allowed in a channel. Approximations of these equations are also possible to further simplify the system of equations and are based on a few other reasonable approximations.
First, by assuming that the sum of the latency between cell i and cell j through s_{ij }buffers is l_{ij}+l_{s}s_{ij}, the sum of arrival time constraint equation (F) can be reduced to
a _{i} =a _{j} −m τ+f _{ij} +l _{ij} +f _{ij} ′+l _{s} s _{ij},
where the latency of a channel emanating form a slack cell is assumed to be constant and referred to it as l_{s}.
Second, the native freeslack equations (B1A) can also be conservatively bound as follows
f _{ij}≦τ−(l _{ij} +
assuming that reasonable assumption that replacement of slack buffers on either side of the cell i would only increase the upper bound. Note to improve conciseness, we define τ_{ij}=l_{ij}+
Third, we can bound the freeslack f_{ij}′ associated with s_{ij }buffers as
f _{ij} ′≦s _{ij}(τ−(l _{ss} +
if the added slack buffers are actually full buffers. This is a practical assumption because slack cells can often be made as compact full buffers with very low cycle times (e.g., 6). If, however, they are made from halfbuffers, then modifications to reflect the potentially lower slack should be applied. The only requirement is that the freeslack is a linear function of sit.
This linear function can be obtained through algorithmic analysis or simulation of actual pipeline buffer cells. One tricky aspect of this analysis is that the freeslack of halfbuffer slack cells actually depends on the characteristics of the neighboring nonslack buffers and thus either a worstcase analysis must be used or the equations need to be modified to include characteristics of the neighboring nonslack buffers. The worstcase analysis must underestimate the slack of buffers and likely could be designed to have a significant impact only when s_{ij }is small. That is, the relative amount of under estimation would be smaller as s_{ij }grows. Note to improve conciseness, we define τ_{s}=l_{ss}+
Fourth, we can remove the need of the utility terms e_{ij }by rewriting the constraint for g_{ij}(0) as follows:
M g _{ij}(0)≧s _{ij}
where M is a large constant chosen such that the constraint M g_{ij}(0)≧s_{ij }guarantees g_{ij}(0) is 1 if any slack is used between leaf cell instances i and j.
Fifth, the halfbuffer slack constraint can be further simplified by using the more conservative constraint
f _{ij} +f _{jk}≦τ−[max(l _{ij} +l _{jk} +
removing the need for the Boolean variables g_{ij}(0). This approximation is often reasonable because the latencies of the pipeline buffers are usually smaller than the logic and thus the impact is to underestimate the available freeslack when pipeline buffers are used. This underestimation can be relatively small when s_{ij }is large because it only impacts the estimate of the freeslack caused by the first and last pipeline buffer of s_{ij}.
The resulting MILP is:
Minimize sum c(s_{ij}) s_{ij }subject to
Arrival time constraints: for all channel c between leaf cell instances i and j:
a _{i} =a _{j} −m τ+f _{ij} +l _{ij} +f _{ij} ′+l _{s } s _{ij},
Free slack constraints: for all channels c between leaf cell instance i and j
f _{ij}≦τ−τ_{ij}
f _{ij} ′≦s _{ij}(τ−τ_{s})
Halfbuffer slack constraints: for all pairs of channels between leaf cell instance i and j and j and k where leaf cell j is a halfbuffer
f _{ij} +f _{jk}≦τ−[max(l _{ij} +l _{jk} +
Time variable bounds, Boolean, and Integral constraints:
The optimization result is nonoptimal, but with some care the approximation can be conservative in that any result obtained will meet the desired cycle time. Let these modified mixedbuffer constraints be referred to in matrix form as A_{m}X_{m}=b_{m}.
Many asynchronous templates also have selfloop delays. These arise from cycles of behavior of a stage that does not involve the evaluation of neighboring stages but still may involve some neighboring completion sensing logic. In this case, the introduction of neighboring slack buffers can reduce these local cycle times.
Rather than complicate our MILP model with additional variables that express these selfloop delays, in particular implementation, these selfloop delays are preanalyzed and any selfloop delay that violates a target cycle time is further analyzed to determine how the selfloop delay can be reduced. If the introduction of neighboring slack cells will reduce the selfloop delay to meet the delay target, then extra constraints indicating which slack buffers are required should be added to the model. For example, if for a path of cells i, j, k, the selfloop delay of cell j violates the target cycle time, but adding at least one slack buffer between i and j or between j and k solves the problem, then a constraint s_{ik}+s_{kj}≧1 should be added to the system. If slack buffers are required on both input and output of cell for j's self loop delay to meet the target cycle time along this path, then we would add the two constraints s_{ij}≧1 and s_{jk}≧1 to the system. Lastly, if the self loop delay exceeds the target cycle time even if there are faster slack cells around it, then the target cycle time cannot be ever met and this should be reported to the user. In this final case, either this cell must be redesigned or the user must relax the target cycle time.
Our proposed mixed integer linear programs can be solved using the simplex algorithm applied to the relaxed LP problem if all vertices of the feasible solution space are guaranteed to be integral. It is wellknown that this happens if and only if the constraint matrix is totally unimodular and the constant matrix is integral. This section proves that with a few modifications our parameterized constraint matrix A_{p }and A_{m }meet this property and thus identifies precisely when our MILP framework can be solved using the simplex algorithm.
A square matrix is unimodular if its determinant is +1 or −1. A_{p }is totally unimodular if and only if every square submatrix has determinant 0, 1, or −1. An obvious necessary condition for this to be true is that A must consist of only 0, 1, and −1's. Sufficient conditions for total unimodularity are:
(1) all its entries are either 0, −1 or +1;
(2) any column has at most two nonzero entries; and
(3) the column with two nonzero entries have entries with opposite sign.
Equivalently, (2) and (3) can be phrased in terms of rows.
To see how this prevents the use of linear programming, consider the homogeneous unbalanced forkjoin pipeline example with additional slack limited to the output of stage 5. Assume the additional pipeline buffers have a cycle time of 7 giving a freeslack of 3 and expand all equality constraints to pairs of inequalities. The MILP becomes:
where s_{5}≧0, f_{5}≧0, and a_{i}≧0 for i=0 . . . 5, and the integral constraint s_{5}ε
The MILP solution yields the solution x_{p}=[8 0 2 4 6 0 2 1] giving an objective function value of 1 whereas the LP relaxation may yield the solution x_{p}=[8 0 2 4 6 0 3 ⅔] giving an objective function value of ⅔. In this example rounding of the LP relaxed solution leads to the MILP solution, but we do not believe this is true in general.
We now describe an approach to make A_{p }totally unimodular. The first concern is the latency of the pipeline buffer (l_{s}) cells may not be 1. In fact, in our examples they are assumed to be 2 (which accounts for the two 2's in the matrix above). If the pipeline buffer latency is approximately the same as the leaf cell latency, all leaf cells and pipeline buffers latencies can be normalized to 1. This means that the b_{p }vector would be normalized by divided it by 2, but if the leafcell latencies are all equal and the cycle times are all a multiple of the leafcell latencies (as is in our examples), the b_{p }vector will remain integral. The second concern is that the normalized freeslack coefficient for added pipeline buffers may also not be a 0, 1, or −1. In our case, the normalized freeslack coefficient is −3 divided by 2 or − 3/2. To address this we can approximate the normalized freeslack coefficient in the matrix to be −1. Alternatively, it is possible to omit this term in the free slack constraints and instead take into consideration the additional freeslack of pipeline buffers when instantiating the buffers into the design. For example, if the solver indicates 5 pipeline buffers are needed in some channel, because of the freeslack of buffers it may be possible to use 3 pipeline buffers instead (depending on the relative local cycle times of pipeline buffers and leafcells). The slack matching result obtained with this approach is not optimal, however, because the cost function used during minimization does not accurately reflect the cost of the used additional pipeline buffers. We believe, however, that this yields a reasonable approximation.
Assume we take this second approach in which we omit the freeslack coefficient for added pipeline buffers and for convenience assume the first T columns of A_{p }correspond to arrival times, the next P columns refer to free slack, and the last P columns refer to slack variables. In addition, assume the last P rows are used to upper bound the free slack variables. Property (1) is met by A_{p}. Property (2) is not met, however, because a row may have four nonzero entries. When it has four nonzero entries, three will be +1 (the entry for the source arrival time variable, the entry for the free slack variable, and the entry for the slack variable) and one will be −1 (the entry for the destination arrival time variable). We then have:
Theorem 5: The normalized (0, 1, −1) A_{p }matrix is totally unimodular.
Proof: Proof is by induction on the number of columns coming from columns T+1 to T+2P in the submatrix. If a square submatrix of A_{p }is taken from the first T columns, then all three properties are satisfied, and it is totally unimodular. If a square submatrix of A_{p }consists of k columns that originally came from columns T+1 to T+2P, then compute the determinant by expanding by minors along a column using Laplace's formula in the range of T+1 to T+2P. Recall this formula states that the determinant is the sum of column entries (having row i and column j) multiplied by the matrix cofactors, where the matrix cofactor is (−1)^{i+j }times the associated matrix minor, i.e., the determinant of the matrix obtained by removing the i^{th }row and j^{th }column. If all entries of the column are 0, the determinant is thus 0. However, in the column there also may be a pair +1, −1 in the column associated with an equality constraint converted to a pair of inequalities. Assume for simplicity that the matrix is organized such that the +1 and −1 elements are in neighboring rows (as in the above example). Both minors may be 0 in which case the overall determinant is 0. Otherwise, the minors must be opposite in sign because the associated matrices only differ by one row that is multiplied by −1. In this case, the two matrix cofactors are equal and the contribution to the overall determinant is again 0. Lastly, there may be a separate +1 in the column that is associated with a freeslack constraint. The contribution to the determinant due to this entry will be the determinant of the matrix with that row and column deleted (possibly inverted in sign depending on the location of the +1). That matrix is also a square submatrix of A_{p }but it has only k−1 columns that originally came from columns T+1 to T+2P, so by the induction hypothesis, it must have determinant +1, 0, or −1. QED.
Consequently, if we assume the latency of all leaf cells and pipeline buffers are equal and normalize them to 1 and also round the vector b to be integral, the integer linear program can be solved with linear programming techniques which can be very fast (or at least have worstcase polynomial time).
Similar approximations can be used to make the mixedbuffer constraint matrix A_{m }totally unimodular. The one additional concern that modifications of A_{m }must account for is the halfbuffer constraints on the sum of freeslacks. This additional constraint implies that columns from T+1 to T+2P may have two +1 elements associated with slack variables which invalidates the proof approach for Theorem 5 which relied on only one such +1 element. One approach to resolve this issue is to presatisfy these halfbuffer constraints by strengthening the constraints on the individual freeslack variables and thus removing the halfbuffer constraints from the system. This overly restricts the freeslack in the system bus is conservative.
An alternative but perhaps practical approach to the proposed approximations in both the A_{p }and A_{m }systems, is to simply relax the integral restriction on the s_{ij }variables, use an efficient LP solver, round the slack results to the nearest integral number of buffers, and, if necessary, further tune the buffer latencies via transistor sizing or by constraining the physical design placement and/or routing. Finally it is also possible to use standard MILP solutions at the cost of complexity, because, in general, algorithms to solve MILPs have exponential worstcase complexity.
The abovedescribed techniques assume that all leafcells are unconditional in nature and consume all input tokens and generated output tokens every cycle. In general, however, leaf cells can conditionally consume and generate data dependent upon internal state and/or the value read upon one or more channels. For these systems, the above approach is an approximation and may add more pipeline buffers than necessary. Several extensions to the above approach that address this issue are discussed below.
One improvement of the above approach is to optimize the slack for different modes of operation in the sequence of their frequency of occurrence. Each mode of operation is associated with a subset of the channels that are active during the mode. The most frequent mode of operation can be slack matched first and the resulting slack on the active channels can be fixed for subsequent modes. Less frequent modes can be given a relaxed throughput target to optimize average throughput. The maximum throughput for the second and any subsequent mode may be limited, however, in order to achieve feasibility.
A second approach is to allow different channels can have different cycle times associated with the most constrained mode of operation in which they are active. This is also nonoptimum because the freeslack for less frequent cycles (i.e., modes) of operation is under estimated when it shares channels active in other cycles (i.e., modes) with more restrictive frequency targets.
A third approach is to create different time and slack variables a_{i,m }and f_{c,m }for each different operation mode m for all channels that are active in this mode. In this way each operation mode would have its own set of variables that must be solved that uses a modedependent frequency target τ_{m }instead of τ. The set of slack variables s_{c }however would not change because the set of constraints for each mode of operation must all be satisfied with the same amount of slack on each channel. This approach is closer to optimal that the first two approaches because the freeslack of each mode of operation is accurately modeled, but has the disadvantage that the complexity of the MILP formulation grows linearly with the number of modes considered. It is still not necessarily optimal, however, because it does not model transient performance bottlenecks associated with changing between modes.
While the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. To reiterate, at least some of the slack matching techniques described herein have been described with reference to a technique for transforming the output of a synchronous logic synthesis CAD tool to an asynchronous design. However, it should be again noted that the slack matching techniques of the present invention are more generally applicable and may be employed in the optimization of any of a wide variety of asynchronous slackelastic systems and latencyinsensitive designs. This includes many quasidelayinsensitive designs.
This invention has introduced a number of mathematical models of the circuit that capture its performance and its parameterized performance as a function of the slack added to the circuits. We represented models with half, full, and mixed buffers with a variety of degrees of complexity and detail. By removing the slack variables, each of the models reduces to a simpler model describing the timing properties of the unoptimized circuit, which can be used for performance analysis. Specifically, any of the formulations can be converted into an LP performance analysis problem by eliminating all s_{ij }variables from the constraints (i.e. fixing them to zero) and then minimizing the objective function τ. The minimized τ is the circuit's worstcase cycle metric.
In addition, although various advantages, aspects, and objects of the present invention have been discussed herein with reference to various embodiments, it will be understood that the scope of the invention should not be limited by reference to such advantages, aspects, and objects. Rather, the scope of the invention should be determined with reference to the appended claims.
Cited Patent  Filing date  Publication date  Applicant  Title 

US4680701  Apr 11, 1984  Jul 14, 1987  Texas Instruments Incorporated  Asynchronous high speed processor having high speed memories with domino circuits contained therein 
US4875224  May 18, 1988  Oct 17, 1989  British Aerospace Plc  Asynchronous communication systems 
US4912348  Dec 9, 1988  Mar 27, 1990  Idaho Research Foundation  Method for designing pass transistor asynchronous sequential circuits 
US5133069 *  Jan 13, 1989  Jul 21, 1992  Vlsi Technology, Inc.  Technique for placement of pipelining stages in multistage datapath elements with an automated circuit design system 
US5212782 *  Apr 1, 1991  May 18, 1993  Vlsi Technology, Inc.  Automated method of inserting pipeline stages in a data path element to achieve a specified operating frequency 
US5367638  Sep 25, 1992  Nov 22, 1994  U.S. Philips Corporation  Digital data processing circuit with control of data flow by control of the supply voltage 
US5434520  May 19, 1992  Jul 18, 1995  HewlettPackard Company  Clocking systems and methods for pipelined selftimed dynamic logic circuits 
US5440182  Oct 22, 1993  Aug 8, 1995  The Board Of Trustees Of The Leland Stanford Junior University  Dynamic logic interconnect speedup circuit 
US5479107  Apr 30, 1993  Dec 26, 1995  Siemens Aktiengesellschaft  Asynchronous logic circuit for 2phase operation 
US5572690  Jun 6, 1995  Nov 5, 1996  Sun Microsystems, Inc.  Cascaded multistage counterflow pipeline processor for carrying distinct data in two opposite directions 
US5666532  May 2, 1996  Sep 9, 1997  Novell, Inc.  Computer method and apparatus for asynchronous ordered operations 
US5732233  Jan 23, 1995  Mar 24, 1998  International Business Machines Corporation  High speed pipeline method and apparatus 
US5752070  Jul 8, 1994  May 12, 1998  California Institute Of Technology  Asynchronous processors 
US5802331  Aug 23, 1996  Sep 1, 1998  U.S. Philips Corporation  Data processing system comprising an asynchronously controlled pipeline 
US5883808 *  Jan 29, 1997  Mar 16, 1999  Nec Corporation  Logic circuit optimization apparatus and its method 
US5889919  Jun 4, 1997  Mar 30, 1999  Sony Electronics, Inc.  Copy protect recording and playback system that enables single authorized recording of protected broadcasts be made 
US5918042  Jan 10, 1997  Jun 29, 1999  Arm Limited  Dynamic logic pipeline control 
US5920899  Sep 2, 1997  Jul 6, 1999  Acorn Networks, Inc.  Asynchronous pipeline whose stages generate output request before latching data 
US5949259  Nov 19, 1997  Sep 7, 1999  Atmel Corporation  Zerodelay slewrate controlled output buffer 
US5973512  Dec 2, 1997  Oct 26, 1999  National Semiconductor Corporation  CMOS output buffer having load independent slewing 
US6038656  Sep 11, 1998  Mar 14, 2000  California Institute Of Technology  Pipelined completion for asynchronous communication 
US6152613  Nov 25, 1997  Nov 28, 2000  California Institute Of Technology  Circuit implementations for asynchronous processors 
US6301655  Sep 15, 1998  Oct 9, 2001  California Institute Of Technology  Exception processing in asynchronous processor 
US6381692  Jul 16, 1998  Apr 30, 2002  California Institute Of Technology  Pipelined asynchronous processing 
US6502180  Feb 1, 2000  Dec 31, 2002  California Institute Of Technology  Asynchronous circuits with pipelined completion process 
US6910196 *  May 8, 2003  Jun 21, 2005  Intel Corporation  Clocked and nonclocked repeater insertion in a circuit design 
US6950959  Aug 1, 2002  Sep 27, 2005  Fulcrum Microystems Inc.  Techniques for facilitating conversion between asynchronous and synchronous domains 
US7013438 *  Nov 1, 2001  Mar 14, 2006  Cadence Design Systems, Inc.  System chip synthesis 
US7050324  Jul 13, 2004  May 23, 2006  Fulcrum Microsystems, Inc.  Asynchronous static random access memory 
US20030146079  Feb 5, 2002  Aug 7, 2003  Goldsmith Charles L.  Proximity microelectromechanical system 
US20030177454 *  Feb 21, 2003  Sep 18, 2003  Fujitsu Limited  Method and program for designing semiconductor integrated circuits 
US20040044979 *  Aug 27, 2002  Mar 4, 2004  Aji Sandeep A.  Constraintbased global router for routing high performance designs 
US20040046590 *  Sep 21, 2001  Mar 11, 2004  Montek Singh  Asynchronous pipeline with latch controllers 
US20040068711 *  Oct 7, 2002  Apr 8, 2004  ShailAditya Gupta  Digital circuit synthesis including timing convergence and routability 
US20040117753 *  Sep 24, 2003  Jun 17, 2004  The Regents Of The University Of California  Floorplan evaluation, global routing, and buffer insertion for integrated circuits 
US20040153984 *  Feb 5, 2003  Aug 5, 2004  Nataraj Akkiraju  Flipflop insertion in a circuit design 
US20040158806 *  Sep 12, 2003  Aug 12, 2004  Scheffer Louis K.  Automatic insertion of clocked elements into an electronic design to improve system performance 
US20040225981 *  May 8, 2003  Nov 11, 2004  Pasquale Cocchini  Clocked and nonclocked repeater insertion in a circuit design 
US20060239392 *  Jun 21, 2006  Oct 26, 2006  Fulcrum Microsystems, Inc., A California Corporation  Asynchronous systemonachip interconnect 
US20070245273 *  Jun 11, 2007  Oct 18, 2007  Interuniversitair Microelektronica Centrum  Task concurrency management design method 
WO1992007361A1  Oct 10, 1991  Apr 30, 1992  Hal Computer Systems, Inc.  Zero overhead selftimed iterative logic 
Reference  

1  A. Dasdan. Experimental Analysis of the Fastest Optimum Cycle Ratio and Mean Algorithms. ACM Transactions on Design Automation of Electronic Systems, vol. 9, No. 4, Oct. 2004, pp. 385418.  
2  A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings and T. K. Lee. The Design of an Asynchronous MIPS R3000 Microprocessor. ARVLSI'97, 1997, pp. 118.  
3  A. J. Martin. Synthesis of Asynchronous VLSI Circuits. Formal Methods for VLSI Design, ed. J. Staunstrup, NorthHolland, 1990, pp. 15,236287.  
4  A. M. Lines. Pipelined Asynchronous Circuits, Masters Thesis, California Institute of Technology, Jun. 1998, pp. 137.  
5  A. Xie. Performance Analysis of Asynchronous Circuits and Systems, Ph.D. Thesis, University of Southern California, Aug. 1999, 207 pages.  
6  Alain J. Martin, "Asynchronous Datapaths and the Design of an Asynchronous Adder", Department of Computer Science California Institute of Technology, Pasadena, California, pp. 124, Oct. 1991.  
7  Alain J. Martin, "SelfTimed FIFO: An Exercise in Compiling Programs into VLSI Circuit", Computer Science Department California Institute of Technology, pp. 121, 1986.  
8  Alain J. Martin, Compiling Communicating Processes into DelayInsensitive VLSI Circuits, Dec. 31, 1985, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 116.  
9  Alain J. Martin, Erratum: Synthesis of Asynchronous VLSI Circuits, Mar. 22, 2000, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 1143.  
10  Alain J. Martin, et al. The Design of an Asynchronous MIPS R3000 Microprocessor, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 118.  
11  Andrew Matthew Lines, Pipelined Asynchronous Circuits, Jun. 1995, revised Jun. 1998, pp. 137.  
12  C G. Wong, A. J. Martin. Highlevel synthesis of asynchronous systems by datadriven decomposition. Design Automation Conference, Jun. 2003, 508513.  
13  C. E. Leiserson and J. B. Saxe. Optimizing synchronous systems. Journal of VLSI Computer System, 1:4167, 1983.  
14  C. G. Wong, A. J. Martin. Datadriven process decomposition for circuit synthesis. Int'l Conference on Electronics, Circuits and Systems, vol. 1, 2001, 539546.  
15  C. H. Papadimitriou and K. Steiglitz, Combinational Optimization: Algorithms and Complexity, Dover Publications Inc, 1998, 9 pages.  
16  Cortadella et al., A concurrent model for desynchronization. Proceedings of IWLS, 2003, 10 pages.  
17  Davare et al., The Best of Both Worlds: the efficient asynchronous implementation of synchronous specifications. Design Automation Conference, Jun. 2004, pp. 500513.  
18  Ferreti et al., Singletrack Asynchronous Pipeline Templates. Dissertation. University of Southern California, Aug. 2004, 171 pages.  
19  G. Strang, Linear Algebra and Its Applications, Academic Press, Inc. 1980, 5 pages.  
20  GLPK: GNU Linear Programming Kit package. http://www.gnu.org/software/glpk/glpk.html, 2003, updated Nov. 23, 2006, 2 pages.  
21  GNU Linear Programming Kit Reference Manual Version 4.4, Jan. 2004, 82 pages.  
22  *  Heo et al., "PowerOptimal Pipelining in Deep Submicron Technology", Proceedings of the 2004 International Symposium on Low Power Electronics and Design, Aug. 911, 2004, pp. 218223. 
23  J. L. Peterson. Petri Net Theory and the Modeling of Systems. Englewood Cliffs, N.J.: PrenticeHall, 1981, 3 pages.  
24  J. Magott. Performance Evaluation of Concurrent Systems using Petri Nets. Information Processing Letters 18, pp. 713, Jan. 1984.  
25  J. Sparsų and J. Staunstrup. Delayinsensitive multiring structures. Integration, the VLSI journal, 15(3):313340, Oct. 1993.  
26  Kondratyev, A., an Lwin, K. Design of asynchronous circuits using synchronous CAD tools., Jul.Aug. 2002, pp. 107117.  
27  M. Ferretti, R. O. Ozdag, P. A. Beerel. High Performance Asynchronous ASIC BackEnd Design Flow Using SingleTrack FullBuffer Standard Cells. In ASYNC'04, Apr. 2004.  
28  M. Greenstreet and K. Steiglitz, Bubbles Can Make SelfTimed Pipelines Fast, Journal of VLSI and Signal Processing, vol. 2, No. 3, pp. 139148, Nov. 1990.  
29  N. Shenoy. Retiming: Theory and practice. Integration, the VLSI journal, 22:121, 1997.  
30  R. M. Karp. A characterization of the minimum cycle mean in a diagraph. Discrete mathematics, 23:309311, 1978.  
31  R. Manohar and A. J. Martin. Slack Elasticity in Concurrent Computing. Proceedings of the Fourth International Conference on the Mathematics of Program Construction, Lecture Notes in Computer Science 1422, pp. 272285, SpringerVerlag 1998.  
32  R. O. Ozdag, P. A. Beerel. Highspeed QDI asynchronous pipelines. In ASYNC'02, Apr. 2002, 10 pages.  
33  Ramamoorthy, C. V. and G. S. Ho. Performance evaluation of asynchronous concurrent systems using Petri nets, IEEE Trans. on Software Engineering, vol. SE6, No. 5, pp. 440449, 1980.  
34  S. Kim, P. A. Beerel. Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm. Int'l Conference on ComputerAided Design, Nov. 2000, 296302.  
35  Stevens et al., An Asynchronous Instruction Length Decode, Journal of SolidState Circuit, vol. 362, Feb. 2001, 217228.  
36  T. E. Williams. SelfTimed Rings and their Application to Division. PhD thesis, Stanford University, May 1991, 157 pages.  
37  T. Murata. Petri nets: properties, analysis and application, Proc. of the IEEE, vol. 77, No. 4, pp. 541579, 1989.  
38  U. Cummings, A. Lines, and A. Martin. An asynchronous pipelined lattice structure filter. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 126133, Nov. 1994, 11 pages.  
39  U.V. Cummings, et al. An Asynchronous Pipelined Lattice Structure Filter, Department of Computer Science California Institute of Technology, Pasadena, California, pp. 18.  
40  Venkat et al., "Timing Verification of Dynamic Circuits", May 1, 1995, IEEE 1995 Custom Integrated Circuits Conference, pp. 271274.  
41  Wilson, "Fulcrum IC heats asynchronous design debate", Aug. 20, 2002, http://www.fulcrummicro.com/press/articleeeTimes082002.shtml, 3 pages. 
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US7739628 *  Feb 15, 2008  Jun 15, 2010  Achronix Semiconductor Corporation  Synchronous to asynchronous logic conversion 
US7769987 *  Jun 27, 2007  Aug 3, 2010  International Business Machines Corporation  Single hot forward interconnect scheme for delayed execution pipelines 
US7882461 *  May 28, 2008  Feb 1, 2011  Magma Design Automation, Inc.  Method for optimized automatic clock gating 
US7982502 *  Sep 15, 2009  Jul 19, 2011  Achronix Semiconductor Corporation  Asynchronous circuit representation of synchronous circuit with asynchronous inputs 
US7984272  Mar 21, 2008  Jul 19, 2011  International Business Machines Corporation  Design structure for single hot forward interconnect scheme for delayed execution pipelines 
US8074193 *  Mar 11, 2009  Dec 6, 2011  Institute of Computer Science (ICS) of the Foundation for Research & Technology HellasFoundation for Research and Technology Hellas (FORTH)  Apparatus and method for mixed singlerail and dualrail combinational logic with completion detection 
US8106683 *  Mar 9, 2011  Jan 31, 2012  Achronix Semiconductor Corporation  One phase logic 
US8209645 *  Sep 24, 2009  Jun 26, 2012  Semiconductor Energy Laboratory Co., Ltd.  System and method for converting a synchronous functional circuit to an asynchronous functional circuit 
US8234607 *  Sep 15, 2009  Jul 31, 2012  Achronix Semiconductor Corporation  Token enhanced asynchronous conversion of synchonous circuits 
US8239799 *  Jan 7, 2010  Aug 7, 2012  Freescale Semiconductor, Inc.  Placing filler cells in device design based on designation of sensitive feature in standard cell 
US8291358  Apr 27, 2010  Oct 16, 2012  Achronix Semiconductor Corporation  Synchronous to asynchronous logic conversion 
US8434047  Jan 25, 2011  Apr 30, 2013  Synopsys, Inc.  Multilevel clock gating circuitry transformation 
US8468476 *  Mar 21, 2011  Jun 18, 2013  Altera Corporation  Method and apparatus for designing a system on multiple field programmable gate array device types 
US8593176  Jan 13, 2012  Nov 26, 2013  Achronix Semiconductor Corporation  One phase logic 
US8739102  May 9, 2013  May 27, 2014  Altera Corporation  Method and apparatus for designing a system on multiple field programmable gate array device types 
US8793629  Jan 10, 2011  Jul 29, 2014  Altera Corporation  Method and apparatus for implementing carry chains on FPGA devices 
US9026967  Apr 4, 2014  May 5, 2015  Altera Corporation  Method and apparatus for designing a system on multiple field programmable gate array device types 
US20080301594 *  May 28, 2008  Dec 4, 2008  Magma Design Automation, Inc.  Method For Optimized Automatic Clock Gating 
US20090006819 *  Jun 27, 2007  Jan 1, 2009  David Arnold Luick  Single Hot Forward Interconnect Scheme for Delayed Execution Pipelines 
US20090006823 *  Mar 21, 2008  Jan 1, 2009  David Arnold Luick  Design structure for single hot forward interconnect scheme for delayed execution pipelines 
US20090210847 *  Feb 15, 2008  Aug 20, 2009  Rajit Manohar  Synchronous to asynchronous logic conversion 
US20100083207 *  Sep 24, 2009  Apr 1, 2010  Hidetomo Kobayashi  System for Designing Functional Circuit and Method for Designing Functional Circuit 
US20100205571 *  Apr 27, 2010  Aug 12, 2010  Achronix Semiconductor Corporation  Synchronous to asynchronous logic conversion 
US20100231261 *  Mar 11, 2009  Sep 16, 2010  Nanochronous Logic, Inc.  Apparatus and Method for Mixed SingleRail and DualRail Combinational Logic with Completion Detection 
US20110062991 *  Sep 15, 2009  Mar 17, 2011  Rajit Manohar  Asynchronous circuit representation of synchronous circuit with asynchronous inputs 
US20110066986 *  Sep 15, 2009  Mar 17, 2011  Virantha Ekanayake  Token enhanced asynchronous conversion of synchonous circuits 
US20110167396 *  Jan 7, 2010  Jul 7, 2011  Freescale Semiconductor, Inc.  Design placement method and device therefor 
WO2011153333A1 *  Jun 2, 2011  Dec 8, 2011  Achronix Semiconductor Corporation  One phase logic 
U.S. Classification  716/104 
International Classification  G06F17/50 
Cooperative Classification  G06F17/5059 
European Classification  G06F17/50D6 
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