|Publication number||US7586145 B2|
|Application number||US 11/191,437|
|Publication date||Sep 8, 2009|
|Filing date||Jul 27, 2005|
|Priority date||Jul 27, 2005|
|Also published as||CN1905196A, CN100454551C, US20070023816|
|Publication number||11191437, 191437, US 7586145 B2, US 7586145B2, US-B2-7586145, US7586145 B2, US7586145B2|
|Inventors||Yuan-Hung Liu, Shih-Chi Fu, Chi-Hsin Lo, Chia-Shiung Tsai|
|Original Assignee||Taiwan Semiconductor Manufacturing Co. Ltd|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (33), Classifications (25), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention generally relates to semiconductor device structures and methods for forming the same, and more particularly to a method for forming an EEPROM flash memory device having a floating gate electrode including a jagged edge with multiple charge transfer points achieving improved erase voltage performance.
In flash EEPROM (Electrically Erasable Programmable Read Only Memory) devices, the level of voltage required to transfer charge to or from a floating gate electrode through insulating layers to accomplish write and erase operation is critical to the successful operation of flash EEPROM devices. For example, reducing a required voltage necessary for erase operations would be advantageous in terms of power requirements and design constraints including critical dimensions of a flash EEPROM device.
It is known that the profile of gate structures can affect the hot electron injection processes or Fowler-Nordheim tunneling processes. An unacceptable gate profile may adversely affect the stability of a floating gate structure thereby adversely affecting the reliability of write and erase operations. For example, the electric field strength present at a polysilicon gate electrode/insulator interface determines the desired flow of current in response to applied voltages to accomplish write and erase operations.
In certain flash EEPROM structures, for example employing a floating gate and self-aligned control gate in a split gate FET configuration, a consistent and predictable profile of the gate structure is critical to proper electrical functioning of the device. As design rules have decreased to below about 0.25 micron technology, forming acceptable control and floating gate electrode profiles to accomplish write and erase operations has become increasingly difficult, with increasingly narrow process margins.
There is therefore a continuing need in the EEPROM device processing art to develop improved EEPROM devices and methods for forming the same to achieve improve device performance and reliability as well as improving process margins to enable scaled down memory cell size.
It is therefore an object of the invention to provide improved EEPROM devices and methods for forming the same to achieve improve device performance and reliability as well as improving process margins to enable scaled down memory cell size.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention as embodied and broadly described herein, the present invention provides an EEPROM flash memory device with a reduced erase voltage and method for forming the same.
In a first embodiment the EEPROM flash memory device includes a floating gate electrode including an outer edge portion comprising multiple charge transfer pointed tips.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
Although the method of the present invention is explained with reference to an exemplary embodiment including the formation of a split gate flash memory device, it will be appreciated that the method of the present invention may be advantageously used in the formation of any polysilicon gate electrode structure where the profile of the polysilicon gate electrode may be advantageously formed with a jagged edge portion including multiple tip to accomplish charge transfer to or from the gate structure.
For example, referring to
It will be appreciated that the semiconductor substrate may include, but is not limited to, silicon, silicon on insulator (SOI), stacked SOI (SSOI), stacked SiGe on insulator (S-SiGeOI), SiGeOI, and GeOI, and combinations thereof. It will also be appreciated that the gate dielectric 14A may include, but is not limited to, doped or undoped silicon dioxide (e.g. nitrogen doped SiO2) formed by conventional chemical, thermal, CVD, or plasma enhanced deposition methods.
For example, referring to
For example, referring to
In an exemplary dry etching process to form the jagged edged portions 22A and 22B, a polymer-rich forming dry etching chemistry is preferably used. For example, polymer forming residues are formed during (in-situ) the etching process to cause preferential etching on portions of the FLG edge portions 22A and 22B, thereby causing a jagged edge to form. In a preferable etching process, an etching chemistry including plasma source gases of HBr, O2, Cl2, and optionally, a carbon rich fluorocarbon e.g., C/F ratio greater than about 2.5) Preferably a conventional DPS (dual plasma source) plasma reactor is used to allow independent adjustable RF power sources and bias power sources. Exemplary plasma etching conditions include a nitrogen containing sources gas include an RF power of about 150-250 Watts, a bias power of about 30-50 Watts, Cl2 at about 150-250 sccm, HBr at about 100-200 sccm and O2 at about 2-5 sccm. It will be appreciated that careful control of the etching chemistry as well as the power and bias sources are required to form the jagged edges with the desired geometry. In addition, the etching process may be carried out at reduced temperatures e.g., about 30° C. or lower to enhance in-situ polymer passivation layer formation during the polysilicon etching process.
It will additionally be appreciated that additional optional steps may include first forming an organic (polymer) layer on the polysilicon 14B layer surface (e.g., in-situ plasma formation) prior to commencing dry etching. It will also be appreciated that a polysilicon isotropic wet etching process may be carried out following the dry etching process to further refine a jagged edge geometry including multiple tipped portions.
Advantageously, the floating gate (FLG) electrode with a multiply tipped jagged edge according to the present invention, allows a reduced voltage in erase operations. For example, referring to
Referring back to
The preferred embodiments, aspects, and features of the invention having been described, it will be apparent to those skilled in the second art that numerous variations, modifications, and substitutions may be made without departing from the spirit of the invention as disclosed and further claimed below.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4701776 *||Dec 1, 1986||Oct 20, 1987||Seeq Technology, Inc.||MOS floating gate memory cell and process for fabricating same|
|US4706102 *||Nov 7, 1985||Nov 10, 1987||Sprague Electric Company||Memory device with interconnected polysilicon layers and method for making|
|US4763299 *||Oct 15, 1985||Aug 9, 1988||Emanuel Hazani||E2 PROM cell and architecture|
|US4933904 *||Dec 14, 1987||Jun 12, 1990||General Electric Company||Dense EPROM having serially coupled floating gate transistors|
|US5087583 *||Jul 27, 1989||Feb 11, 1992||Emanuel Hazani||Process for EEPROM cell structure and architecture with shared programming and erase terminals|
|US5321284 *||Dec 18, 1989||Jun 14, 1994||Texas Instruments Incorporated||High frequency FET structure|
|US5544103 *||Jul 12, 1994||Aug 6, 1996||Xicor, Inc.||Compact page-erasable eeprom non-volatile memory|
|US5633184 *||Feb 9, 1995||May 27, 1997||Mitsubishi Denki Kabushiki Kaisha||Method of making semiconductor device with floating bate|
|US5677216 *||Jan 7, 1997||Oct 14, 1997||Vanguard International Semiconductor Corporation||Method of manufacturing a floating gate with high gate coupling ratio|
|US5879992 *||Jul 15, 1998||Mar 9, 1999||Taiwan Semiconductor Manufacturing Company, Ltd.||Method of fabricating step poly to improve program speed in split gate flash|
|US6034395 *||Jun 5, 1998||Mar 7, 2000||Advanced Micro Devices, Inc.||Semiconductor device having a reduced height floating gate|
|US6229176 *||Feb 25, 1999||May 8, 2001||Taiwan Semiconductor Manufacturing Company||Split gate flash with step poly to improve program speed|
|US6236082 *||Aug 13, 1998||May 22, 2001||National Semiconductor Corporation||Floating gate semiconductor device with reduced erase voltage|
|US6242308 *||Jul 16, 1999||Jun 5, 2001||Taiwan Semiconductor Manufacturing Company||Method of forming poly tip to improve erasing and programming speed split gate flash|
|US6596588 *||Oct 22, 2001||Jul 22, 2003||Amic Technology Corporation||Method of fabricating a flash memory cell|
|US6630381 *||Oct 24, 2000||Oct 7, 2003||Emanuel Hazani||Preventing dielectric thickening over a floating gate area of a transistor|
|US6649472 *||Aug 2, 2002||Nov 18, 2003||Taiwan Semiconductor Manufacturing Company||Method of manufacturing a flash memory cell with high programming efficiency by coupling from floating gate to sidewall|
|US6649967 *||Jun 5, 2001||Nov 18, 2003||Hyundai Electronics Industries Co., Ltd.||Non-volatile memory device with a floating gate having a tapered protrusion|
|US6656796 *||Jan 14, 2002||Dec 2, 2003||Taiwan Semiconductor Manufacturing Co., Ltd||Multiple etch method for fabricating split gate field effect transistor (FET) device|
|US6693010 *||Nov 19, 2002||Feb 17, 2004||National Semiconductor Corporation||Split gate memory cell with a floating gate in the corner of a trench|
|US6710396 *||Jan 24, 2003||Mar 23, 2004||Silicon-Based Technology Corp.||Self-aligned split-gate flash cell structure and its contactless flash memory arrays|
|US6746920 *||Jan 7, 2003||Jun 8, 2004||Megawin Technology Co., Ltd.||Fabrication method of flash memory device with L-shaped floating gate|
|US6747310 *||Oct 7, 2002||Jun 8, 2004||Actrans System Inc.||Flash memory cells with separated self-aligned select and erase gates, and process of fabrication|
|US6767792 *||Mar 18, 2003||Jul 27, 2004||Megawin Technology Co., Ltd.||Fabrication method for forming flash memory device provided with adjustable sharp end structure of the L-shaped floating gate|
|US6847068 *||May 19, 2003||Jan 25, 2005||Nanya Technology Corporation||Floating gate and fabrication method therefor|
|US6849506 *||Sep 11, 2003||Feb 1, 2005||Hyundai Electronics Industries Co., Ltd.||Non-volatile memory device and fabrication method|
|US6861306 *||Nov 13, 2002||Mar 1, 2005||National Semiconductor Corporation||Method of forming a split-gate memory cell with a tip in the middle of the floating gate|
|US6865099 *||Aug 1, 2002||Mar 8, 2005||Silicon Storage Technology, Inc.||Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory|
|US6908814 *||Dec 3, 2003||Jun 21, 2005||Macronix International Co., Ltd.||Process for a flash memory with high breakdown resistance between gate and contact|
|US7118969 *||Feb 27, 2004||Oct 10, 2006||Samsung Electronics Co., Ltd.||Method of manufacturing a floating gate and method of manufacturing a non-volatile semiconductor memory device comprising the same|
|US7180127 *||Jun 17, 2004||Feb 20, 2007||Silicon Storage Technology, Inc.||Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region|
|US7190018 *||Apr 7, 2003||Mar 13, 2007||Silicon Storage Technology, Inc.||Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation|
|US20050287740 *||Jun 24, 2004||Dec 29, 2005||Taiwan Semiconductor Manufacturing Company, Ltd.||System and method of forming a split-gate flash memory cell|
|U.S. Classification||257/317, 257/314, 257/318, 257/322, 257/325, 257/315, 257/323, 257/319, 257/316, 257/320, 257/324, 257/321, 257/E29.3, 257/326|
|International Classification||H01L29/792, H01L29/76, H01L29/788|
|Cooperative Classification||H01L27/115, H01L29/7881, H01L27/11521, H01L29/42324|
|European Classification||H01L29/423D2B2, H01L29/788B, H01L27/115, H01L27/115F4|
|Jan 7, 2006||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., TAIWA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIU, YUAN-HUNG;FU, SHIH-CHI;LO, CHI-HSIN;AND OTHERS;REEL/FRAME:017170/0134
Effective date: 20050623
|Feb 6, 2013||FPAY||Fee payment|
Year of fee payment: 4