|Publication number||US7586349 B2|
|Application number||US 11/424,980|
|Publication date||Sep 8, 2009|
|Filing date||Jun 19, 2006|
|Priority date||Jun 17, 2005|
|Also published as||DE102005028173A1, DE102005028173B4, US20060284659, WO2006134175A2, WO2006134175A3|
|Publication number||11424980, 424980, US 7586349 B2, US 7586349B2, US-B2-7586349, US7586349 B2, US7586349B2|
|Original Assignee||Texas Instruments Deutschland Gmbh|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (4), Classifications (5), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to a CMOS integrated circuit for correction of the duty cycle of a clock signal.
Many integrated circuit applications need a full swing clock signal with a high precision clock duty cycle. The clock duty cycle is defined as the ratio of the output time during which the clock pulse is at a high level to the total clock cycle time period.
Duty Cycle=T high / T period
In double data rate applications (DDR), for example, both the rising and falling edges of a clock signal are used to write data into a flip-flop. Therefore, DDR systems demand a high precision duty cycle with a maximum deviation of +/−0.5%. This high precision must be guaranteed over a large frequency range and over variations which can be due to the process, to voltage fluctuations or to temperature. Even clock signals which are generated using a phase locked loop do not provide the necessary performance.
Current duty cycle correction circuits include operational amplifiers which use current mirrors for generating a correction voltage. But any mismatch of the transistors in the current mirror will result in a correction voltage offset. This offset directly influences the duty cycle of the output.
Furthermore, a differential amplifier generates the correction voltage by comparing the actual signal DC voltage to a reference voltage. This approach requires a zero offset of the reference voltage in combination with the differential amplifier, which is very difficult over process, voltage and temperature variations.
Therefore, there is a need for a duty cycle correction circuit wherein any transistor mismatch is cancelled out and no operational amplifiers are needed. This will lead to an easy implementation.
Furthermore, there is a need for a duty cycle correction circuit that allows a wide frequency range, uses a small chip area and has a low current consumption.
The invention provides a clock signal duty cycle correction circuit for a CMOS integrate circuit. The circuit comprises a correction amplifier with an input to which an input clock signal is applied and an output to which a capacitor is connected. The inventive circuit further comprises a voltage controlled resistor arrangement which is connected in the current path of the correction amplifier and which has a resistance control input, and a duty cycle detector with an input to which the output of the correction amplifier is applied and which has a detection output that supplies the correction voltage representative of a detected duty cycle. The output of the duty cycle detector is applied to the resistance control input of the voltage controlled resistor arrangement. The inventive CMOS duty cycle correction circuit forms a control loop with the duty cycle detector in the feedback path.
In a preferred embodiment, the duty cycle detector comprises a buffer amplifier and an RC low pass circuit connected to the output of the buffer amplifier. Preferably, the time constant t of the low pass circuit which is the product of the resistance R and the capacitance C is much greater than a period of the clock signal. The voltage output of the RC low pass circuit is indicative of the actual duty cycle. If a clock signal with a low level of 0 V and a high level of VDD is supplied to the RC low pass circuit, the RC low pass circuit delivers a DC voltage of VDD/2 for a duty cycle of 50%, a DC voltage between VDD and VDD/2 for a duty cycle of greater than 50% and a DC voltage between 0 V and VDD/2 for a duty cycle of less than 50%.
In a further embodiment, the correction amplifier comprises a complementary MOS transistor pair with interconnected gates to which the input clock signal is applied, and the voltage controlled resistor arrangement comprises a series connected complementary MOS transistor pair with interconnected gates to which the output of the duty cycle detector is applied. Thus, the output of the duty cycle detector which indicates the actual duty cycle controls the resistors of the voltage controlled resistor arrangement. The resistors are formed by appropriately sized MOS transistors. The voltage controlled resistor arrangement is connected in the current path of the correction amplifier and forms a low pass together with the capacitor which is connected to the output of the correction amplifier. The capacitor may be one inherent to the integrated circuit. Changing the resistor values influences the rising or falling times of the data signal edges.
The signal output of the duty cycle corrector is fed into an output buffer, which is formed by a series connected complementary MOS transistor pair.
Example embodiments are described below, with reference to accompanying drawings, wherein:
The detection of the actual duty cycle of the clock signal is effectuated by the RC low pass circuit whose function is explained with reference to
The output voltage VRC of the RC low pass circuit needs to be amplified in order to achieve a certain loop gain. This amplification is effectuated by the second inverter 24, which is a CMOS inverter cell operating in an analog mode.
The control voltage VC is applied to the gates of the transistors MP3 and MN3 of the second complementary MOS transistor pair. Transistors MP3 and MN3 are interconnected by their drains forming an output 32 of the correction amplifier 16. A charge capacitor 34 is connected to output 32. This charge capacitor 34 may be formed by an inherent capacitance due to transmission lines or by a parasitic transistor capacitance. The source of PMOS transistor MP3 is connected to the drain of PMOS transistor MP2, and the source of NMOS transistor MN3 is connected to the drain of NMOS transistor MN2. Transistors MP3 and MN3 form a voltage controlled resistor arrangement which connects the MOS transistors MP2, MN2 in series with each other. The drain source resistance of each of transistors MP2, MN2 is controlled by the applied gate voltage which is the control voltage VC output from duty cycle detector 20. Together with the capacitor 34, these voltage controlled resistors form a low pass filter. If control voltage VC is greater than VDD/2, transistor MN2 is more conducting than transistor MP3. This results in a faster falling edge at the output 32. If control voltage VC is smaller than VDD/2, the resistance of MP3 is lowered so that the rising edge of the clock signal at the output 32 gets faster. By so controlling the rise and fall times of the output signal, the duty cycle of the clock signal is adjusted.
Using the inventive duty cycle corrector, there are no offset problems. The output duty cycle of the clock signal is correctly adjusted, independently of whether the control voltage VC rises or decreases, as shown by the graphs in
The inventive CMOS duty cycle correction integrated circuit needs very few components and is easy to implement. Using an RC low pass circuit for duty cycle detection and a simple inverter cell as feedback amplifier results in a very stable circuit.
Those skilled in the art to which the invention relates will appreciate that various additions, deletions, substitutions and other modifications may be made to the described embodiments, without departing from the scope of the claimed invention.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8149037 *||Jul 21, 2010||Apr 3, 2012||Hynix Semiconductor Inc.||Clock duty correction circuit|
|US8471616 *||Jun 26, 2012||Jun 25, 2013||Samsung Electronics Co., Ltd.||Duty ratio correction circuit|
|US20100188126 *||Jan 26, 2009||Jul 29, 2010||International Business Machines Corporation||Voltage Controlled Duty Cycle and Non-Overlapping Clock Generation Implementation|
|US20130015897 *||Jan 17, 2013||Samsung Electronics Co., Ltd.||Duty ratio correction circuit|
|U.S. Classification||327/175, 327/172|
|Jul 28, 2006||AS||Assignment|
Owner name: TEXAS INSTRUMENTS DEUTSCHLAND GMBH, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAMBOURIS, SOTIRIOS;REEL/FRAME:018017/0368
Effective date: 20060619
|Feb 25, 2013||FPAY||Fee payment|
Year of fee payment: 4