|Publication number||US7605460 B1|
|Application number||US 12/028,434|
|Publication date||Oct 20, 2009|
|Filing date||Feb 8, 2008|
|Priority date||Feb 8, 2008|
|Publication number||028434, 12028434, US 7605460 B1, US 7605460B1, US-B1-7605460, US7605460 B1, US7605460B1|
|Inventors||Paul Ying-Fung Wu, Soon-Shin Chee|
|Original Assignee||Xilinx, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Non-Patent Citations (2), Referenced by (8), Classifications (23), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention generally relates to power distribution systems, and more particularly to power distribution systems implemented within a package substrate.
System-in-package (SIP) is an integration approach that is often utilized to achieve intelligent partitioning of the key components of an electronics system to achieve increased functionality using smaller form factors. One implementation of SIP technology applies three-dimensional integration, whereby one or more semiconductor die are stacked on top of a package substrate so as to increase the amount of circuitry that may exist per unit area.
Die stacking involves a process whereby a base die, such as a field programmable gate array (FPGA) for example, is attached to a package substrate to form a device package. The base die may also provide a platform for one or more stacked die, such as random access memory (RAM) or a microprocessor. Interconnections between the base die, the package substrate, and the one or more stacked die may be implemented using a plurality of implementations, such as using micro-bumps, solder bumps, solder balls, wire bonds, build-up vias, plated-through holes (PTHs), and associated through die vias (TDVs).
The inter-die signal path connections may be facilitated through the use of programmable heterogeneous integration (PHI) tiles. In general, a PHI tile consists of programmable multiplexers, TDVs, level translation circuits, test circuits, and dedicated power supply ports. A PHI tile is used to interconnect a base die having specific patterns of TDVs and associated input/output (I/O) pads with one or more stacked die having I/O pads that match the I/O pad placements of the base die. Logic signals existing within the stacked die may then be propagated to the base die using the associated TDVs, I/O pads, and level translation circuitry as may be required in a particular application.
Inter-die signal path connections may also be formed between the base die, the stacked die, and the package substrate to supply the one or more die with operational power. In particular, the package substrate may act as a power distribution system that may be comprised of multiple conductive layers, whereby pairs of conductive layers are arranged as power/ground plane pairs. Each power/ground plane pair of the package substrate is separated by a dielectric material, which acts as an insulative layer between the power/ground plane pair.
Power planes 120,122 and 116,118 may exist within the core of package substrate 104, or conversely, may exist within the build-up layers of package substrate 104, as power plane pairs. In particular, power plane 122 may provide a reference potential, e.g., ground potential, and power plane 120 may provide an operational potential that is referenced to the potential of ground plane 122. Similarly, power plane 118 may provide a reference potential, e.g., ground potential, and power plane 116 may provide an operational potential that is referenced to the potential of ground plane 118. Each operational and reference potential is then provided to die 106, via circuit board 102, using a plurality of plated-through holes (PTHs) that are implemented within the core of package substrate 104, combined with build-up vias, or laser vias, that are implemented within the build-up layers of package substrate 104.
Power planes 116-122 may comprise an entire conductive layer within the core of package substrate 104, or conversely, may be implemented as isolated “islands” of conductivity. In either instance, a characteristic impedance, Z0, is associated with each power plane pair and associated interconnect that provides operational power to die 106 from circuit board 102. Assuming the power planes and interconnects are lossless, the characteristic impedance of the power distribution system may be defined as:
where L is the spreading inductance and C is the distributed capacitance of a particular power plane pair and associated interconnect. While the power distribution system is assumed to be lossless for purposes of analysis, typical power distribution systems often exhibit lossy characteristics, so as to dampen, or dissipate, resonance energy that may be created during high speed switching operations within die 106.
As can be verified from equation (1), minimization of the characteristic impedance of the power distribution system may be accomplished by: decreasing the spreading inductance L; increasing the distributed capacitance C; or a combination of both. The magnitude of spreading inductance exhibited by a power plane pair within a package substrate is directly proportional to the thickness of the dielectric layer that separates the operational power plane from the reference power plane. Thus, the spreading inductance increases as the thickness of the dielectric layer increases.
The distributed capacitance magnitude, on the other hand, is inversely proportional to the thickness of the dielectric layer that separates the operational power plane from the reference power plane. Thus, the distributed capacitance decreases as the thickness of the dielectric layer increases. It can be seen, therefore, that by decreasing the thickness of the dielectric layer, the spreading inductance may be decreased and the distributed capacitance may be increased, which decreases the overall impedance of the power distribution system in accordance with equation (1).
Conventional power distribution systems, however, utilize power plane pairs that are separated by dielectric layers having thicknesses between 35 μm and 100 μm. As such, the spreading inductance of the power plane pair is increased above a desirable limit and the distributed capacitance of the power plane pair is decreased below a desirable limit, which increases the overall impedance of the power distribution system beyond desirable limits.
Generally, power plane pairs 212,214 and 216,218 exist within core portion 228 to implement a power distribution system for die 206. In particular, package substrate 204 provides power plane pairs 212,214 and 216,218, which may be separated by a dielectric layer having thickness 220 and 222, respectively. The spreading inductance exhibited by power plane pairs 212,214 and 216,218 having a dielectric layer thickness of 35 μm, for example, is approximately equal to 45 pico henries per square. The distributed capacitance of such an arrangement is approximately equal to 112 pF/cm2. A 100 μm dielectric layer displaced between the power plane pairs, on the other hand, exhibits approximately 130 pico henries per square of spreading inductance and approximately 35 pF/cm2 of distributed capacitance.
Maximization of the distributed capacitance allows the power distribution system to maximize the ability to respond to dynamic current demands that are imposed by die 206. Similarly, minimization of the spreading inductance minimizes the reluctance of the power distribution system to retard changes in current flow. As discussed above, however, conventional power plane pairs exhibit relatively thicker dielectric layers, which increases the overall impedance of the power distribution system, thereby limiting the power distribution system's performance during dynamic current demands imposed by die 206. Given that additional die are stacked upon die 206 to form a stacked die package, the dynamic current demands that are imposed upon the power distribution system are even greater.
What is needed, therefore, is a power distribution system that both maximizes the distributed capacitances and minimizes the spreading inductance so as to optimize current flow for enhanced noise performance of a package substrate within, for example, a SIP based integration.
To overcome limitations in the prior art, and to overcome other limitations that will become apparent upon reading and understanding the present specification, various embodiments of the present invention disclose a method and apparatus to reduce the spreading inductance and increase the distributed capacitance of power plane pairs so as to optimize current flow for enhanced noise performance of a package substrate power distribution system.
In accordance with one embodiment of the invention, a power distribution system comprises a package substrate that includes a plurality of conductive layers that are separated by a plurality of insulating layers, where each of the plurality of insulating layers has a first thickness. The package substrate further includes a plurality of copper-clad laminate structures, where each copper-clad laminate structure includes conductive layers that are separated by an insulating layer having a second thickness. The power distribution system further comprises a die that is coupled to the package substrate and is adapted to conduct operational power from the plurality of copper-clad laminate structures. The second thickness is less than one half of the first thickness.
In accordance with another embodiment of the invention, a power distribution system comprises a package substrate that includes a plurality of conductive layers that are separated by a plurality of insulating layers, where each of the plurality of insulating layers has a first thickness. The package substrate further includes a plurality of copper-clad laminate structures, where each copper-clad laminate structure includes first and second conductive layers having first and second perforation patterns, where the first and second conductive layers are separated by an insulating layer having a second thickness. The power distribution system further comprises a die that is coupled to the package substrate and is adapted to conduct operational power from the plurality of copper-clad laminate structures. The second thickness is less than one quarter of the first thickness.
In accordance with another embodiment of the invention, a method of forming a power distribution system within a package substrate comprises developing a starting material to form power plane pairs within the package substrate. The starting material includes first and second conductive layers that are separated by a first insulating layer. The method further comprises laminating the power plane pairs together to form a core portion of the package substrate, laminating build-up layers to the core portion to form build-up portions of the package substrate. The build-up portions include a plurality of conductive layers separated by a plurality of second insulating layers. A thickness of the first insulating layer is less than half of a thickness of the plurality of second insulating layers.
Various aspects and advantages of the invention will become apparent upon review of the following detailed description and upon reference to the drawings in which:
Generally, various embodiments of the present invention are applied to the field of integrated circuits (ICs) of which programmable logic devices (PLDs) are a subset. In particular, a method and apparatus is provided to reduce the spreading inductance and increase the distributed capacitance of power planes within the power distribution system of a semiconductor package substrate. In one embodiment, a pre-fabricated, copper-clad laminate (CCL) structure is utilized as a starting material for the power plane pairs, which are then integrated into a package substrate using imaging, lamination, and drilling/plating processes.
The CCL implemented power plane pairs within the package substrate exhibit an insulating layer having thicknesses between, e.g., 1-15 micrometers (μm). Thus, the thickness of the dielectric layer of the CCL implemented power plane pairs are less than half of the insulating layer thicknesses of conventional power plane pairs, which range between 35-100 μm. As such, the spreading inductance and the distributed capacitance of the CCL implemented power plane pairs of the power distribution system combine to optimize current flow into the corresponding die of the semiconductor package, which subsequently reduces detrimental effects, such as ground bounce and power supply noise.
In an alternate embodiment, two metal planes and a dielectric layer may be used to form a starting material having a larger insulating layer thickness, e.g., 35 μm. The starting material may then be laminated together and then compressed using elevated pressure and increased heat to form a final CCL structure exhibiting an insulating layer thickness of, e.g., 5 μm. In particular, adjoining the two metal planes includes a lamination step, whereby a dielectric material is “sandwiched” between the two metal planes such that the original thickness of the dielectric material is compressed to a final thickness of, e.g., 5 μm. Such a reduced dielectric thickness is facilitated by the use of perforated mesh patterns formed in one, or both, of the two metal planes, whereby excess dielectric material is allowed to flow into the perforated mesh patterns of the first and/or second metal planes during the adjoining process. Non-conductive spacer posts inserted between the two metal planes prior to lamination define a minimum separation distance between the two metal planes after adjoinment. As such, an effective separation distance between the two metal planes is established that ultimately reduces the spreading inductance and increases the distributed capacitance of the final CCL structure.
Alternate embodiments employ plating or deposition processes to obtain a minimum separation distance between the two metallic planes of a power plane pair. For example, metallization of a non-conductive surface may be employed, whereby non-conductive elements, such as polymers, ceramics, and glass, may be sensitized and activated to accept conductive elements, such as nickel, aluminum, and copper, during a deposition process. Both surfaces of the non-conductive layer may then be plated through, e.g., a deposition process, to ultimately form the power plane pair, whereby the thickness of the non-conductive layer may be readily selected to, e.g., 1-15 μm.
The package substrate of semiconductor die package 300 is arranged in layers, where for example, conductive/insulative layers form build-up portion 312 at the top of the package substrate, conductive/insulative layers form core 310 within the middle of the package substrate, and conductive/insulative layers form build-up portion 314 at the bottom of the package substrate. In one embodiment, power plane pair 340,342 implements an operational power and ground plane pair within the core of the substrate package that is operating at a first relative voltage magnitude. Power plane pair 344,346 implements an additional operational power and ground plane pair within the core of the substrate package that is operating at a second relative voltage magnitude. It is noted, however, that more than two operational power and ground plane pairs may be implemented within core 310 depending upon the particular application. For example, a 3+6+3 configuration may be implemented, whereby 6 conductive layers within the core of the package substrate combine to form 3 power plane pairs. It is noted that still other configurations may be possible.
Each of the conductive/insulative layers of build-up portions 312 and 314 of the package substrate may be sequentially processed in a build-up processing sequence, whereby a sheet of conductive material, such as copper or aluminum, may be laminated onto both surfaces of an insulative layer, such as may be implemented using a prepreg material, to form a first “sandwich”. Geometric patterns may then be defined by a microlithographic exposure process, whereby photoresist deposited on the conductive layers of the sandwich are exposed to geometric patterns of radiation, such as ultraviolet (UV) light, whereby the exposed areas are defined by an exposure tool, photomask, and/or computer data.
After exposure, the photoresist is subjected to a development process that converts the latent image in the photoresist into the final image, which ultimately serves as the mask in the subsequent etching process to selectively remove a portion of each conductive layer to produce the required geometric patterns in both conductive layers of the sandwich. Build-up vias 316 may then be formed within the sandwich and plated with a conductive material. Build-up vias 316 may additionally be coupled to one of the conductive layers of the sandwich, or conversely, may be electrically isolated from both conductive layers of the sandwich as required by the application. Additional sandwiches may be similarly processed and laminated together to produce build-up portions 312 and 314 of the package substrate, whereby the various geometric patterns of build-up portions 312 and 314 may be utilized to provide signal traces, build-up via isolation islands, build-up via coupling patterns, and any other geometric pattern that may be required for power and signal routing within the package substrate.
In step 454, geometric patterns 408 may be etched into conductive layers 402 and 404, as illustrated in
In step 456, power plane pairs are laminated to a dielectric, or insulating, layer 410 to form core portion 310 of the package substrate of
Plated-through hole 416, for example, provides connectivity to the bottom conductive layer of power plane pair 412 while being electrically isolated from the other conductive layers of power plane pairs 412 and 414. Plated-through hole 418, on the other hand, provides connectivity to the bottom conductive layer of power plane pair 414 while being electrically isolated from the other conductive layers of power plane pairs 412 and 414. Similarly, plated-through hole 420 provides connectivity to the top conductive layer of power plane pair 414 while being electrically isolated from the other conductive layers of power plane pairs 412 and 414. In addition, plated-through hole 422 provides connectivity to the top conductive layer of power plane pair 412 while being electrically isolated from the other conductive layers of power plane pairs 412 and 414.
Previously developed conductive and insulative layers of build-up portions 312 and 314 may then be laminated to core 310, as in step 460, to form the package substrate having build-up layers 424 and 426 and associated interconnections. As illustrated in
The resulting CCL implemented power plane pairs 412 and 414 within the package substrate of
In a first embodiment, as illustrated in
A second power supply may be similarly connected to solder balls 336 and 338 and associated interconnects 356 and 358, respectively, so as to provide the operational power at a second voltage magnitude and a second voltage reference magnitude to power plane pair 344 and 346, respectively, that may be required by die 302 during operation. In such an instance, power plane pairs 340,342 and 344,346 are electrically isolated from one another by associated interconnects 352-358.
In order to further increase the capacitance of the power distribution system of
In an alternate embodiment, as illustrated in
As such, a low-impedance loop is generated within the package substrate that extends from capacitor 506 to power plane pair 544,546 through associated build-up vias 514 and interconnects 508 and 510. The low-impedance loop then continues along power plane pair 544,546 through interconnect 512 to power plane pair 540,542 and to capacitor 504 through the build-up vias 516.
Interconnection of the two power planes as illustrated in
A plurality of perforations may be formed within metallic plane 602 during step 652 of
While the shape of perforations 614 and 616 is illustrated as being circular, perforations 614 and 616 may instead exhibit a plurality of shapes, e.g., rectangular, square, elliptical, hexagonal, octagonal, etc. In addition, while the mesh patterns of
Adjoining metallic plane 602 with metallic plane 604 as illustrated in
It is noted, that perforations 614 and/or 616 of metallic planes 602 and/or 604, respectively, allow dielectric material 606 to flow into metallic planes 602 and/or 604 during compression step 656. In particular, dielectric material 608 flows into perforations 614 and dielectric material 610 may optionally flow into perforations 616 (if any) during compression step 656 to facilitate the compression of dielectric material 606 to a final thickness of, e.g., 5 μm. As such, the final thickness of dielectric material 606 is less than one quarter of the dielectric layer thicknesses of conventional power plane pairs, which range between 35-100 μm.
In comparison with
In alternate embodiments, the CCL structure of
Other aspects and embodiments of the present invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and illustrated embodiments be considered as examples only, with a true scope and spirit of the invention being indicated by the following claims.
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|U.S. Classification||257/691, 257/762, 257/700, 438/652|
|Cooperative Classification||H01L2224/16235, H01L2224/16225, H01L2924/19105, H01L2924/09701, H05K1/0265, H05K3/4602, H01L23/49822, H01L23/50, H01L2924/15311, H05K1/162, H01L2924/01078, H01L2924/3011, H05K2201/09309, H01L23/49827, H05K2201/10674|
|European Classification||H05K1/02C8B, H01L23/498D, H01L23/50|