|Publication number||US7605574 B2|
|Application number||US 11/785,227|
|Publication date||Oct 20, 2009|
|Filing date||Apr 16, 2007|
|Priority date||Apr 26, 2006|
|Also published as||CN101064472A, EP1850468A2, EP1850468A3, US20070252567|
|Publication number||11785227, 785227, US 7605574 B2, US 7605574B2, US-B2-7605574, US7605574 B2, US7605574B2|
|Inventors||David Dearn, Holger Haiplik|
|Original Assignee||Wolfson Microelectronics Plc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Non-Patent Citations (2), Referenced by (13), Classifications (6), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to switching regulator circuits and in particular to switching regulator circuits which use slope compensation techniques to stabilise the regulator.
2. Description of the Related Art
Switching regulators are very commonly used in DC-DC conversion as they offer higher efficiency than linear regulators. They typically consist, in their most basic form, of an inductor, a capacitor, a diode and a switch which switches the inductor alternately between charging and discharging states. These basic elements can be arranged to form a step-down (buck), step-up (boost) or inverting buck-boost regulator.
Control of the switch has been achieved previously by techniques such as “voltage mode control” and “current-mode control”. In the case of a basic constant frequency current-mode control buck converter the switch is connected to an input voltage and is closed at the beginning of a clock cycle. Closing the switch causes the current in an inductor connected between the switch and the output of the converter to rise. This current is monitored and compared against the output of an error amplifier. When the output voltage of the inductor current monitor exceeds the output voltage of the error amplifier the switch is turned off, and not turned on again until the beginning of the next clock cycle. In this way the output voltage is controlled to the required value.
It is a well known phenomenon in current-mode control regulators that when the duty cycle (switch ON time/clock period) of the converter exceeds 50%, subharmonic oscillation can occur. Subharmonic oscillation is an undesirable repeating pattern in inductor current that occurs every two or more periods. [See R. W. Erickson, D. Maksimović, Fundamentals of Power Electronics, 2nd Edition, Kluwer Academic Publishers, 2001, pp. 439-449.]
It is also well known that the problem of subharmonic oscillation can be addressed by using the technique known as “slope (or ramp) compensation”. This is typically done by adding a predetermined duty-cycle-independent synchronous sawtooth signal (variously termed an artificial ramp, a compensatory ramp or loosely but simply “additional slope”) to the measured inductor current up slope, or alternatively by subtracting a similar signal from the error amplifier output. To ensure stability for all duty cycles up to 100%, the slope of this ramp should be equivalent to at least half of the anticipated maximum inductor current down slope.
DC-DC converters usually have some means to limit the current in the inductor. There are many different ways to implement the current limit, but it is often convenient to use the signal of “inductor current plus additional slope” to give a current limit. Examples of this are common and one way of doing this is to simply limit (“clamp”) the voltage output of the error amplifier. In that case the error amplifier signal is not only used for control of the converter but also for current limiting. One drawback of this is that due to the “additional slope” the current limit has different values for different duty cycles when using a fixed voltage limit on the output of the error amplifier. This means that the true maximum current in the inductor falls proportionally with the duty cycle.
U.S. Pat. No. 6,611,131 discloses a technique to remove the effect of the “additional slope” for the current limit by increasing the current limit by the same amount as the slope on a cycle-by-cycle basis by means of an adjustable voltage clamp circuit controlled by the slope compensation circuit. This, however, has the same problem as having no slope compensation at all for the current limit comparison, in that subharmonic oscillation will occur in current limit.
It is therefore an object of the invention to provide a DC-DC regulator that alleviates these drawbacks in the prior art and addresses the problem of subharmonic oscillation while maintaining a substantially steady inductor current limit for most of its operation, independent of duty cycle.
In a first aspect of the invention there is provided a current-mode switching regulator comprising at least: an inductor; a main switch for controlling the current flow through the inductor; and a feedback control circuit for operating the main switch cyclically and to vary a duty cycle of the main switch so as to substantially maintain an output voltage of the regulator at a desired level, the feedback control circuit further including slope compensation circuitry for introducing an offset into a comparison between a signal representing the fed-back output error voltage and a signal representing the inductor current, wherein the regulator further comprises current limiting circuitry for controlling the main switch responsive to a current limit reference signal, the current limit circuitry comprising adjustment circuitry for adjusting the current limit reference signal in response to the duty cycle of more than one previous cycle so as to limit current in the inductor irrespective of the output voltage and to a value which, in the steady state, is substantially independent of the duty cycle.
Limiting the current in the inductor to a value substantially independent of the duty cycle should be understood to mean that the value to which the inductor current is limited is independent of duty cycle in the steady state, but is allowed to change in the event of a change in duty cycle, being restored to its former level over a number of cycles. By this technique, the inventors have found a way to provide a current-mode voltage regulator with slope compensation and with a steady-state inductor current limit independent of duty-cycle without subharmonic oscillations in current limit.
The current limit circuitry may control the main switch on the basis of a combination of the current limit reference signal and one of or a combination of the fed-back output error voltage signal, the inductor current signal and a slope compensation signal.
The adjustment circuitry may further comprise a low pass filter arranged to receive for each cycle a value representative of the duty cycle in that clock cycle and to combine the values for several clock cycles to generate the current limit reference. Preferably this low pass filter has a corner frequency less than the clock frequency of the regulator. In one embodiment the corner frequency of the low pass filter is an order of magnitude less than the clock frequency of the regulator.
The slope compensation circuitry may, in operation, generate a ramp signal of a predetermined amplitude during each clock cycle, and the adjustment circuitry may comprise a sample and hold circuit operable in each cycle to capture a value representative of a proportion of the ramp amplitude defined by the duty cycle in that clock cycle.
Alternatively, the adjustment circuitry may be arranged to generate a ramp signal replicating a ramp signal generated within the slope compensation circuitry, the replica ramp signal being used to generate for each clock cycle a value representative of a proportion of the ramp amplitude defined by the duty cycle in that clock cycle. In operation the generation of the replica ramp signal may be interrupted in phase with opening of the main switch so as to ramp only as far as the representative value and then to hold its value for use in generating the current limit reference signal. A sample and hold circuit may be connected to receive the replica ramp signal and to hold the representative value.
There may be further provided scaling circuitry to scale the signals in various parts of the circuit, for example to make full use of the available signal headroom. The scaling circuitry may be arranged to scale the intermediate signal, which may be of a different scale to the compensatory ramp signal, to maintain the same overall signal transfer functions as in the unscaled circuit. This scaling may include scaling or converting signals between current and voltage representations for scaling the signal corresponding to a proportion of the compensatory ramp signal.
The current limiting circuitry may further comprise a clamping circuit to act on the feedback control circuit, the clamping circuit being controlled by the current limit reference signal. The clamping circuit may comprise a comparator and a transistor, arranged such that the comparator compares the signal representing the fed-back error voltage to the current limit reference signal and, should the signal representing the fed-back output voltage exceed current limit reference signal, causes the signal representing the fed-back output voltage to be clamped, the transistor diverting excess current to ground.
Alternatively the regulator may be arranged such that the current limiting circuitry controls the main switch on the basis of a comparison of the current limit reference signal and a combination of the inductor current signal and the slope compensation signal. The current limiting circuitry may comprise a comparator for comparing the current limit reference signal and the signal representing the inductor current offset by the slope compensation circuitry, the main switch being reset should the signal representing the inductor current exceed the current limit reference signal regardless of the result of the comparison between the signal representing the fed-back error voltage and the signal representing the inductor current offset by the slope compensation circuitry. This may be done by providing an OR gate such that the main switch is reset should the signal representing the inductor current offset by the slope compensation circuitry exceed either the current limit reference signal or the signal representing the fed-back output voltage.
The regulator may comprise a rectifier. The rectifier may be a diode, or a second switch arranged to run synchronous with the main switch. The main and second switches may be arranged to be in antiphase with each other for most of the operating modes. In certain operating modes both switches can be open. The regulator may be arranged to function as a buck (step down), boost (step up) or inverting buck-boost regulator.
The regulator may comprise a current monitor for measuring the current in the inductor.
The feedback control circuit may comprise an error amplifier for producing the signal representing the fed-back error voltage from the regulator output by comparing the regulator output to a fixed reference.
The regulator may further provide circuitry to add the ramp signal to the measured inductor current up slope or alternatively, to subtract the ramp from the current limit reference signal.
In a further aspect of the invention there is provided a current-mode switching regulator comprising at least
In a yet further aspect of the invention there is provided a current-mode switching regulator comprising at least
In all the above the skilled person will appreciate that circuitry should be taken to include software or firmware implementation where possible.
Embodiments of the invention will now be described, by way of example only, by reference to the accompanying drawings, in which:
It should be noted that the measured inductor current may be represented as a voltage, related to the actual inductor current by a designed scaling factor or transresistance, in some embodiments including the one described here. Alternatively this signal may be a current, possibly scaled with respect to the actual current by a dimensionless scaling factor. Similarly other signals inside embodiments may be currents rather than voltages, with appropriate choice of other components, e.g. transconductance rather than voltage amplifiers, current comparators rather than voltage comparators, switched-current rather than switched-capacitor filters etc. It may be convenient in design to scale the signals in various parts of the circuit, for example to make full use of the available signal headroom, but the scaling will be preformed so that the overall operation will be equivalent.
The switch 100 is then closed at the beginning of the next clock cycle, and the inductor current begins to rise again.
For clarity, the error amplifier output VERR is shown constant over this timescale. In practice there will be some modulation of this level due to voltage ripple and load variation causing modulation of VOUT, but this modulation may be rendered small by decoupling and does not affect the basic operation of the circuit over timescales of a few cycles.
As explained previously, it is also well known that the problem of subharmonic oscillation can be addressed by using the technique known as “slope (or ramp) compensation”. This is typically done by adding a predetermined duty-cycle-independent synchronous sawtooth signal to the measured inductor current, or alternatively by subtracting a similar signal from the error amplifier output. To ensure stability for all duty cycles up to 100%, the slope ma of this ramp should be equivalent to at least half of the anticipated maximum magnitude of the inductor current down slope, −m2.
It is often convenient in a DC-DC converter to use the signal of “error amplifier output minus slope” or “inductor current plus slope” to give a current limit. There are a number of known ways of doing this, and a common way is to simply limit (or “clamp”) the voltage output of the error amplifier. In such a case this would mean that the error amplifier signal is not only used for control of the converter but also for current limiting. One drawback is that, as the clamping level is fixed, the effect of the “additional slope” results in the actual current limit of the regulator varying and being dependent on the duty cycle. For example, in
In this embodiment, VADJ is derived from a ramp signal which is a replica of the ramp signal produced by ramp generator 665 for at least part of each clock cycle. This ramp signal is produced by passing a constant current IINT from current source 672 through an integrator 680, possibly just a capacitor. Prior to being integrated, current IINT is passed through switch 675, which is in-phase with switch 600, so that this current is only transmitted when switch 600 is closed (that is the “on portion” of the clock cycle). The resultant intermediate signal thus ramps up, replicating the ramp signal produced by ramp generator 665 for the duration of the “on portion” of the clock cycle, and holding the achieved ramped value for the remainder of the clock cycle. This intermediate signal is then reset to zero at the end of each clock cycle. The intermediate signal is then passed through sample and hold circuit 682 and is then low pass filtered by filter 685, before being fed to the clamp 695.
The ramp generator 665 may generate its ramp using a current source charging a capacitor, the capacitor then being discharged at the end of each clock cycle. If so, the ramp signal at the output of the integrator 680 will be a replica of the output of ramp generator 665 if both signals are generated using the same value of current source current and capacitance. Alternatively, it may be convenient to scale the current of current source 672 and its load capacitance by the same factor, to obtain the same output ramp voltage. A further possibility is to scale the intermediate signal with respect to the compensatory ramp signal m, by scaling the current or capacitance separately, to compensate for other signal scaling introduced elsewhere in the regulator, e.g. to optimise signal swings.
An alternative would be to use the voltage from the output of ramp generator 665 (or a duplicated compensatory ramp current therefrom, if 665 is current-output), and to sample-and-hold this ramp at the end of the on portion of each clock cycle to provide a similar duty-cycle-dependent intermediate signal.
Various methods of clamping the output of an amplifier are well known. The clamp 695 may simply be a bipolar transistor with emitter connected to VERR, base connected to VCL and collector grounded, with VLIM suitably offset to compensate for the base-emitter voltage VBE of the transistor. Preferably and more accurately, the clamp 695 may comprise a transistor and a comparator. The comparator compares the output of the error amplifier to the current limit signal. Should the output of the error amplifier exceed the current limit signal, the comparator switches on the transistor which then diverts excess current from the output of the error amplifier 640 to ground, clamping the output of the error amplifier as a result.
The integration may be performed simply using a capacitor, with the resultant signal then filtered using a larger capacitor, for example by briefly connecting the first capacitor in parallel with the larger capacitor to share charge for a brief period each clock cycle. Alternatively, well-known op-amp-based integrator circuitry could be used.
The current source IINT and integrating capacitor within 680 could be designed to be the same as equivalent devices within ramp generator 665: for an integrated circuit implementation, as relative accuracy within semiconductor integrated circuits is excellent, there would be excellent matching between the compensation ramp voltage and the “duty cycle”-factored voltage VADJ.
The corner frequency of the low pass filter is chosen to be lower than the clock frequency of the converter. If the corner frequency is, for example, 10 times lower, then a change in the duty cycle of the converter of say 10% will only be fully seen on the output of the low pass filter after approximately 5 time constants of the filter (with a time constant being 10/(2×π×fCLK)≈1.6×TCLK in this example (where fCLK is the clock frequency and TCLK is the clock period)).
In this case the regulator is operating in current limit and the error amplifier output VERR is being held at the clamping limit by the clamp. When, for example, the load current demand decreases, the output voltage VOUT of this buck converter operating in current limit will rise, and as a consequence the up-slope (dependent on VIN−VOUT) will decrease and the down-slope of the inductor current (dependent on VOUT) will increase. As a result there is an increase in duty-cycle (shown after the first clock period) and, as a consequence, the resulting current limit initially falls due to the effect of the slope compensation. The clamping limit is then increased each cycle as the limit-adjustment signal settles to its new value, until the clamping limit reaches the new value appropriate for the duty cycle, giving the same maximum inductor current as before. Of course it is more likely that the change in current limit is more continuous, and is probably averaged over a number of cycles.
It should be understood that the above circuit operates only to adjust the clamping limit to compensate for the effect of the slope compensation on the current limit. Therefore this adjustment is relevant only when the circuit is operating at or near the current limit. When operating below this limit the error amplifier output level would be below the clamping limit and the regulator operates normally (although the clamping limit is always set, regardless of whether the circuit is operating at the current limit or not). This is illustrated in
In this example of operation, the load current demand increases, initially causing VOUT to drop. This causes the error amplifier output 950 (not clamped in this case) to increase as shown by the upward slope in this trace over the first three cycles, this causing an increase in duty cycle. The increased duty cycle causes the peak current in the inductor to increase and finally settle to a new value appropriate for the new load. As can be seen, the clamping limit 910 is also adjusted to accommodate the new duty cycle, but as the peak inductor current does not reach the current limit, this change has no other effect on the regulator or its output. Line 930 shows that the current limit does not vary with the duty cycle, apart from the deliberately imposed settling time.
In operation the comparator 650 works as previously described in relation to
Comparator 1000 compares the sum of measured inductor current and slope compensation signal to the current limit reference signal VCL, VCL being the sum of VLIM and the adjustment signal VADJ. If the measured inductor current rises to too high a value, comparator 1000 produces a second control signal to turn off the main switch at that point in the cycle. In steady state, VADJ will settle to the value which cancels the effect of the slope compensation signal on the current limit, so the current threshold will be when the measured inductor current corresponds to VLIM.
The two control signals feed into an “OR” gate 1010 such that latch 670 is reset should either condition be met, i.e. the slope compensated current monitor 660 output signal exceed either error amplifier output VERR or the signal (=VLIM+VADJ). Each clock cycle the former will occur first if the regulator is not in current limit, the second will occur first if the regulator is in current limit, i.e. the inductor current has to be limited before reaching the value required to satisfy the load current demand.
It is envisaged that such techniques as disclosed herein has many applications. One such use is on an audio power management circuit. It could also be used in circuits providing backlighting for displays (e.g. using white LEDs). It is also particularly suited to camera flash circuits which tend to operate in current limit during the flash time.
Similar techniques could also be used to prevent subharmonic oscillations in related circuits, for example in Class-D audio amplifiers (e.g. in M. Berkhout, “Integrated Overcurrent Protection System for Class-D Audio Power Amplifiers,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2237-2245, November 2005).
The foregoing example is for illustrative purposes only. For example the converter may be any type of DC-DC converter, such as a boost or inverting or non-inverting buck-boost converter instead of the buck converter illustrated. The integrator, ramp generator, clamp or sample and hold circuit may be of any kind known or devised. Or instead of the sample-and-hold circuit a further current source (as 672), switch (as 675) and integrator could be used alternately with current source 672, switch 675 and integrator 680 with the switch in each case left open for a further cycle (therefore holding the signal constant during this further cycle) before being closed. The resultant signals could then be multiplexed together to obtain a signal made up of the portions of the resultant signals when being held throughout the cycle (switch open).
Consequently, it should be understood that other embodiments and variations are envisaged without departing from the spirit and scope of the invention.
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|U.S. Classification||323/284, 323/282, 363/21.17|
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