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Publication numberUS7606060 B2
Publication typeGrant
Application numberUS 11/832,190
Publication dateOct 20, 2009
Filing dateAug 1, 2007
Priority dateJan 18, 2006
Fee statusLapsed
Also published asUS7295458, US20070165445, US20090034345
Publication number11832190, 832190, US 7606060 B2, US 7606060B2, US-B2-7606060, US7606060 B2, US7606060B2
InventorsYuen H. Chan, William V. Huott, Donald W. Plass
Original AssigneeInternational Business Machines Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Eight transistor SRAM cell with improved stability requiring only one word line
US 7606060 B2
Abstract
An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.
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Claims(2)
1. A static random access memory comprising in combination:
a plurality of bi-stable memory cells arranged in rows and columns;
a pair of write bit lines common to each memory cell in a column;
a single pre-charged read bit line common to each memory cell in a column;
each cell including a pair of write data field effect transistors respectively connecting said each cell in column to said pair of write bit lines, a gate of each of said pair connected respectively to said pair of write bit lines for writing data into each cell;
a single read data field effect transistor connecting said each cell to said read bit line, with its gate coupled to a node of said each cell in a column for reading data from said cell;
a single field effect transistor connected to said pair of write data field effect transistors and said read data field effect transistor with its gate coupled to a single word line to control both read access and write access to said each cell.
2. A static random access memory as in claim 1 wherein:
said pair of write data field effect transistors are each n-type field effect transistors;
said read data field effect transistor is an n-type field effect transistor, and
said single field effect transistor is an n-type field effect transistor.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

This application contains subject matter that is related to the subject matter of the following applications, each of which is assigned to the same assignee as this application, International Business Machines Corporation of Armonk, N.Y. Each of the below listed applications is hereby incorporated herein by reference in its entirety. This application is a continuation of U.S. patent application Ser. No. 11/334,647 filed on Jan. 18, 2006, now U.S. Pat. No. 7,295,458 issued on Nov. 13, 2007, and is hereby incorporated herein by reference in its entirety.

TRADEMARKS

IBM ® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. S/390, Z900 and z990 and other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an improved Static Random Access Memory (SCRAM) cell and more particularly to stable cell with only one word line.

2. Description of the Background

Typical prior art CMOS SRAM cells have a six-transistor typology, such as that shown in FIG. 1. Two P channel field effect transistors (PPETs) P1 and P2 act as pull up transistors and two N channel field effect transistors (NFETs) N1 and N2 act as pull down transistors. Two NFETs N3 and N4 serve as pass gates to control access to the cell for reading and writing to the cell. These pass gates N3 and N4 are connected to a word line WL. P1 and N1 form an inverter and P2 and N2 form another inverter. As shown these invertors are cross-coupled to form a bi-stable cell.

An SRAM array has n rows and m columns of SRAM cells with cells of a row sharing a single word line WL and cells of a column sharing a pair of bit lines BLL and BLR. During standby, all of the word lines WL are low (i.e., at GND) and all bit lines are biased to the voltage level of the power supply Vdd. Thus, the pass-gate transistors of each cell are shut off. A cell state representing a 1 data bit, for example, is established with P1 and N2 on and P2 and N1 off so that the node L at the left of the cell is high (Vdd) and the node R at the right of the cell is low (GND). With P1 and N2 off and P2 and N1 on, node L is low and node R is high. During access time to the SRAM array a row is selected by driving its word line WL high to Vdd, which turns on half of the pass gates connected to that word line, namely, those connected to a high node. Thus, for each cell along a word line, one pass gate is turned on.

During a read access, a cell in a selected column, where its bit lines precharge devices are turned off, pulls down one of the bit lines (BL or BR) from its pre-charged high state (Vdd) by the “ON” passgate of the full selected cell (one that is selected in both the word and column dimension). A sense amplifier detects the differential voltage between the bit lines and generates an output. The cells along a selected word line likewise generate a differential voltage, but these signals are ignored. These cells along a selected word line that are not selected by the columns are commonly referred to as “half selected” cells. Unselected columns could have their bit line precharge devices either turned off or stayed on, depending on the design preference.

High performance designs, such as for cache where read and write operations are performed within a short clock cycle, cell beta ratios that are typically in a range between 2.2 and 3.5 in order to avoid unintended changes in the state of a cell due to a so called “half-selected cell disturbance”. The beta ratio is a function of the ratio of the channel resistance of the pass gate transistor to the channel resistance of the pull down transistor. Half-selected cell disturbance occurs when a word line connected to a memory cell of unselected columns with bit lines biased to a predetermined Vdd is activated. This causes the body voltage of a pass-gate transistor of a non-selected cell to be more conductive than the cell pull down transistor, there by causing the ground state node (“0”node) to switch states and disrupt the state of the memory cell.

In fast switching environments a high beta ratio improves the margin preventing half-selected cell disturbances. However a higher-beta ratio results in decreased cell performance, such as lower write. Particularly, sub 100 nm silicon technologies are having increased problems with cell SRAM cell stability when trying to write to the cells at high rates due to the inherent variations in individual cell beta ratios as a result to limitations in the degree to which device channel parameters can be controlled at these extremely small devices sizes.

Adding additional transistors to the basic six-transistor SRAM cell have been proposed in the prior art in order to prevent half-selected cell disturbance by providing separate access paths for reading and writing. However these prior art proposals have not proven satisfactory. Particularly, as they employ two separate word lines, one for writing and one for reading.

SUMMARY OF THE INVENTION

An object of this invention is the provision of an improved SRAM cell that provides cell stability, with reduced cell area requirements without impacting the writing speed to the cell.

Another object of the invention is the provision of an improved SRAM cell with separate cell access paths for reading and writing and only a single word line. Briefly, this invention contemplates the provision of an SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

DESCRIPTION OF THE DRAWINGS

The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a typical prior art six transistor SRAM CELL.

FIG. 2 is a schematic of one embodiment of an SRAM cell in accordance with the teachings of this invention.

The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 2 of the drawings, the part of the cell comprised of PFET pull-up transistors P1 and P2 and NFET pull-down transistors N1 and N2 connected to nodes R and L is the same as the corresponding part of the prior art cell discussed above, where like reference numbers are used, and will not be further explained here. In accordance with the teachings of this invention, a pair of NFET write access transistors 24 and 26 provides access to the nodes R and L in a write operation. The source of the left hand NFET 24 is connected to the left node L and the source of the right hand NFET 26 is connected to the right node R. The drains of NFET 24 and 26 are connected to the drains of NFET 24 and 26 and whose drain is connected to ground. The gate of the left write access NFET 24 is connected to a normally low left write bit line wbl_1 and the gate of the right write access NFET 26 is connected to a normally low right write bit line wbl_r. The write bit access lines wbl_l and wbl_r are common to all of the cells in a column and are coupled to word line control logic, not shown. The gate of the word line NFET 28 is connected to a word line wl that is common to all the cells in a row and is connected to word line control logic, not shown.

Read access to the cell nodes L and R is provided by a read access NFET 32 whose drain is connected to ground via the word line NFET 28 and whose source is connected to a read bit line rbl, which is common to all the cells in a column and is coupled to control logic and a sense amplifier, not shown. The gate of NFET 32 is connected to the node L in this exemplary embodiment.

In operation, in order to write to the cell, one of the normally low write bit lines wbl_l or wbl_r is brought high while the other write bit line remains in its normally low state. Concurrently, the word line wl is brought high. The node (L or R) connected to write access NFET (24 or 26) whose gate is high is therefore connected to ground through that write access NFET and the word line NFET 28. If the node is in a high state, it is pulled down, causing the cell to change states. If the node is in a low state, the cell maintains its existing state.

Similarly, in order to read the state of the cell, the read bit line rl is precharged high before a read operation. Concurrently, the word line wl is brought high so that the drain of read access transistor 32 is connected to ground via word line NFET 28. In this exemplary embodiment, with the gate of read access NFET 32 connected to the left node L, if the node L is in its high state, NFET 32 conducts, connecting the read bit line rl to ground via NFET 28, thus providing a signal indicating the high state of that side of the cell. If node L is in a low state. NFET 32 does not conduct, and bit line rl remains in its high state, thus providing a signal indicating the low state of that side of the cell.

While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8325510 *Feb 12, 2010Dec 4, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Weak bit compensation for static random access memory
US8385136Oct 27, 2010Feb 26, 2013Taiwan Semiconductor Manufacturing Company, Ltd.Memory circuit and method of operating the same
US20110199839 *Feb 12, 2010Aug 18, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Weak bit compensation for static random access memory
Classifications
U.S. Classification365/154, 365/156, 365/155
International ClassificationG11C11/00
Cooperative ClassificationG11C8/14, G11C11/412
European ClassificationG11C8/14, G11C11/412
Legal Events
DateCodeEventDescription
Dec 10, 2013FPExpired due to failure to pay maintenance fee
Effective date: 20131020
Oct 20, 2013LAPSLapse for failure to pay maintenance fees
May 31, 2013REMIMaintenance fee reminder mailed