|Publication number||US7612465 B2|
|Application number||US 12/041,503|
|Publication date||Nov 3, 2009|
|Filing date||Mar 3, 2008|
|Priority date||Dec 7, 2004|
|Also published as||US7345378, US20060119992, US20080150358|
|Publication number||041503, 12041503, US 7612465 B2, US 7612465B2, US-B2-7612465, US7612465 B2, US7612465B2|
|Inventors||Lawrence G. Pearce|
|Original Assignee||Intersil Americas Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Non-Patent Citations (2), Classifications (19), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present application claims priority to and is a continuation application of U.S. application Ser. No. 11/006,006 entitled “Power Supply Circuit Containing Multiple DC-DC Converters Having Programmable Output Current Capabilities,” filed on Dec. 7, 2004, now U.S. Pat. No. 7,345,378, which is herein incorporated by reference in its entirety.
The continuing growth and expansion of the electronics industry has been accompanied by a demand for DC power supplies having a wide variety of performance specifications. Depending upon the application, it is not uncommon for a given product design to employ a plurality of DC power supplies, which not only differ in terms of their output voltages, but which have differing current capabilities among the power supply outputs. Although power supply manufacturers have been able to provide power supplies that meet these and other user needs, each power supply's implementation is often custom-configured to a given specification (e.g., output voltage and output current drive capability). This means that the user must maintain an inventory of different power supply circuits, to accommodate variations in application requirements. To reduce cost and inventory complexity, the user would prefer that performance characteristics of the various circuits within its power supply inventory be programmable or user-configurable.
The above-mentioned problems of current systems are addressed by embodiments of the present invention and will be understood by reading and studying the following specification. The following summary is made by way of example and not by way of limitation. It is merely provided to aid the reader in understanding some of the aspects of the invention.
In one embodiment, a method of operating a power converter circuit is provided. The method comprises selectively coupling control signals to at least one output driver stage of a plurality of output driver stages of the power converter circuit to obtain a desired output at a select output port of the plurality of output ports. Wherein each output driver stage has a defined current drive capacity that is output to the select output port in response to the control signals.
Before detailing the user-configurable power supply circuit architecture of the invention, it should be observed that the present invention resides primarily in a novel combination of conventional controlled power supply and switching circuits and components therefor. In a practical implementation, these circuits and components may be readily implemented using field programmable gate array (FPGA)-configured, application specific integrated circuit (ASIC) chip sets and associated power MOSFETs. Consequently, the configuration of such circuits and components have, for the most part, been depicted in the drawings by readily understandable schematic-block diagrams, which show only those specific features that are pertinent to the present invention, so as not to obscure the disclosure with details which will be readily apparent to those skilled in the art having the benefit of the description herein. Thus, the diagrammatic illustrations are primarily intended to show the major functional components of the invention in convenient groupings that will enable the present invention to be more readily understood.
The synchronous buck converter has been selected for representation in
Attention is now directed to
In a similar manner, although only four (power MOSFET-based) output driver stages (designated output driver stages 31, 32, 33, 34) and only two output voltage terminals (designated output terminals Vout1 and Vout2) have been shown, it is to be understood that the invention is not limited to these or any other numbers of output driver stages or output voltage terminals. As in the case of illustrating only two control loops 10 and 20, the illustrated numbers of output driver stages and output voltage terminals are for the purpose of facilitating a ready understanding of the functionality and architecture of the invention, without unduly burdening the drawings.
In order to provide an appreciation for the considerable flexibility that is offered by the architecture of the present invention, each of the output driver stages 31-34 has a respectively different current drive capability. It is to be observed, however, that the current drive capabilities of the output driver stages need not be respectively different from one another; they may be the same, or differ in any manner desired. For purposes of the present description, output driver stage 31 may have a one amp (1 A) current drive capability, output driver stage 32 may have a two amp (2A) current drive capability, output driver stage 33 may have a three amp (3 A) current drive capability, and output driver stage 34 may have a four amp (4 A) current drive capability.
Each output driver stage includes an upper electronic driver device, such as an upper power field effect transistor, or UFET, having its source-drain current flow path coupled between an upper power supply rail UR and a common or phase node, which corresponds to one of the phase nodes A, B, C and D. Each of the phase nodes of the output driver stages constitutes an available output port that is intended to be selectively externally connected to one end of an output inductor L, a second end of which is coupled to an output filter capacitor C and one of a pair of output voltage ports Vout1 and Vout2 of the overall power supply. Each output driver stage further includes a lower electronic driver device, such as a lower power FET, or LFET, having its source-drain current flow path coupled between a lower power supply rail LR and one of the phase nodes A, B, C and D.
In an integrated circuit realization of the invention the inductors and output capacitors would be external to the integrated circuit, and the phase nodes of the output stages would be individually available to connect as required. In a multi-component module realization, inductors and capacitors would be included in the module with access to pins allowing arbitrary connection to output stages and output voltage ports.
The gate control input to the UFET of a respective output driver stage is selectively coupled through an upper input switch SWU to the upper PWM output of a selected buck controller which, in the illustrated embodiment corresponds to either buck controller 10 or buck controller 20. Similarly, the gate control input to the LFET of a respective output driver stage is selectively coupled through a lower input switch SWL to the lower PWM output of one of the buck controllers 10 and 20. Buck controller 10 provides PWM gate drive signals UG1 and LG1 associated with a first output voltage V1, and being respectively available for controlling the turn ON/OFF times of the UFET and LFET of an output driver stage controlled thereby, while buck controller 20 provides PWM gate drive signals UG2 and LG2 associated with a second output voltage V2, and being respectively available for controlling the turn ON/OFF times of the UFET and LFET of an output driver stage controlled thereby.
As a non-limiting example, in the illustrated embodiment of a dual buck DC-DC converter architecture having a two-fold output voltage supply capability (V1 and V2), the input switches SWU and SWL that are used to interface the outputs of the buck controllers with the control inputs of the output driver stages may be readily implemented as digital components, such as 2:1 logic gates, control inputs for which comprise single pin connections. These pins are tied to one of a pair of preselected voltages for establishing the path through the switch, as will be readily understood by one skilled in the art.
Considering the (four amp) output driver stage 34, as a non-limiting example, configuring the switches SWU and SWL, so as to connect the gate drive inputs of its UFET and LFET to the PWM gate drive signals UG1 and LG1 supplied by buck controller 10, will result in the output driver stage 34 producing an output waveform consistent with an output voltage of V1 volts in accordance with the PWM signal supplied by buck controller 10, and at a current drive capability of four amps. In order to supply this voltage V1 at external output port Vout1, it is necessary for the user to externally connect the phase node A of output driver stage 34 to the output inductor L that feeds the voltage output port Vout1. This set of connections will result in voltage output port Vout1 supplying an output voltage of V1 volts at a current drive capability of four amps.
If it is desired to increase the current drive capability from its value of four amps for the output voltage V1 being supplied at the voltage output Vout1, it is necessary to configure the input switches SWU and SWL for the UFET and LFET pairs of one or more of the other output driver stages 33, 32 and 31, in the same manner described above for the four amp output driver stage 34, and to also provide a connection between one or more of the phase nodes B, C and D of these output driver stages to the input side of the inductor L that feeds the voltage output port Vout1.
Take, for example, the case where it is desired to provide voltage output port Vout1 with an output voltage V1 having a five amp current drive capability, and to provide voltage output port Vout2 with an output voltage V2 having a five amp current drive capability. One solution would be to have the (four amp) output driver stage 34 connected in the manner described above, and to also connect the (one amp) output driver stage 31 in the same manner. Namely, the switches SWU and SWL coupled to the control gates of the UFET and LFET of (one amp) output driver stage 31 would be connected to receive the gate drive signals UG1 and LG1 supplied by the buck controller 10. This will result in the one amp output driver stage 31 producing at phase node D waveform in accordance with the PWM signal supplied by buck controller 10, and a current capability of one amp.
In order to supply this additional one amp current drive capability to the output port Vout1, it is necessary for the user to connect the phase node D of output driver stage 31 to the output inductor L that feeds the voltage output port Vout1. What results is a summation of the currents from the four amp node A of the output driver stage 34 and the one amp node D of the output driver stage 31 to the output inductor L that is connected to the voltage output port Vout1. This combining of the outputs of the output driver stages 34 and 31 therefore produces, at voltage output port Vout1, a voltage of V1 volts at a total current drive capability of five amps.
To provide an output voltage V2 at a five amp current drive capability at the voltage output port Vout2, use may be readily made of the two amp and three amp current drive capabilities of the remaining two output driver stages 32 and 33, respectively. Since each of these driver stages is to supply the voltage V2, it is necessary to apply to their associated input switches SWU and SWL, that are respectively coupled to the gates of the UFET and LFET of output driver stages 32 and 33, the PWM gate drive signals UG2 and LG2 that are generated by the V2 voltage buck controller 20. This will cause the output driver stage 32 to produce an output voltage waveform averaging V2 volts and a drive current capability of two amps at the phase node C, in accordance with the PWM signal supplied by buck controller 20.
It will also cause the three-amp output driver stage 33 to produce an output voltage waveform averaging V2 volts and a current drive capability of three amps, in accordance with the PWM signal supplied by buck controller 20. In order to supply, to the output port Vout2, the voltage V2 that is represented as the average at the phase nodes B and C of respective output drive stages 32 and 33, it is necessary for the user to externally connect the phase node B of output driver stage 33 and the phase node C of output driver stage 32 to the output inductor L that feeds the voltage output port Vout2. This results in a summation of the currents from the two-amp node C of output driver stage 32 and the three-amp node B of output driver stage 33 to the output inductor L that is connected to the voltage output port Vout2. This summation of the outputs of output driver stages 32 and 33 therefore produces a voltage V2 having a current capability of five amps at voltage output port Vout2.
It is to be understood that the foregoing description is not limitative of the capabilities of the two buck controller, four output driver stage power supply architecture example shown in
For example, the dual buck architecture of
As an alternative to the use of pulse generator 100, its function may be implemented by selectively supplying a control command to buck controllers 10 and 20, so as to cause selected ones of the output drivers 31, 32, 33 and 34 to generate output pulses at any of nodes A, B, C and D, which are coupled via inductors L to the output ports Vout1 and Vout2.
In response to pulse generator 100 supplying a test pulse to the front end of the inductor L feeding voltage output port Vout1, monitoring logic circuit 200 should detect a response pulse at each of phase nodes A and D. Similarly, in response to pulse generator 100 supplying a test pulse to the front end of the inductor L feeding voltage output port Vout12 monitoring logic circuit 200 should detect a response pulse at each of phase nodes B and C. If each of these response pulses is not detected a fault is indicated for the corresponding phase node. Thus, for example, for the case of voltage output port Vout1, if a response pulse is detected at phase node A, but not at phase node D, it may be inferred that there has been a miswiring of the phase node D of driver stage 31, and a fault indication for phase node D is produced. Likewise, for the case of voltage output port Vout2, if a response pulse is detected at phase node B, but not at phase node C, it may be inferred that there has been a miswiring of the phase node C of driver stage 32, and a fault indication for phase node C is produced.
In addition to connecting fault detection logic circuitry in the manner described above, combinational logic circuitry may also be used to used to automatically internally configure connections provided through the respective switches SWU and SWL from the buck controllers to the output driver stages, based upon the external connections made by the user from the phase nodes of the output drivers to the inductors feeding the voltage output ports. To this end, as diagrammatically illustrated in
The pulse generator and MUX 300 is used to individually pulse the inputs to one of the switches SWU of each respective output driver stage. As a non-limiting example, the pulse may be applied to upper switch SWU, so that the phase node of a respective driver stage will be briefly pulled high (to the voltage of the upper power supply rail UR) in response to the pulse. A combinational logic circuit 400 then looks at the front ends of the inductors (which have been externally connected by the user to respective phase nodes of the output driver stages) for the presence of a response pulse. For each inductor at which a response pulse is produced, logic circuit 400 knows that an external connection has been provided by the user from the phase node of the output driver stage to the gate of which a pulse has been applied by pulse generator and MUX 300. Knowing which phase nodes produce output pulses, logic circuit 400 may then proceed to selectively enable either upper or lower feedthrough paths of the switches SWU and SWL, and thereby configure the output drivers' input switches to the appropriate buck controller.
As will be appreciated from the foregoing description, the desire to make voltage and current drive output parameters of a power supply user-configurable is readily achieved in accordance with the power supply architecture of the present invention, having a plurality of synchronous buck DC-DC converter control loops that provide respectively different output voltages, together with a plurality of output driver stages having given current drive capabilities, and inputs to which are connectable via a set of selectively (user- or automatically) configurable switches to PWM outputs of any of the buck converter control loops. The output of each output driver stage is selectively connectable by the user to any of plural output voltage ports, so that each output voltage port is capable of supplying any of the respectively different output voltages provided by the synchronous buck DC-DC converter control loops, and has an output current capability that depends upon which output driver stages are coupled to it.
While I have shown and described several embodiments in accordance with the present invention, it is to be appreciated that the same is not limited thereto but, as described above, is susceptible to numerous changes and modifications as will be readily understood by a person skilled in the art. Consequently, I do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4659942||Jun 3, 1985||Apr 21, 1987||The Charles Stark Draper Laboratory, Inc.||Fault-tolerant power distribution system|
|US5625546||Sep 13, 1995||Apr 29, 1997||Inventio Ag||Method and apparatus for the variable allocation of static inverters to at least one load|
|US5808879||Dec 26, 1996||Sep 15, 1998||Philips Electronics North America Corporatin||Half-bridge zero-voltage-switched PWM flyback DC/DC converter|
|US6018233||Jun 30, 1997||Jan 25, 2000||Sundstrand Corporation||Redundant starting/generating system|
|US6037752||Jun 30, 1997||Mar 14, 2000||Hamilton Sundstrand Corporation||Fault tolerant starting/generating system|
|US6144327||Aug 12, 1997||Nov 7, 2000||Intellectual Property Development Associates Of Connecticut, Inc.||Programmably interconnected programmable devices|
|US6369559 *||Nov 15, 2000||Apr 9, 2002||Texas Instruments Incorporated||Buck controller coprocessor to control switches|
|US6429674 *||Apr 28, 2000||Aug 6, 2002||Jon E. Barth||Pulse circuit|
|US6768225||Aug 30, 2001||Jul 27, 2004||Digipower Manufacturing Inc.||Multiple power sources control system|
|US6906433 *||Jun 11, 2002||Jun 14, 2005||Intel Corporation||Method and apparatus for regulating the efficiency of a power supply in a computer system|
|US7043648||Apr 28, 2003||May 9, 2006||Kabushiki Kaisha Toshiba||Multiprocessor power supply system that operates a portion of available power supplies and selects voltage monitor point according to the number of detected processors|
|US20030218384||May 20, 2003||Nov 27, 2003||Kabushiki Kaisha Toshiba||Electronic apparatus and power control method|
|US20050225177||Apr 13, 2004||Oct 13, 2005||Jacobs James K||Integrated power supply system|
|1||"Monolithic 6 AMP DC-DC Stop-Down Regulator", "Intersil Datasheet, EL7566. FN7102.5", Dec. 1, 2004, pp. 1-14, Publisher: Intersil.|
|2||"Single Synchronous Buck Regulators With Intergrated FET", "Intersil Datasheet ISL6410, ISL6410A. FN9149.3", Sep. 17, 2004, pp. 1-13, Publisher: Intersil.|
|U.S. Classification||307/24, 307/140, 307/115, 307/113|
|International Classification||H01H9/54, H02B1/24, H02J1/00|
|Cooperative Classification||Y10T307/352, H02M3/1584, Y10T307/406, Y10T307/747, Y10T307/391, Y10T307/305, Y10T307/414, H02M2001/008, Y10T307/76, Y10T307/944, Y10T307/865|
|Sep 3, 2009||AS||Assignment|
Owner name: INTERSIL AMERICAS INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PEARCE, LAWRENCE GEORGE;REEL/FRAME:023186/0801
Effective date: 20041118
|Apr 30, 2010||AS||Assignment|
Owner name: MORGAN STANLEY & CO. INCORPORATED,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC.;AND OTHERS;REEL/FRAME:024320/0001
Effective date: 20100427
Owner name: MORGAN STANLEY & CO. INCORPORATED, NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC.;AND OTHERS;REEL/FRAME:024320/0001
Effective date: 20100427
|Jun 14, 2013||REMI||Maintenance fee reminder mailed|
|Nov 3, 2013||LAPS||Lapse for failure to pay maintenance fees|
|Dec 24, 2013||FP||Expired due to failure to pay maintenance fee|
Effective date: 20131103
|Jun 10, 2014||AS||Assignment|
Owner name: INTERSIL AMERICAS LLC, CALIFORNIA
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