|Publication number||US7615801 B2|
|Application number||US 11/159,972|
|Publication date||Nov 10, 2009|
|Filing date||Jun 23, 2005|
|Priority date||May 18, 2005|
|Also published as||EP1882274A2, US20060261348, WO2006124183A2, WO2006124183A3|
|Publication number||11159972, 159972, US 7615801 B2, US 7615801B2, US-B2-7615801, US7615801 B2, US7615801B2|
|Inventors||Sei-Hyung Ryu, Jason R. Jenny, Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Hudson McDonald Hobgood|
|Original Assignee||Cree, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (106), Non-Patent Citations (49), Referenced by (1), Classifications (19), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation in part of and claims priority from co-pending U.S. patent application Ser. No. 11/131,880, filed May 18, 2005, the content of which is hereby incorporated herein by reference as if set forth in its entirety.
This invention relates to power semiconductor devices and related methods of fabricating power semiconductor devices and, more particularly, to high voltage silicon carbide devices and related methods of fabricating high voltage silicon carbide devices.
Power devices are widely used to carry large currents and support high voltages. Modern power devices are generally fabricated from monocrystalline silicon semiconductor material. One type of power device is the thyristor. A thyristor is a bistable power semiconductor device that can be switched from an off-state to an on-state, or vice versa. Power semiconductor devices, such as thyristors, high-power bipolar junction transistors (“HPBJT”), or power metal oxide semiconductor field effect transistors (“MOSFET”), are semiconductor devices capable of controlling or passing large amounts of current and blocking high voltages.
Thyristors are generally known and conventionally have three terminals: an anode, a cathode, and a gate. A thyristor is turned on by applying a short current pulse across the gate and the cathode. Once the thyristor turns on, the gate may lose its control to turn off the device. The turn off may be achieved by applying a reverse voltage across the anode and the cathode. A specially designed gate turn-off thyristor (“GTO”), however, is typically turned off by a reverse gate pulse. The GTO thyristors generally start conduction by some trigger input and then behave as diodes thereafter.
A thyristor is a highly rugged device in terms of transient currents, di/dt and dv/dt capability. The forward voltage (VF) drop in conventional silicon thyristors is about 1.5 V to 2 V, and for some higher power devices, about 3 V. Therefore, the thyristor can control or pass large amounts of current and effectively block high voltages (i.e., a voltage switch). Although VF determines the on-state power loss of the device at any given current, the switching power loss may become a dominating factor affecting the device junction temperature at high operating frequencies. Because of this, the switching frequencies possible using conventional thyristors may be limited in comparison with many other power devices.
Two parameters of a thyristor are the built-in potential (which is a characteristic of any given semiconductor material's bandgap) and the specific on-resistance (i.e., the resistance of the device in the linear region when the device is turned on). The specific on-resistance for a thyristor is typically as small as possible so as to provide a large current per unit area for a given voltage applied to the thyristor. The lower the specific on-resistance, the lower the VF drop is for a given current rating. The minimum VF for a given semiconductor material is its built-in potential (voltage).
Some conventional thyristors may be manufactured in silicon (Si) or gallium arsenide (GaAs), such as a silicon controlled rectifier (“SCR”). Thyristors formed in Si or GaAs, however, may have certain performance limitations resulting from the Si or GaAs material itself, such as the minority carrier lifetime and the thickness of the drift region. The largest contributory factor to specific on-resistance is the resistance of the thick low-doped drift region of the thyristor. In a majority carrier device, such as a MOSFET, the specific on-resistance is determined by the doping concentration and the thickness of the lightly doped drift layer. In a minority carrier (or bipolar) device, carriers, both electrons and holes, are injected into this drift layer, and substantially reduces the specific on-resistance. This effect is referred to as conductivity modulation. As the rated voltage of a thyristor increases, typically the thickness of the drift region increases and the doping of the drift region decreases. For effective conductivity modulation, a very long minority carrier lifetime is required. At the same time, the amount carriers stored in the drift layer increases because the volume of the drift layer is increased. Therefore, the time required to remove access carriers in the drift layer, which determines the switching times and frequencies, may increase dramatically for devices with higher blocking voltage ratings.
Development efforts in power devices have includes the use of silicon carbide (SiC) devices for power devices. Silicon carbide has a wide bandgap, a lower dielectric constant, a high breakdown field strength, a high thermal conductivity, and a high saturation electron drift velocity relative to silicon. These characteristics may allow silicon carbide power devices to operate at higher temperatures, higher power levels and with lower specific on-resistance and higher switching frequency than conventional silicon-based power devices. A theoretical analysis of the superiority of silicon carbide devices over silicon devices is found in a publication by Bhatnagar et al. entitled “Comparison of 6H—SiC, 3C—SiC and Si for Power Devices”, IEEE Transactions on Electron Devices, Vol. 40, 1993, pp. 645-655, the disclosure of which is hereby incorporated herein by reference as if set forth in its entirety. A thyristor fabricated in silicon carbide is described in commonly assigned U.S. Pat. No. 5,539,217 to Edmond et al. entitled Silicon Carbide Thyristor, the disclosure of which is hereby incorporated herein by reference as if set forth in its entirety.
Notwithstanding the potential advantages of silicon carbide, it may be difficult to fabricate power devices, including thyristors, in silicon carbide. For example, these high voltage devices are typically formed using a lightly doped epitaxial layer on a highly doped n-type conductivity silicon carbide substrate having a thickness of from about 300 to about 400 μm. Low resistivity p-type silicon carbide substrates may not be available as a result of the available acceptor species (Aluminum and Boron) having deep energy levels that may result in carrier freeze out. Thus, the exclusive use of n-type substrates may limit the polarity of available high voltage devices. For example, only p-channel Insulated Gate Bipolar Transistors (IGBTs) and pnpn thyristors may be available. In addition, the available devices may only be capable of blocking voltages in one direction.
Furthermore, in order to form a blocking junction at the substrate-epitaxial layer interface, a planar edge termination structure may be formed or an edge beveling process may be used to reduce the likelihood of premature breakdown at the edges of the device. Forming planar edge termination structures on a backside of the device may be difficult and costly to implement as extensive processing may be needed after removal of the 300 to 400 μm thick n-type substrate. Edge beveling may include etching through the substrate or grinding/polishing the sidewalls of the device, which may also be difficult because the voltage blocking epitaxial layers are generally much thinner than the substrate.
Some embodiments of the present invention provide high voltage silicon carbide (SiC) devices. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer, has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface of the voltage blocking SiC substrate. A third region of SiC is provided on the second SiC layer and has the second conductivity type. A fourth region of SiC is provided in the second SiC layer, has the first conductivity type and is adjacent to the third region of SiC. First and second contacts are provided on the first and third regions of SiC, respectively.
In further embodiments of the present invention, third and fourth contacts may be provided on the second and fourth regions of SiC, respectively. A first metal overlayer may be provided on the first and third contacts that electrically connects the first and third contacts. A second metal overlayer may be provided on the second and fourth contacts that electrically connects the second and fourth contacts. In certain embodiments of the present invention, the first and second overlayers may be patterned so as to allow light to enter the device such that the device turns on responsive to the light.
In still further embodiments of the present invention, the voltage blocking substrate may be a bidirectional voltage blocking layer and have a bevel edge termination structure. In certain embodiments of the present invention, the voltage blocking substrate may be a boule grown substrate. The bevel edge termination structure may provide a first blocking junction between the first surface of the voltage blocking substrate and the first SiC layer and a second blocking junction between the second surface of the voltage blocking substrate and the second SiC layer. The device may have a voltage drop of about 2.7 V at the first blocking junction. The resistance of the first SiC layer beneath the first region of SiC may be large enough so that a small lateral current Il in the first SiC layer can result in a voltage drop of 2.7 V, which can trigger the thyristor on.
In some embodiments of the present invention, the voltage blocking substrate may be a 4H—SiC high purity substrate having a carrier concentration no greater than about 1.0×1015 cm−3. The voltage blocking substrate may have a thickness of greater than about 100 μm.
In further embodiments of the present invention, the first conductivity type may be p-type SiC and the second conductivity type may be n-type SiC. In other embodiments of the present invention, the first conductivity type may be n-type SiC and the second conductivity type may be p-type SiC.
In still further embodiments of the present invention, the first and second SiC layers may have carrier concentrations of from about 1.0×1015 cm−3 to about 1.0×1019 cm−3. The first and third regions of SiC may have carrier concentrations of from about 1.0×1016 cm−3 to about 1.0×1021 cm−3. The second and fourth regions of SiC may have carrier concentrations of from about 1.0×1017 cm−3 to about 1.0×1021 cm−3.
In some embodiments of the present invention, the first and second SiC layers may have thicknesses of from about 0.1 μm to about 20.0 μm. The first and third regions of SiC may have thicknesses of from about 0.1 μm to about 10.0 μm. The second and fourth regions of SiC may extend into the first SiC layer and the second SiC layer, respectively, from about 0.1 μm to about 2.0 μm.
In further embodiments of the present invention, the SiC device may be a thyristor. The first and third regions of SiC may be anode regions of the thyristor and the second and fourth regions of SiC may be gate regions of the thyristor.
Still further embodiments of the present invention provide silicon carbide (SiC) thyristors. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first SiC anode region is provided on the first SiC layer and has the second conductivity type. A first SiC gate region is provided in the first SiC layer, has the first conductivity type and is adjacent to the first SiC anode region. A second SiC layer having the first conductivity type is provided on a second surface of the voltage blocking SiC substrate. A second SiC anode region is provided on the second SiC layer and has the second conductivity type. A second SiC gate region is provided in the second SiC layer, has the first conductivity type and is adjacent to the second SiC anode region. First, second, third and fourth contacts are provided on the first and second SiC anode regions and on the first and second SiC gate regions, respectively.
While the present invention is described above primarily with reference to high voltage devices and thyristors, methods of fabricating high voltage devices and thyristors are also provided herein.
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompass both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the device in one of the Figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
Embodiments of the present invention are described with reference to a particular polarity conductivity type for various layers/regions. However, as will be appreciated by those of skill in the art, the polarity of the regions/layers may be inverted to provide an opposite polarity device. For example, the terms “first conductivity type” and “second conductivity type” refer to opposite conductivity types such as n or p-type, however, each embodiment described and illustrated herein includes its complementary embodiment as well.
Some embodiments of the present invention prevention provide thyristors and/or other power devices that may include silicon carbide voltage blocking substrates as discussed herein. Thus, while embodiments of the present invention are described with reference to thyristors, embodiments of the present invention may be used in other devices, such as metal oxide semiconductor field effect transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs) or other such high voltage power devices.
According to some embodiments of the present invention, high voltage power devices are provided on voltage blocking substrates. Thus, voltage blocking and carrier injecting pn junctions can be provided by forming silicon carbide layers on first and second opposite surfaces of the voltage blocking substrate, i.e. the voltage blocking substrate may allow the provision of high voltage devices having bi-directional blocking capabilities. Furthermore, according to some embodiments of the present invention discussed herein removal of from about 300 to about 400 μm of the substrate may no longer be necessary to provide a bevel termination structure, therefore, allowing for voltage blocking in multiple directions, i.e., bi-directional devices. Bi-directional devices, for example, bi-directional thyristors, typically have on and off states for both positive and negative anode voltages and, therefore, may be useful for high voltage AC applications. Bi-directional thyristors are discussed in Physics of Semiconductor Devices by S. M. Sze at pages 229-234, the content of which is incorporated herein by reference as if set forth in its entirety.
Furthermore, an edge beveling process may also be simplified according to some embodiments of the present invention as the location of the pn blocking junctions (i.e., between the voltage blocking substrate and the layer formed thereon) may be well defined and the voltage blocking layer (substrate) accounts for most of the thickness of the device. Thus, according to some embodiments of the present invention, high voltage devices may be provided on n-type and/or p-type silicon carbide substrates, which may increase the polarities available in high voltage devices as discussed further herein.
As used herein, a “voltage blocking substrate” refers to an n-type or a p-type high purity silicon carbide substrate capable of providing a bi-directional voltage blocking layer for a high voltage device. In some embodiments of the present invention, the voltage blocking substrate may be a 4H—SiC substrate having a carrier concentration of no greater than about 1.0×1015 cm−3 and a thickness of greater than about 100 μm. The details with respect to the voltage blocking substrate and methods of fabricating the voltage blocking substrate are discussed in commonly assigned U.S. patent application Ser. No. 11/052,679 (Client Ref. No. P0475) entitled Process for Producing Silicon Carbide Crystals Having Increased Minority Carrier Lifetimes, filed Feb. 7, 2005, the disclosure of which is incorporated herein by reference as if set forth herein in its entirety.
Referring now to
In some embodiments of the present invention, the substrate 10 may be a boule grown substrate. Boule grown substrates are discussed in commonly assigned U.S. patent application Ser. No. 10/686,795, filed Oct. 16, 2003, entitled Methods of Forming Power Semiconductor Devices using Boule-Grown Silicon Carbide Drift Layers and Power Semiconductor Devices Formed Thereby, the disclosure of which is hereby incorporated herein by reference as if set forth in its entirety.
As further illustrated in
According to embodiments of the present invention illustrated in
A second layer of SiC 12 may be provided on a second surface 10B of the substrate 10. The second layer of SiC 12 may be a p-type or an n-type SiC epitaxial layer or implanted layer. According to embodiments of the present invention illustrated in
First and second regions of SiC 22 and 23 may be provided on the first layer of SiC 14 and the second layer of SiC 12, respectively. In embodiments of the present invention illustrated in
Third and fourth regions of SiC 20 and 21 may be provided in the first layer of SiC 14 and the second layer of SiC 12, respectively. In embodiments of the present invention illustrated in
First through fourth ohmic contacts 26, 27, 28 and 29 are provided on the third and fourth regions of SiC 20 and 21 and the first and second regions of SiC 22 and 23, respectively. As used herein the term “ohmic contact” refers to contacts where an impedance associated therewith is substantially given by the relationship of Impedance=V/I, where V is a voltage across the contact and I is the current, at substantially all expected operating frequencies (i.e., the impedance associated with the ohmic contact is substantially the same at all operating frequencies) and currents. The first and second ohmic contacts 26 and 27 may provide gate contacts for a thyristor according to some embodiments of the present invention. Similarly, the third and fourth ohmic contacts 28 and 29 may provide anode contacts for a thyristor according to some embodiments of the present invention. In some embodiments of the present invention, the first and second ohmic contacts 26 and 27 provided on the third and fourth n+ regions of SiC 20 and 21, respectively, may include, for example, nickel (Ni) contacts. Furthermore, third and fourth ohmic contacts 28 and 29 provided on the first and second p+ regions of SiC 22 and 23, respectively, may include, for example, aluminum (Al) based contacts, such Al/(Titanium (Ti)) contacts. It will be understood that these metals are provided for exemplary purposes only and that other suitable metals may also be used without departing from the scope of the present invention.
A first metal overlayer 30 may be provided on the first and third ohmic contacts 26 and 28, respectively, and a second metal overlayer 31 may be provided on the second and fourth ohmic contacts 27 and 29, respectively. As illustrated in
In some embodiments of the present invention, the device may be designed to turn on by applying voltages greater than a break-over voltage. In these embodiments of the present invention, the overlayers 30 may not be patterned. However, in embodiments of the present invention where the device is designed to be turned on optically (light activated), the first and second overlayers 30 and 31 may be patterned so as to allow light to enter the device. For example, a planar view of a light activated thyristor according to some embodiments of the present invention is illustrated in
As further illustrated in
It will be understood that although embodiments of the present invention discussed with respect to
As discussed above, with respect to
The use of voltage blocking 4H—SiC substrates may enable the design and fabrication of, for example, the bidirectional thyristors. As discussed above, the two terminal structure of
Referring now to
The first layer of SiC 14 may be a p-type or an n-type silicon carbide layer and may grown on the first surface 10A of the substrate 10 or implanted in the first surface 10A of the substrate 10 without departing from the scope of the present invention. If the first layer of SiC 14 is an n-type implanted region, for example, nitrogen or phosphorus ions may be implanted. If, on the other hand the first layer of SiC is a p-type implanted region, for example, Al or Boron(B) ions may be implanted. In embodiments of the present invention discussed with respect to
A second layer of SiC 12 may be formed on a second surface 10B of the substrate 10. The second layer of SiC 12 may be p-type or n-type SiC and may be grown on the second surface 10B of the substrate or implanted in the second surface 10B of the substrate 10. According to embodiments of the present invention illustrated in
A third layer of SiC 16 may be formed on the first layer of SiC 14. The third layer of SiC 16 may be p-type or n-type SiC and may be grown on a surface of the first layer of SiC 14 or implanted in the surface of the first layer of SiC 14. According to embodiments of the present invention illustrated in
A fourth layer of SiC 18 may be formed on the second layer of SiC 12. The fourth layer of SiC 18 may be p-type or n-type SiC and may be grown on a surface of the second layer of SiC 12 or implanted in the surface of the second layer of SiC 12. According to embodiments of the present invention illustrated in
Referring now to
As further illustrated in
Referring now to
As further illustrated in
Referring now to
Referring now to
As illustrated in
It will be understood by those having skill in the art that, although the processing steps in the fabrication of high voltage devices according to embodiments of the present invention are discussed in a particular order herein, the order of steps in
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3280386||Nov 7, 1962||Oct 18, 1966||Westinghouse Electric Corp||Semiconductor a.c. switch device|
|US3360696 *||May 14, 1965||Dec 26, 1967||Rca Corp||Five-layer symmetrical semiconductor switch|
|US3629011||Sep 6, 1968||Dec 21, 1971||Matsushita Electric Ind Co Ltd||Method for diffusing an impurity substance into silicon carbide|
|US3964091 *||Oct 11, 1974||Jun 15, 1976||Bbc Brown Boveri & Company Limited||Two-way semiconductor switch|
|US3988760||Feb 26, 1975||Oct 26, 1976||General Electric Company||Deep diode bilateral semiconductor switch|
|US4032364||May 3, 1976||Jun 28, 1977||General Electric Company||Deep diode silicon controlled rectifier|
|US4466172||Jul 27, 1981||Aug 21, 1984||American Microsystems, Inc.||Method for fabricating MOS device with self-aligned contacts|
|US4779126||Sep 12, 1986||Oct 18, 1988||International Rectifier Corporation||Optically triggered lateral thyristor with auxiliary region|
|US4811065||Jun 11, 1987||Mar 7, 1989||Siliconix Incorporated||Power DMOS transistor with high speed body diode|
|US5111253||Aug 28, 1990||May 5, 1992||General Electric Company||Multicellular FET having a Schottky diode merged therewith|
|US5170231||May 24, 1991||Dec 8, 1992||Sharp Kabushiki Kaisha||Silicon carbide field-effect transistor with improved breakdown voltage and low leakage current|
|US5184199||Jun 5, 1990||Feb 2, 1993||Sharp Kabushiki Kaisha||Silicon carbide semiconductor device|
|US5270554||Jun 14, 1991||Dec 14, 1993||Cree Research, Inc.||High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide|
|US5348895||Jun 2, 1993||Sep 20, 1994||Texas Instruments Incorporated||LDMOS transistor with self-aligned source/backgate and photo-aligned gate|
|US5384270||Nov 10, 1993||Jan 24, 1995||Fuji Electric Co., Ltd.||Method of producing silicon carbide MOSFET|
|US5385855||Feb 24, 1994||Jan 31, 1995||General Electric Company||Fabrication of silicon carbide integrated circuits|
|US5393999||Jun 9, 1994||Feb 28, 1995||Texas Instruments Incorporated||SiC power MOSFET device structure|
|US5396085||Dec 28, 1993||Mar 7, 1995||North Carolina State University||Silicon carbide switching device with rectifying-gate|
|US5416342 *||Jun 23, 1993||May 16, 1995||Cree Research, Inc.||Blue light-emitting diode with high external quantum efficiency|
|US5506421||Nov 24, 1992||Apr 9, 1996||Cree Research, Inc.||Power MOSFET in silicon carbide|
|US5510281||Mar 20, 1995||Apr 23, 1996||General Electric Company||Method of fabricating a self-aligned DMOS transistor device using SiC and spacers|
|US5510630||Oct 18, 1993||Apr 23, 1996||Westinghouse Electric Corporation||Non-volatile random access memory cell constructed of silicon carbide|
|US5539217||Aug 9, 1993||Jul 23, 1996||Cree Research, Inc.||Silicon carbide thyristor|
|US5629531||Dec 9, 1994||May 13, 1997||Cree Research, Inc.||Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures|
|US5663580||Mar 15, 1996||Sep 2, 1997||Abb Research Ltd.||Optically triggered semiconductor device|
|US5710059||Apr 24, 1996||Jan 20, 1998||Abb Research Ltd.||Method for producing a semiconductor device having a semiconductor layer of SiC by implanting|
|US5726463||Aug 7, 1992||Mar 10, 1998||General Electric Company||Silicon carbide MOSFET having self-aligned gate structure|
|US5734180||Jun 5, 1996||Mar 31, 1998||Texas Instruments Incorporated||High-performance high-voltage device structures|
|US5763905||Jul 9, 1996||Jun 9, 1998||Abb Research Ltd.||Semiconductor device having a passivation layer|
|US5804483||Aug 6, 1996||Sep 8, 1998||Abb Research Ltd.||Method for producing a channel region layer in a sic-layer for a voltage controlled semiconductor device|
|US5814859||Nov 15, 1995||Sep 29, 1998||General Electric Company||Self-aligned transistor device including a patterned refracting dielectric layer|
|US5837572||Jan 10, 1997||Nov 17, 1998||Advanced Micro Devices, Inc.||CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein|
|US5851908||May 8, 1995||Dec 22, 1998||Abb Research Ltd.||Method for introduction of an impurity dopant in SiC, a semiconductor device formed by the method and a use of highly doped amorphous layer as a source for dopant diffusion into SiC|
|US5877041||Jun 30, 1997||Mar 2, 1999||Harris Corporation||Self-aligned power field effect transistor in silicon carbide|
|US5917203||Mar 31, 1997||Jun 29, 1999||Motorola, Inc.||Lateral gate vertical drift region transistor|
|US5972801||Nov 8, 1995||Oct 26, 1999||Cree Research, Inc.||Process for reducing defects in oxide layers on silicon carbide|
|US5976936||Jul 15, 1997||Nov 2, 1999||Denso Corporation||Silicon carbide semiconductor device|
|US6020600||Sep 26, 1997||Feb 1, 2000||Nippondenso Co., Ltd.||Silicon carbide semiconductor device with trench|
|US6025233||May 20, 1999||Feb 15, 2000||Ngk Insulators, Ltd.||Method of manufacturing a semiconductor device|
|US6025608||Nov 18, 1997||Feb 15, 2000||Abb Research Ltd.||Semiconductor device of SiC with insulating layer and a refractory metal nitride layer|
|US6054352||Feb 20, 1998||Apr 25, 2000||Fuji Electric Co., Ltd.||Method of manufacturing a silicon carbide vertical MOSFET|
|US6096607||Aug 17, 1998||Aug 1, 2000||Fuji Electric Co., Ltd.||Method for manufacturing silicon carbide semiconductor device|
|US6100169||Jun 8, 1998||Aug 8, 2000||Cree, Inc.||Methods of fabricating silicon carbide power devices by controlled annealing|
|US6107142||Jun 8, 1998||Aug 22, 2000||Cree Research, Inc.||Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion|
|US6117735||Jan 5, 1999||Sep 12, 2000||Fuji Electric Co., Ltd.||Silicon carbide vertical FET and method for manufacturing the same|
|US6133587||Feb 13, 1998||Oct 17, 2000||Denso Corporation||Silicon carbide semiconductor device and process for manufacturing same|
|US6162665||May 23, 1995||Dec 19, 2000||Ixys Corporation||High voltage transistors and thyristors|
|US6165822||Jan 4, 1999||Dec 26, 2000||Denso Corporation||Silicon carbide semiconductor device and method of manufacturing the same|
|US6180958||Feb 7, 1997||Jan 30, 2001||James Albert Cooper, Jr.||Structure for increasing the maximum voltage of silicon carbide power transistors|
|US6204135||Jan 31, 2000||Mar 20, 2001||Siced Electronics Development Gmbh & Co Kg||Method for patterning semiconductors with high precision, good homogeneity and reproducibility|
|US6221700||Jul 28, 1999||Apr 24, 2001||Denso Corporation||Method of manufacturing silicon carbide semiconductor device with high activation rate of impurities|
|US6228720||Feb 18, 2000||May 8, 2001||Matsushita Electric Industrial Co., Ltd.||Method for making insulated-gate semiconductor element|
|US6238967||Apr 12, 1999||May 29, 2001||Motorola, Inc.||Method of forming embedded DRAM structure|
|US6239463||Aug 28, 1997||May 29, 2001||Siliconix Incorporated||Low resistance power MOSFET or other device containing silicon-germanium layer|
|US6246076||Aug 28, 1998||Jun 12, 2001||Cree, Inc.||Layered dielectric on silicon carbide semiconductor structures|
|US6297100||Sep 29, 1999||Oct 2, 2001||Denso Corporation||Method of manufacturing silicon carbide semiconductor device using active and inactive ion species|
|US6303508||Dec 16, 1999||Oct 16, 2001||Philips Electronics North America Corporation||Superior silicon carbide integrated circuits and method of fabricating|
|US6316791||Feb 22, 2000||Nov 13, 2001||Siced Electronics Development Gmbh & Co. Kg||Semiconductor structure having a predetermined alpha-silicon carbide region, and use of this semiconductor structure|
|US6344663||Apr 15, 1996||Feb 5, 2002||Cree, Inc.||Silicon carbide CMOS devices|
|US6399996||Jul 20, 2000||Jun 4, 2002||Apd Semiconductor, Inc.||Schottky diode having increased active surface area and method of fabrication|
|US6420225||Mar 13, 2001||Jul 16, 2002||Apd Semiconductor, Inc.||Method of fabricating power rectifier device|
|US6429041||Jul 13, 2000||Aug 6, 2002||Cree, Inc.||Methods of fabricating silicon carbide inversion channel devices without the need to utilize P-type implantation|
|US6448160||Apr 6, 2000||Sep 10, 2002||Apd Semiconductor, Inc.||Method of fabricating power rectifier device to vary operating parameters and resulting device|
|US6455892||Sep 15, 2000||Sep 24, 2002||Denso Corporation||Silicon carbide semiconductor device and method for manufacturing the same|
|US6551865||Mar 28, 2002||Apr 22, 2003||Denso Corporation||Silicon carbide semiconductor device and method of fabricating the same|
|US6573534||Mar 10, 1999||Jun 3, 2003||Denso Corporation||Silicon carbide semiconductor device|
|US6593620||Oct 6, 2000||Jul 15, 2003||General Semiconductor, Inc.||Trench DMOS transistor with embedded trench schottky rectifier|
|US6610366||Apr 12, 2001||Aug 26, 2003||Cree, Inc.||Method of N2O annealing an oxide layer on a silicon carbide layer|
|US6653659||Jun 7, 2002||Nov 25, 2003||Cree, Inc.||Silicon carbide inversion channel mosfets|
|US6759684||Nov 14, 2001||Jul 6, 2004||National Institute Of Advanced Industrial Science And Technology||SiC semiconductor device|
|US6767843||Oct 1, 2001||Jul 27, 2004||Cree, Inc.||Method of N2O growth of an oxide layer on a silicon carbide layer|
|US6770911||Sep 12, 2001||Aug 3, 2004||Cree, Inc.||Large area silicon carbide devices|
|US20020038891||Jul 24, 2001||Apr 4, 2002||Sei-Hyung Ryu||Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel|
|US20020047125||Nov 14, 2001||Apr 25, 2002||Nat ' L Inst. Of Advanced Industrial And Technology||SiC semicoductor device|
|US20020102358||Oct 26, 2001||Aug 1, 2002||Das Mrinal Kanti||Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment|
|US20030047748 *||Sep 12, 2001||Mar 13, 2003||Anant Agarwal||Large area silicon carbide devices|
|US20030079676||Oct 28, 2002||May 1, 2003||Alexandre Ellison||High resistivity silicon carbide single crystal|
|US20030160302 *||Feb 22, 2002||Aug 28, 2003||Igor Sankin||Silicon carbide bipolar junction transistor with overgrown base region|
|US20040119076||Oct 30, 2003||Jun 24, 2004||Sei-Hyung Ryu||Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors and methods of fabricating vertical JFET limited silicon carbide metal- oxide semiconductor field effect transistors|
|US20040211980||Apr 24, 2003||Oct 28, 2004||Sei-Hyung Ryu||Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same|
|US20040212011||Apr 24, 2003||Oct 28, 2004||Sei-Hyung Ryu||Silicon carbide mosfets with integrated antiparallel junction barrier schottky free wheeling diodes and methods of fabricating the same|
|US20040222501||May 8, 2003||Nov 11, 2004||Kordina Olof Claes Erik||Chemical vapor deposition epitaxial growth|
|US20050000406||Apr 23, 2004||Jan 6, 2005||Okmetic Oyj||Device and method for producing single crystals by vapor deposition|
|US20050082542 *||Oct 16, 2003||Apr 21, 2005||Sumakeris Joseph J.||Methods of forming power semiconductor devices using boule-grown silicon carbide drift layers and power semiconductor devices formed thereby|
|US20060137600 *||Aug 22, 2003||Jun 29, 2006||Alexandre Ellison||Lightly doped silicon carbide wafer and use thereof in high power devices|
|DE10036208A1||Jul 25, 2000||Feb 14, 2002||Siced Elect Dev Gmbh & Co Kg||Current control semiconductor device has current within lateral channel region controlled via at least one depletion zone|
|DE19809554A1||Mar 5, 1998||Sep 10, 1998||Denso Corp||Silicon carbide semiconductor device|
|DE19832329A1||Jul 17, 1998||Feb 4, 1999||Siemens Ag||Silicon carbide semiconductor structure manufacturing method|
|DE19900171A1||Jan 5, 1999||Jul 8, 1999||Denso Corp||Silicon carbide semiconductor structure especially a vertical power MOSFET has stable FET characteristics and high gate insulation reliability|
|EP0637069B1||Jul 30, 1993||Jan 31, 2001||Cree, Inc.||Method of obtaining high quality silicon dioxide passivation on silicon carbide|
|EP1058317A2||May 25, 2000||Dec 6, 2000||Intersil Corporation||Low voltage dual-well MOS device|
|EP1204145A2||Oct 23, 2001||May 8, 2002||Matsushita Electric Industrial Co., Ltd.||Semiconductor element|
|JP2000049167A||Title not available|
|JP2000082812A||Title not available|
|JP2000106371A||Title not available|
|JPH0334466A||Title not available|
|JPH01117363A||Title not available|
|JPH03157974A||Title not available|
|JPH08264766A||Title not available|
|JPH09205202A||Title not available|
|JPH11191559A||Title not available|
|JPH11238742A||Title not available|
|JPH11261061A||Title not available|
|JPH11266017A||Title not available|
|JPH11274487A||Title not available|
|WO1995005006A1||Aug 5, 1994||Feb 16, 1995||Cree Research, Inc.||Silicon carbide thyristor|
|1||A.K. Agarwal, J.B. Casady, L.B. Rowland, W.F. Valek, and C.D. Brandt, "1400 V 4H-SiC Power MOSFET's," Materials Science Forum vols. 264-268, pp. 989-992, 1998.|
|2||A.K. Agarwal, L.B. Casady, L.B. Rowland, W.F. Valek, M.H. White, and C.D. Brandt, "1.1 kV 4H-SiC Power UMOSFET's," IEEE Electron Device Letters, vol. I8, No. 12, pp. 586-588, Dec. 1997.|
|3||A.K. Agarwal, N.S. Saks, S.S. Mani, V.S. Hegde and P.A. Sanger, "Investigation of Lateral Resurf, 6H-SiC MOSFETs," Materials Science Forum, vols. 338-342, pp. 1307-1310, 2000.|
|4||A.K. Agarwal, S. Seshadri, and L.B. Rowland, "Temperature Dependence of Fowler-Nordheim Current in 6H-and 4H-SiC MOS Capacitors," IEEE Electron Device Letters, vol. 18, No. 12, Dec. 1997, pp. 592-594.|
|5||A.V. Suvorov, L.A. Lipkin, G.M. Johnson, R. Singh and J.W. Palmour, "4H-SiC Self-Aligned Implant-Diffused Structure for Power DMOSFETs," Materials Science Forum vols. 338-342, pp. 1275-1278, 2000.|
|6||Agarwal et al. "A Critical Look at the Performance Advantages and Limitations of 4H-SiC Power UMOSFET Structures," 1996 IEEE ISPSD and IC's Proc. , May 20-23, 1996, pp. 119-122.|
|7||Baliga, Power Semiconductor Devices, Chapter 7, PWS Publishing, 1996.|
|8||Bhatnagar et al. "Comparison of 6H-SiC, 3C-SiC, and Si for Power Devices," IEEE Transactions on Electron Devices, vol. 40, No. 3, Mar. 1993, pp. 645-655.|
|9||Capano, M.A., et al., Ionization Energies and Electron Mobilities in Phosphorus-and Nitrogen-Implanted 4H-Silicon Carbide, IEEE ICSCRM Conference 1999, Research Triangle Park, North Carolina (Oct. 10-13, 1999).|
|10||D. Alok, E. Arnold, and R. Egloff, "Process Dependence of Inversion Layer Mobility in 4H-SiC Devices," Materials Science Forum, vols. 338-342, pp. 1077-1080, 2000.|
|11||Das, Mrinal K. Graduate thesis entitled, Fundamental Studies of the Silicon Carbide MOS Structure. Purdue University, 1999.|
|12||Dastidar, Sujoyita, A Study of P-Type Activation in Silicon Carbide, Thesis (Purdue University, May 1998).|
|13||Fukuda et al. "Improvement of SiO2/4H-SiC Interface Using High-Temperature Hydrogen Annealing at Low Pressure and Vacuum Annealing," Jpn J. Appl. Phys. vol. 38, Apr. 1999, pp. 2306-2309.|
|14||G.Y. Chung, C.C. Tin, J.R. Williams, K. McDonald, M. Di Ventra, S.T. Pantelides, L.C. Feldman, and R.A. Weller, "Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4H polytype of silicon carbidc," Applied Physics Letters, vol. 76, No. 13, pp. 1713-1715, Mar. 2000.|
|15||G.Y. Chung, C.C. Tin, J.R. Williams, K. McDonald, R.K. Chanana, R.A. Weller, S.T. Pantelides, L.C. Feldman, O.W. Holland, M.K. Das, and J.W. Palmour, "Improved Inversion Channel Mobility for 4H-SiC MOSFETs Following High Temperature Anneals in Nitric Oxide," IEEE Electron Device Letters, vol. 22, No. 4, Apr. 2001.|
|16||International Search Report and Written Opinion of the International Search Authority corresponding to PCT/US2006/014673, mailed Mar. 12, 2007.|
|17||Ishidoh, Michiharu et al., "A New High Power Symmetrical GTO" Conference record of the IEEE Industry Applications Society Annual Meeting (Cat. No. 89CH2792-0) IEEE, New York, New York, USA (May 1, 1989), pp. 1273-1278.|
|18||J. Tan, J.A. Cooper, Jr., and Mr. R. Melloch, "High-Voltage Accumulation-Layer UMOSFETs in 4H-SiC," IEEE Electron Device Letters, vol. 19, No. 12, pp. 487-489, Dec. 1998.|
|19||J.B. Casady, A.K. Agarwal, L.B. Rowland, W.F. Valek, and C.D. Brandt, "900 V DMOS and 1100 V UMOS 4H-SiC Power FETs," IEEE Device Research Conference, Ft. Collins, CO Jun. 23-25, 1997.|
|20||J.N. Shenoy, J.A. Cooper and M.R. Meelock, "High-Voltage Double-Implanted Power MOSFETs in 6H-SiC," IEEE Electron Device Letters, vol. 18, No. 3, pp. 93-95, Mar. 1997.|
|21||K. Ueno and Tadaaki Oikawa, "Counter-Doped MOSFET's of 4H-SiC," IEEE Electron Device Letters, vol. 20, No. 12, pp. 624-626, Dec. 1999.|
|22||K. Ueno, R. Asai, and T. Tsuji. "4H-SiC MOSFET's Utilizing the H2 Surface Cleaning Technique." IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 244-246.|
|23||L.A. Lipkin and J.W. Palmour, "Low interface state density oxides on p-type SiC," Materials Science Forum vols. 264-268, pp. 853-856, 1998.|
|24||Lipkin et al. "Challenges and State-of-the-Art Oxides in SiC," Mat. Res. Soc. Symp. Proc. vol. 640, 2001, pp. 27-29.|
|25||Lipkin et al. "Insulator Investigation on SiC for Improved Reliability," IEEE Transactions on Electron Devices. vol. 46, No. 3, Mar. 1999, pp. 525-532.|
|26||M. K. Das, L.A. Lipkin, J.W. Palmour, G.Y. Chung, J.R. Williams, K. McDonald, and L.C. Feldman, "High Mobility 4H-SiC Inversion Mode MOSFETs Using Thermally Grown, NO Annealed SiO2," IEEE Device Research Conference, Denver, CO Jun. 19-21, 2000.|
|27||M.K. Das, J.A. Cooper, Jr., M.R. Melloch, and M.A. Capano, "Inversion Channel Mobility in 4H- and 6H-SiC MOSFETs," IEEE Semiconductor Interface Specialists Conference, San Diego, CA, Dec. 3-5, 1998.|
|28||Mondal et al. "An Integrated 500-V Power DSMOSFET/Antiparallel Rectifier Device with Improved Diode Reverse Recovery Characteristics," IEEE Electron Device Letters, vol. 23, No. 9, Sep. 2002, pp. 562-564.|
|29||Motorola Power MOSFET Transistor Databook, 4th edition. Motorola, INc., 1989, pp. 2-5-4-2-5-7.|
|30||P.M. Shenoy and B.J. Baliga, "The Planar 6H-SiC ACCUFET: A New High-Voltage Power MOSFET Structure," IEEE Electron Device Letters, vol. 18, No. 12, pp. 589-591, Dec. 1997.|
|31||Palmour et al. "SiC Device Technology: Remaining Issues," Diamond and Related Materials. vol. 6, 1997, pp. 1400-1404.|
|32||Patel, R., et al., Phosphorus-Implanted High-Voltage N.sup.+ P 4H-SiC Junction Rectifiers, Proceedings of 1998 International Symposium on Poer Semiconductor Devices & ICs, pp. 387-390 (Kyoto).|
|33||R. Schömer, P. Friedrichs, D. Peters, H. Mitlehner, B. Weis, and D. Stephani, "Rugged Power MOSFETs in 6H-SiC with Blocking Capability up to 1800 V," Materials Science Forum vols. 338-342, pp. 1295-1298, 2000.|
|34||R. Schorner, P. Friedrichs, D. Peters, and D. Stephani, "Significantly Improved Performance of MOSFETs on Silicon Carbide Using the 15R-SiC Polytype," IEEE Electron Device Letters, vol. 20, No. 5, pp. 241-244, May 1999.|
|35||Ranbir Singh, Sei-Hyung Ryu and John W. Palmour, "High Temperature, High Current, 4H-SiC Accu-DMOSFET," Materials Science Forum vols. 338-342, pp. 1271-1274, 2000.|
|36||Rao et al. "Al and N Ion Implantations in 6H-SiC," Silicon Carbide and Related Materials. 1995 Conf, Kyoto, Japan. Published 1996.|
|37||Rao et al. "P-N Junction Formation in 6H-SiC by Acceptor Implantation into N-Type Substrate," Nuclear Instruments and Methods in Physics Research B. vol. 106, 1995, pp. 333-338.|
|38||Ryu et al. Article and Presentation: "27 mOmega-cm2, 1.6 kV Power DiMOSFETs in 4H-SiC," Proceedings of the 14 International Symposium on Power Semiconductor Devices & ICs 2002, Jun. 4-7, 2002, Santa Fe, NM.|
|39||S. Sridevan and B. Jayant Baliga, "Lateral N-Channel Inversion Mode 4H-SiC MOSFET's," IEEE Electron Device Letters, vol. 19, No. 7, pp. 228-230, Jul. 1998.|
|40||S.T. Pantelides, "Atomic Scale Engineering of SiC Dielectric Interfaces," DARPA/MTO High Power and ONR Power Switching MURI Reviews, Rosslyn, VA, Aug. 10-12, 1999.|
|41||Sze, Physics of Semiconductor Devices, Second Edition, John Wiley & Sons, 1981, pp. 196-198 and 229-234.|
|42||U.S. Appl. No. 10/686,795, "Methods of Forming Power Semiconductor Devices Using Boule-Grown Silicon Carbide Drift Layers and Power Semiconductor Devices Formed Thereby," filed Oct. 16, 2003.|
|43||U.S. Appl. No. 11/052,679, "Process for Producing Silicon Carbide Crystals Having Increased Minority Carrier Lifetimes," filed Feb. 7, 2005.|
|44||U.S. Appl. No. 60/294,307, "Method of N2O Growth on an Oxide Layer on a Silicon Carbide Layer," filed May 31, 2001.|
|45||U.S. Appl. No. 60/435,212, "Vertical JFET Limited Silicon Carbide Power Metal-Oxide Semiconductor Field Effect Transistors and Methods of Fabricating Vertical JFET Limited Silicon Carbide Power Metal-Oxide Semiconductor Field Effect Transistors," filed Dec. 20, 2002.|
|46||V .R. Vathulya, H. Shang, and M.H. White, "A Novel 6H-SiC Power DMOSFET with Implanted P-Well Spacer," IEEE Electronic Device Letters, vol. 20, No. 7, Jul. 1999, pp. 354-356.|
|47||V.R. Vathulya and M.H. White, "Characterization of Channel Mobility on Implanted SiC to Determine Polytype Suitability for the Power DIMOS Structure," Electronic Materials Conference, Santa Barbara, CA, Jun. 30-Jul. 2, 1999.|
|48||Williams et al. "Passivation of the 4H-SiC/SiO2 Interface with Nitric Oxide," Materials Science Forum. vols. 389-393 (2002), pp. 967-972.|
|49||Y. Wang, C. Weitzel, and M. Bhatnagar, "Accumulation-Mode SiC Power MOSFET Design Issues," Materials Science Forum, vols. 338-342, pp. 1287-1290.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
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|U.S. Classification||257/123, 257/E29.215, 257/E29.115, 257/128, 257/E27.052|
|Cooperative Classification||H01L29/747, H01L29/0661, H01L29/87, H01L2924/10156, H01L29/1608, H01L29/6606, H01L29/66068|
|European Classification||H01L29/66M4T, H01L29/66M4D, H01L29/747, H01L29/87, H01L29/06C, H01L29/06C4|
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|Oct 19, 2010||CC||Certificate of correction|
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