Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS7626249 B2
Publication typeGrant
Application numberUS 11/972,418
Publication dateDec 1, 2009
Filing dateJan 10, 2008
Priority dateJan 10, 2008
Fee statusPaid
Also published asUS7824966, US20090179313, US20090311832
Publication number11972418, 972418, US 7626249 B2, US 7626249B2, US-B2-7626249, US7626249 B2, US7626249B2
InventorsMaria Clemens Y. Quinones, Jocel P. Gomez
Original AssigneeFairchild Semiconductor Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Flex clip connector for semiconductor device
US 7626249 B2
Abstract
A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.
Images(9)
Previous page
Next page
Claims(20)
1. A semiconductor die package comprising:
a semiconductor die having a first surface comprising a die contact region, and a second surface;
a leadframe structure comprising a die attach pad and a lead structure, wherein the semiconductor die is attached to the die attach pad; and
a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region,
wherein the first electrical contact region of the flex clip connector is coupled to the die contact region and wherein the second electrical contact region of the flex clip connector is coupled to the lead structure.
2. The semiconductor die package of claim 1 wherein the lead structure is a source lead structure and the die contact region is a source die contact region.
3. The semiconductor die package of claim 1 wherein the semiconductor die comprises a MOSFET.
4. The semiconductor die package of claim 1 wherein the lead structure is a first lead structure and wherein the leadframe structure comprises a second lead structure, wherein the first lead structure and the second lead structure are separated from the die attach pad.
5. The semiconductor die package of claim 4 wherein the first lead structure is a source lead structure and the second lead structure is a gate lead structure.
6. The semiconductor die package of claim 1 wherein the flexible insulator covers a conductive region between the first electrical contact region and the second electrical contact region.
7. The semiconductor die package of claim 1 wherein the package is a leadless package.
8. The semiconductor die package of claim 1 further comprising a first conductive adhesive coupling the first electrical contact to the die contact region and a second conductive adhesive coupling the second electrical contact to the lead structure.
9. The semiconductor die package of claim 1 further comprising a molding material covering at least a portion of the semiconductor die and the leadframe structure.
10. the semiconductor die package of claim 1 wherein the leadframe structure further comprises a dummy lead structure.
11. The semiconductor die package of claim 1 wherein leadframe structure comprises a base material.
12. The semiconductor die package of claim 11 wherein the base material comprises copper.
13. The semiconductor die package of claim 11 wherein the leadframe structure comprises another material that is plated on the base material.
14. The semiconductor die package of claim 11 wherein the semiconductor die comprises a gate structure.
15. The semiconductor die package of claim 14 wherein the gate structure is a trenched gate structure.
16. The semiconductor die package of claim 15 wherein the semiconductor die comprises a power MOSFET comprising the trenched gate structure.
17. The semiconductor die package of claim 16 wherein the package is a leadless package.
18. The semiconductor die package of claim 9 wherein the flexible insulator comprises a material that is different from the molding material.
19. The semiconductor die package of claim 1 wherein the flexible insulator comprises polyimide or polyamide.
20. The semiconductor die package of claim 1 wherein the flexible insulator comprises a dielectric layer, and wherein the flex clip connector further comprises a metal layer disposed on the dielectric layer.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS

Not applicable.

BACKGROUND

Semiconductor die packages using conductive clip structures are known. For example, a semiconductor die package using a rigid clip structure is described in U.S. Pat. No. 6,465,276. The clip structure described in U.S. Pat. No. 6,465,276 connects a source region and a gate region at one surface of a semiconductor die to corresponding leads. In this patent, source and gate contacts of the clip are initially connected by a tie bar. Separation of the gate and source connection of the clip is performed by laser cutting of the connecting tie bar, after clip is bonded to the die. Also, the clip structure is only applicable to a single die configuration.

Since the clip structure is rigid, the horizontal alignment of any two structures to be connected by the clip structure needs to be relatively precise. If two structures are not horizontally aligned, the clip structure may not contact one of the structures and rework may be needed. Also, the additional laser cutting step can increase processing time during the package assembly process.

Embodiments of the invention address these, and other problems, individually and collectively.

BRIEF SUMMARY

Embodiments of the invention include semiconductor die packages and method for making the same.

One embodiment of the invention is directed to a semiconductor die package comprising a semiconductor die having a first surface comprising a die contact region, and a second surface. It also has a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It further includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region, where the first electrical contact region of the flex clip connector is coupled to the die contact region and wherein the second electrical contact region of the flex clip connector is coupled to the lead structure. The first and second electrical contact regions can form part of a conductive trace or can be connected to a conductive trace.

Another embodiment of the invention is directed to a method for forming a semiconductor die package. The method includes attaching a semiconductor die having a first surface comprising a die contact region, and a second surface, to a leadframe structure comprising a die attach pad and a lead structure. The semiconductor die is attached to the die attach pad. The method also includes attaching a flex clip connector to the semiconductor die and the leadframe structure, where the flex clip connector comprises a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.

These and other embodiments of the invention are described in further detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a perspective view of a semiconductor die package according to an embodiment of the invention. A portion of the molding material is cut away and the flex clip connector is lifted to show its underside.

FIGS. 2( a) and 2(b) show cross-sectional side views of the semiconductor die package shown in FIG. 2( e) along the lines A-A and B-B, respectively.

FIGS. 2( c) and 2(d) show detailed regions C and D in FIGS. 2( a) and 2(b) respectively.

FIG. 2( e) shows a top plan view of the package shown in FIG. 1.

FIGS. 3( a)-3(f) show side views of various semiconductor die package configurations including flex clip connectors.

FIGS. 4( a)-4(l) show plan views of various flex clip connectors.

FIG. 5( a) shows a side view of another semiconductor die package according to an embodiment of the invention.

FIG. 5( b) shows a top view of the package illustrated in FIG. 5( a).

FIG. 5( c) shows another side view of the package illustrated in FIG. 5( a).

FIG. 5( d) is a top perspective view of the package illustrated in FIG. 5( a).

FIG. 5( e) is a bottom perspective view of the package illustrated in FIG. 5( c).

FIGS. 6( a)-6(e) illustrate precursors that are formed in the formation of a semiconductor die package according to an embodiment of the invention.

FIG. 7 shows a schematic cross-section of a vertical power MOSFET.

DETAILED DESCRIPTION

Embodiments of the invention are directed to packages and methods incorporating a flex clip connector. The flex clip connector may have conductive traces of any suitable thickness, and a flexible supporting insulator that supports the conductive traces. Ends of the conductive traces may incorporate contact regions that will contact regions of one or more semiconductor dies as well as regions of a leadframe structure. The insulator may be comprised of one or more dielectric layers. In some embodiments, the insulator comprises a plastic material such as polyimide or polyamide. The flex clip connectors can be used in semiconductor die packages that have one, two, or any suitable number of semiconductor dies. Since the flex clip connectors according to embodiments of the invention can be already formed prior to assembling the other components of a semiconductor die package, fewer steps are needed in a final semiconductor die package assembly process.

The flex clip connectors according to embodiments of the invention can replace or can be used in conjunction with conventional rigid copper clips for bonding applications, for example, in low RDSon power packages. An exemplary flex clip connector can be attached to a die bonded leadframe or substrate as one piece, even if the semiconductor die package to be formed has multiple semiconductor dice. The flex clip connector can be attached to a semiconductor die bonded leadframe structure in a block or group of flex clip connectors, so that throughput is higher as compared to singulated copper clip attach methods. The flex clip connectors according to embodiments of the invention are also lightweight, and intricate copper trace designs can be used to accommodate various package designs. Embodiments of the invention also provide a maximized electrical connection of a DMOS (diffused metal oxide semiconductor) die source pad to a leadframe structure for reduced device on-resistance through conductive trace (e.g., copper trace) conduction. The flex clip connectors can also be designed for top-set or down-set package configurations where the top surface of a semiconductor die does not form a perfectly flat plane with a bonding surface of a corresponding lead structure bonding post.

FIG. 1 shows a semiconductor die package according to one embodiment of the invention. The semiconductor die package includes a semiconductor die 3 having a first surface comprising at least one die contact region. In this example, the at least one die contact region comprises source contact regions covered with conductive adhesives 2-1, 2-2, and a gate contact region covered with another conductive adhesive 2-3. A second surface of the semiconductor die 3, that is opposite the first surface of the semiconductor die 3, may be attached to a die attach pad 5 (or drain pad in this example) of a leadframe structure 80. The semiconductor die 3 may be attached to the die attach pad 5 using a conductive adhesive 4 such as solder. The die attach pad 5 serves as a drain connection (i.e., an output connection) for a MOSFET (metal oxide semiconductor field effect transistor) device in the semiconductor die 3.

The semiconductor dies used in the semiconductor die packages according to preferred embodiments of the invention include vertical power transistors. Exemplary vertical power transistors are described, for example, in U.S. Pat. Nos. 6,274,905, and 6,351,018, both of which are assigned to the same assignee as the present application, and both which are herein incorporated by reference in their entirety for all purposes. Vertical power transistors include VDMOS (vertical diffused metal oxide semiconductor) transistors. A VDMOS transistor is a MOSFET that has two or more semiconductor regions formed by diffusion. It has a source region, a drain region, and a gate. The device is vertical in that the source region and the drain region are at opposite surfaces of the semiconductor die. The gate may be a trenched gate structure or a planar gate structure, and is formed at the same surface as the source region. Trenched gate structures are preferred, since trenched gate structures are narrower and occupy less space than planar gate structures. During operation, the current flow from the source region to the drain region in a VDMOS device is substantially perpendicular to the die surfaces. An example of a vertical MOSFET is shown in FIG. 7.

Referring again to FIG. 1, in addition to the die attach pad 5, the leadframe structure 80 also includes a source lead structure 6 with a plurality of source leads 6-1 extending from a perpendicularly oriented source post 6-2. The leadframe structure 80 also includes a gate structure 7 with a gate lead 7-1 also extending from a gate post 7-2. The gate structure 7 and the source structure 6 are separated from each other and from the die attach pad 5.

As used herein, the term “leadframe structure” can refer to a structure that is derived from a lead frame. A typical leadframe structure includes a source lead structure, a gate lead structure, and an optional dummy lead structure. A leadframe structure may include continuous or discontinuous sections of metal. Suitable leadframe structures may be obtained using any suitable process including etching, stamping etc. They may also include a base metal such as copper or aluminum, and may or may not be plated with another material (such as Ni/Pd).

The semiconductor die package in FIG. 1 also includes a flex clip connector 1, which comprises a side tab 1-17. It also comprises a flexible insulator 1-6, die source contact regions 1-1, 1-2, and a lead post source contact region 1-4. The contact regions 1-1, 1-2, and 1-4 may be part of a single conductive trace sandwiched between a first flexible insulating top layer and a discontinuous flexible bottom layer which defines the contact regions 1-1, 1-2, and 1-4. The lead post source contact region 1-4 is electrically and mechanically coupled to the source lead structure 6 using a conductive adhesive 2-4 (e.g., solder or a conductive epoxy), and the die source contact regions 1-1, 1-2 are coupled to source conductive adhesives 2-1, 2-2 on source die contact regions in the die 3. Source current can flow from the source lead structure 6 to the source conductive adhesives 2-1, 2-2 on the die source contact regions via a conductive path that is formed between the lead post source contact region 1-4 and the die source contact regions 1-1, 1-2. The conductive path may comprise a metallic layer that is sandwiched between dielectric layers in the insulator 1-6.

The lead post gate contact region 1-5 in the flex clip connector 1 is coupled to the gate lead structure 7 via a conductive adhesive 2-5. A die gate contact region 1-3 in the flex clip connector 1 is coupled to a gate conductive adhesive 2-3 on a gate die contact region in the die 3. Gate current can flow from the gate lead structure 7 to the gate conductive adhesive 2-3 on the gate region in the semiconductor die 3 via a conductive path that is formed between the lead post gate contact region 1-5 and the gate die contact region 1-3. The conductive path may comprise a metallic layer that is sandwiched between dielectric layers in the insulator 1-6. The lead post gate contact region 1-5 and the gate die contact region 1-3, are electrically isolated from the source contact regions 1-1, 1-2, and 1-4.

A molding material 8 is formed around at least a portion of the leadframe structure 80, and the semiconductor die 3. The molding material 8 may cover the flex clip connector. The molding material 8 protects internal components of the semiconductor die package and may comprise any suitable material including an epoxy material.

FIGS. 2( a) and 2(c) illustrate side views of the semiconductor die package shown in FIG. 2( e) along the line A-A. As shown in FIG. 2( a), the die attach pad 5 is partially etched (e.g., half-etched) so that it is easier to lock the molding material 8 to the die attach pad 5. FIGS. 2( a) and 2(c) additionally show a conductive adhesive 2-4 attached to a source lead structure 6. The close up view in FIG. 2( c) shows a lead post source contact region extending from a conductive trace 1-10 which is partially sandwiched between two dielectric layers forming the insulator 1-6. As shown, the top dielectric layer of the insulator 1-6 is continuous, but the bottom dielectric layer of the insulator is discontinuous.

FIGS. 2( b) and 2(d) illustrate side views of the of the semiconductor die package shown in FIG. 2( e) along the line B-B. The close up view in FIG. 2( d) shows die gate and source contact regions 1-3, 1-2, attached to gate and source regions in the semiconductor die 3 using conductive adhesives 2-3, 2-2.

FIGS. 3( a)-3(f) show side views of various package embodiments that can use a flex clip connector. FIG. 3( a) shows a package with a flat design so that the flex clip connector 1 is flat when it is in the semiconductor die package. FIG. 3( b) shows a dual top-set design. As shown, the die 3 is set lower than corresponding leads 9. The leads 9 also have include external portions 9-1 which extend outside of the molding material 8. FIG. 3( c) shows a dual down-set design where the leads 9 are below the upper surface of the die 3. FIG. 3( d) shows a top-set design for TO type packages. As shown, a lead 9 is on one side of the die 3 and is above the upper surface of the die 3. Another lead is below the upper surface of the die 3 and extends from the die attach pad 5. FIG. 3( e) shows a down-set design where a lead 9 is on one side of the semiconductor die 3 and is down-set with respect to the upper surface of the die 3. FIG. 3( f) shows a down-set design with a flat terminal. As illustrated by FIGS. 3( a)-3(f), the flex clip connector 1 according to embodiments of the invention can be advantageously used in a number of different package configurations (e.g., top-set or down-set designs).

FIGS. 4( a)-4(l) show plan views of various flex clip connectors. In FIGS. 4( a)-4(i), reference number 1-7 refers to a flexible conductive (e.g., copper) trace. The other reference numbers are in these Figures are described above. FIGS. 4( a)-4(i) illustrate that the various contact regions can have any suitable defined shapes, and that the traces that interconnect such contact regions can also have different shapes. FIGS. 4( i)-4(l) illustrate different flex clip connectors with different shapes. Suitable flex clip connectors need not be limited to the rectangular shapes shown in FIGS. 4( a)-4(i), but can have different planar shapes to accommodate different package configurations.

FIG. 5( a) shows a side view of a package according to an embodiment of the invention. FIG. 5( b) shows a top view of the package illustrated in FIG. 5( a). FIG. 5( c) shows another side view of the package illustrated in FIG. 5( a). FIG. 5( d) is a top perspective view of the package illustrated in FIG. 5( a). FIG. 5( e) is a bottom perspective view of the package illustrated in FIG. 5( c). As shown in FIGS. 5( a)-5(e), the flex clip connector 1 may be covered with the molding material. However, the bottom surface of the die attach pad 5 may be exposed through the molding material 8 and an exterior surface of the molding material 8 may be substantially coplanar with the exposed surface of the die attach pad 5. The other components of the package shown in FIGS. 5( a)-5(e) are described above.

Also as shown in FIGS. 5( a)-5(e), the leads 6-1, 7-1 do not extend past the lateral surface of the molding material 8. The semiconductor die package illustrated in FIG. 1 may therefore be characterized as a “leadless” package. A “leaded” package can be one in which the leads of the package extend past the lateral edges of the molding material 8 of the semiconductor die package 100. Embodiments of the invention can include both leaded and leadless packages.

FIGS. 6( a)-6(e) illustrate precursors that are formed in the formation of a semiconductor die package according to an embodiment of the invention. A method for forming a package can be described with reference to FIGS. 6( a)-6(c).

The method includes attaching a semiconductor die 3 having a first surface comprising a die contact region, and a second surface to a leadframe structure 80 comprising a die attach pad and a lead structure.

Before or after the semiconductor die 3 is attached to the leadframe structure 80, the flex clip connector 1 is obtained. The flex clip connector 1 may be obtained (e.g., formed) using any suitable method. In one embodiment, a flexible sheet of dielectric material may be coated with a metal layer using deposition processes known in the art. Suitable metal deposition processes include electroplating, sputtering, blade coating, curtain coating et al. The conductive layer in the flex clip connector 1 may be formed using any suitable material including copper, aluminum, conductive pastes with conductive particles, etc.

After coating a first dielectric layer with a metallic material, an optional second dielectric layer may be patterned on the deposited metal (or conductive) layer. Dielectric patterning methods are well known in the art. Patterning can define exposed metal regions which may form the previously described contact regions.

The first and second dielectric layers may be formed using any suitable dielectric material. Suitable dielectric materials include polyimide, polyamide, etc.

After the flex clip connector 1 is obtained, the flex clip connector 1 is attached to the semiconductor die and the leadframe structure 80. As noted above, the flex clip connector 1 comprises a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector 1 is coupled to the die contact region and wherein the second electrical contact region of the flex clip connector 1 is coupled to the lead structure.

Conductive adhesives may be coated on the die 3, the leadframe structure 80, and/or the contact regions of the flex clip connector 1. After coating one of more of these components with conductive adhesives, they components can be aligned and bonded together as described above.

After bonding the flex clip connector 1 to the die 3 and the leadframe structure 80, a molding material 8 is formed around at least a portion of the flex clip connector 1, the semiconductor die 3, and a part of the leadframe structure 80. A molding tool with molding dies can be used to mold the molding material 8. Suitable molding process conditions are known to those of ordinary skill in the art.

After molding, a sawing/singulation process can be performed (FIG. 6( e)) and then test, and tape & reel processing can be performed (FIG. 6( e)).

As used herein “top” and “bottom” surfaces are used in the context of relativity with respect to a circuit board upon which the semiconductor die packages according to embodiments of the invention are mounted. Such positional terms may or may not refer to absolute positions of such packages.

The semiconductor die packages described above can be used in electrical assemblies including circuit boards with the packages mounted thereon. They may also be used in systems such as phones, computers, etc.

Any recitation of “a”, “an”, and “the” is intended to mean one or more unless specifically indicated to the contrary.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described, it being recognized that various modifications are possible within the scope of the invention claimed.

Moreover, one or more features of one or more embodiments of the invention may be combined with one or more features of other embodiments of the invention without departing from the scope of the invention.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3956821Apr 28, 1975May 18, 1976Fairchild Camera And Instrument CorporationMethod of attaching semiconductor die to package substrates
US4058899Aug 23, 1976Nov 22, 1977Fairchild Camera And Instrument CorporationDevice for forming reference axes on an image sensor array package
US4191943Mar 17, 1978Mar 4, 1980Fairchild Camera And Instrument CorporationFiller-in-plastic light-scattering cover
US4680613Dec 1, 1983Jul 14, 1987Fairchild Semiconductor CorporationLow impedance package for integrated circuit die
US4720396Jun 25, 1986Jan 19, 1988Fairchild Semiconductor CorporationSolder finishing integrated circuit package leads
US4731701May 12, 1987Mar 15, 1988Fairchild Semiconductor CorporationIntegrated circuit package with thermal path layers incorporating staggered thermal vias
US4751199Jan 21, 1987Jun 14, 1988Fairchild Semiconductor CorporationHigh degree of compliance, withstanding mechanical stress by absorption
US4772935Jun 17, 1986Sep 20, 1988Fairchild Semiconductor CorporationDie bonding process
US4791493Aug 19, 1987Dec 13, 1988Canon Kabushiki KaishaImage reading apparatus with illumination timing control
US4796080Nov 3, 1987Jan 3, 1989Fairchild Camera And Instrument CorporationSemiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
US4839717Jun 7, 1988Jun 13, 1989Fairchild Semiconductor CorporationCeramic package for high frequency semiconductor devices
US4890153Apr 4, 1986Dec 26, 1989Fairchild Semiconductor CorporationSingle bonding shelf, multi-row wire-bond finger layout for integrated circuit package
US5327325Feb 8, 1993Jul 5, 1994Fairchild Space And Defense CorporationThree-dimensional integrated circuit package
US5646446Dec 22, 1995Jul 8, 1997Fairchild Space And Defense CorporationThree-dimensional flexible assembly of integrated circuits
US5776797Jul 2, 1997Jul 7, 1998Fairchild Space And Defense CorporationThree-dimensional flexible assembly of integrated circuits
US6133634Aug 5, 1998Oct 17, 2000Fairchild Semiconductor CorporationHigh performance flip chip package
US6329706Aug 23, 2000Dec 11, 2001Fairchild Korea Semiconductor, Ltd.Leadframe using chip pad as heat conducting path and semiconductor package adopting the same
US6424035Nov 5, 1998Jul 23, 2002Fairchild Semiconductor CorporationSemiconductor bilateral switch
US6432750Feb 22, 2001Aug 13, 2002Fairchild Korea Semiconductor Ltd.Power module package having insulator type heat sink attached to rear surface of lead frame and manufacturing method thereof
US6449174Aug 6, 2001Sep 10, 2002Fairchild Semiconductor CorporationCurrent sharing in a multi-phase power supply by phase temperature control
US6465276Jun 12, 2001Oct 15, 2002Siliconx (Taiwan) Ltd.Power semiconductor package and method for making the same
US6489678Mar 15, 1999Dec 3, 2002Fairchild Semiconductor CorporationHigh performance multi-chip flip chip package
US6556750May 25, 2001Apr 29, 2003Fairchild Semiconductor CorporationBi-directional optical coupler
US6566750Sep 3, 1999May 20, 2003Kabushiki Kaisha Toyoda Jidoshokki SeisakushoSemiconductor module
US6574107Feb 26, 2001Jun 3, 2003Fairchild Korea Semiconductor Ltd.Stacked intelligent power module package
US6621152Jul 2, 2001Sep 16, 2003Fairchild Korea Semiconductor Ltd.Thin, small-sized power semiconductor package
US6627991Apr 10, 2000Sep 30, 2003Fairchild Semiconductor CorporationHigh performance multi-chip flip package
US6630726 *Nov 7, 2001Oct 7, 2003Amkor Technology, Inc.Power semiconductor package with strap
US6645791Apr 23, 2001Nov 11, 2003Fairchild SemiconductorSemiconductor die package including carrier with mask
US6674157Nov 2, 2001Jan 6, 2004Fairchild Semiconductor CorporationSemiconductor package comprising vertical power transistor
US6683375Jun 15, 2001Jan 27, 2004Fairchild Semiconductor CorporationSemiconductor die including conductive columns
US6696321Dec 3, 2002Feb 24, 2004Fairchild Semiconductor, CorporationHigh performance multi-chip flip chip package
US6720642Dec 16, 1999Apr 13, 2004Fairchild Semiconductor CorporationFlip chip in leaded molded package and method of manufacture thereof
US6731003Mar 11, 2003May 4, 2004Fairchild Semiconductor CorporationWafer-level coated copper stud bumps
US6740541Sep 4, 2002May 25, 2004Fairchild Semiconductor CorporationUnmolded package for a semiconductor device
US6756689Jan 8, 2003Jun 29, 2004Fairchild Korea Semiconductor, Ltd.Power device having multi-chip package structure
US6774465Oct 4, 2002Aug 10, 2004Fairchild Korea Semiconductor, Ltd.Semiconductor power package module
US6777800Sep 30, 2002Aug 17, 2004Fairchild Semiconductor CorporationSemiconductor die package including drain clip
US6806580Dec 26, 2002Oct 19, 2004Fairchild Semiconductor CorporationMultichip module including substrate with an array of interconnect structures
US6830959Jan 17, 2003Dec 14, 2004Fairchild Semiconductor CorporationSemiconductor die package with semiconductor die having side electrical connection
US6836023Apr 14, 2003Dec 28, 2004Fairchild Semiconductor CorporationStructure of integrated trace of chip package
US6867481Apr 11, 2003Mar 15, 2005Fairchild Semiconductor CorporationLead frame structure with aperture or groove for flip chip in a leaded molded package
US6867489Jan 21, 2003Mar 15, 2005Fairchild Semiconductor CorporationSemiconductor die package processable at the wafer level
US6891256Oct 15, 2002May 10, 2005Fairchild Semiconductor CorporationThin, thermally enhanced flip chip in a leaded molded package
US6891257Mar 30, 2001May 10, 2005Fairchild Semiconductor CorporationPackaging system for die-up connection of a die-down oriented integrated circuit
US6893901May 14, 2001May 17, 2005Fairchild Semiconductor CorporationCarrier with metal bumps for semiconductor die packages
US6943434Oct 2, 2003Sep 13, 2005Fairchild Semiconductor CorporationMethod for maintaining solder thickness in flipchip attach packaging processes
US6989588Sep 24, 2001Jan 24, 2006Fairchild Semiconductor CorporationSemiconductor device including molded wireless exposed drain packaging
US6992384Dec 19, 2003Jan 31, 2006Fairchild Semiconductor CorporationHigh performance multi-chip flip chip package
US7022548Dec 22, 2003Apr 4, 2006Fairchild Semiconductor CorporationMethod for making a semiconductor die package
US7023077Mar 11, 2004Apr 4, 2006Fairchild Semiconductor CorporationCarrier with metal bumps for semiconductor die packages
US7061077Aug 30, 2002Jun 13, 2006Fairchild Semiconductor CorporationSubstrate based unmolded package including lead frame structure and semiconductor die
US7061080Jun 10, 2002Jun 13, 2006Fairchild Korea Semiconductor Ltd.Power module package having improved heat dissipating capability
US7081666Feb 4, 2005Jul 25, 2006Fairchild Semiconductor CorporationLead frame structure with aperture or groove for flip chip in a leaded molded package
US7122884Apr 14, 2003Oct 17, 2006Fairchild Semiconductor CorporationRobust leaded molded packages and methods for forming the same
US7154168Nov 5, 2003Dec 26, 2006Fairchild Semiconductor CorporationFlip chip in leaded molded package and method of manufacture thereof
US7157799Jun 4, 2003Jan 2, 2007Fairchild Semiconductor CorporationSemiconductor die package including carrier with mask and semiconductor die
US7196313Apr 2, 2004Mar 27, 2007Fairchild Semiconductor CorporationSurface mount multi-channel optocoupler
US7199461Jan 21, 2004Apr 3, 2007Fairchild Korea Semiconductor, LtdSemiconductor package suitable for high voltage applications
US7208819Oct 26, 2004Apr 24, 2007Fairchild Korea Semiconductor Ltd.Power module package having improved heat dissipating capability
US7215011Aug 25, 2005May 8, 2007Fairchild Semiconductor CorporationFlip chip in leaded molded package and method of manufacture thereof
US7217594Feb 3, 2004May 15, 2007Fairchild Semiconductor CorporationAlternative flip chip in leaded molded package design and method for manufacture
US7242076May 18, 2004Jul 10, 2007Fairchild Semiconductor CorporationPackaged integrated circuit with MLP leadframe and method of making same
US7256479Jan 13, 2005Aug 14, 2007Fairchild Semiconductor CorporationMethod to manufacture a universal footprint for a package with exposed chip
US7268414Mar 4, 2003Sep 11, 2007Fairchild Korea Semiconductor Ltd.Semiconductor package having solder joint of improved reliability
US7271497Mar 10, 2003Sep 18, 2007Fairchild Semiconductor CorporationDual metal stud bumping for flip chip applications
US7285849Nov 18, 2005Oct 23, 2007Fairchild Semiconductor CorporationSemiconductor die package using leadframe and clip and method of manufacturing
US7315077Nov 12, 2004Jan 1, 2008Fairchild Korea Semiconductor, Ltd.Molded leadless package having a partially exposed lead frame pad
US7332806Jan 31, 2005Feb 19, 2008Fairchild Semiconductor CorporationThin, thermally enhanced molded package with leadframe having protruding region
US20060214222 *May 31, 2006Sep 28, 2006Ashok ChallaPower semiconductor devices and methods of manufacture
US20080048342 *Apr 30, 2007Feb 28, 2008Chuan CheahMulti-chip module
US20080224300 *Mar 27, 2007Sep 18, 2008Ralf OtrembaSemiconductor Module With Semiconductor Chips And Method For Producing It
Non-Patent Citations
Reference
1U.S. Appl. No. 11/626,503, Cruz et al.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7824966Aug 19, 2009Nov 2, 2010Fairchild Semiconductor CorporationFlex chip connector for semiconductor device
US8114712Dec 22, 2010Feb 14, 2012General Electric CompanyMethod for fabricating a semiconductor device package
US8334593Jan 13, 2012Dec 18, 2012General Electric CompanySemiconductor device package
Classifications
U.S. Classification257/666, 257/E23.039
International ClassificationH01L23/495
Cooperative ClassificationH01L2224/32245, H01L23/49562, H01L2924/01046, H01L2924/01013, H01L24/40, H01L23/3107, H01L24/39, H01L23/49524, H01L2924/01005, H01L2924/01019, H01L2924/01006, H01L2924/01082, H01L2924/01033, H01L2924/01029, H01L2924/13091, H01L24/36, H01L2224/73263, H01L2224/40247, H01L2224/37147
European ClassificationH01L24/36, H01L24/39, H01L24/40, H01L23/495C4, H01L23/495G8
Legal Events
DateCodeEventDescription
Jun 3, 2013FPAYFee payment
Year of fee payment: 4
Aug 7, 2009ASAssignment
Owner name: FAIRCHILD SEMICONDUCTOR CORPORATION, MAINE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:QUINONES, MARIA CLEMENS Y.;GOMEZ, JOCEL P.;REEL/FRAME:023070/0825
Effective date: 20080110