US 7627057 B2
The present invention, takes advantage of the properties of quadrature signals to achieve precise quadrature alignment in a simple fashion. The expectation of the product of quadrature signals is zero. A phase error detection network therefore operates by multiplying the received quadrature signals and low-pass filtering the product to produce an error signal. When the signals are in precise quadrature relationship, the error signal will be zero. Real-time feedback control may be used to drive the error to zero. In accordance with another aspect of the invention, a variable phase shift network is achieved using a dual delay line. The difference in delay between the two delay lines is adjusted in response to the error signal to obtain precise quadrature alignment. The principles of the invention may be applied in connection with traditional mixer architectures or with switch-mode architectures.
1. A receiver for receiving a communications signal to produce two output signals in quadrature relation to one another, comprising:
a low-noise amplifier;
a first switching transistor and a second switching transistor being connected to the low-noise amplifier;
a local oscillator;
an adjustable phase shift network having a first delay line and a second delay line, each delay line having its input connected to the local oscillator, the first delay line and the second delay line respectively deriving a first reference signal and a second reference signal having a 90° phase difference therebetween;
means for, using the first and second reference signals, performing frequency downconversion of the communications signal outputted from the low-noise amplifier and outputting the two output signals from the first and second switching transistors; and
a phase error detection network for forming an error signal derived of the product of the two output signals,
wherein said adjustable phase shift network adjusts a relative delay between the first reference signal and the second reference signal using the error signal,
wherein the means for performing frequency downconversion comprises a first drive transistor and a second drive transistor,
wherein an output of the first delay line is coupled to a gate of the first drive transistor via a first inductor, and a drain of the first drive transistor is coupled to a gate of the first switching transistor,
wherein an output of the second delay line is coupled to a gate of the second drive transistor via a second inductor, and a drain of the second drive transistor is coupled to a gate of the second switching transistor,
wherein, each of the drains of the first and second drive transistors is coupled to a first rail voltage which is greater than the threshold voltage of the switching transistor, and each of sources of the drive transistors is coupled to a second rail voltage which is less than the threshold voltage,
wherein, each of the outputs from the first and second delay lines, supplies a sinusoidal signal to the gate of the respective drive transistor causing, an input capacitance of the respective drive transistor to resonate with an inductance, and causing each drive transistor to alternate between two states including one state in which the drive transistor causes the first rail voltage to be applied to its respective switching transistor through a resistor to turn the switching transistor on, and another state in which each drive transistor causes the second rail voltage to be applied to its respective switching transistor to turn the switching transistor off.
2. The receiver of
3. The receiver of
4. The receiver of
This application is a Continuation of U.S. Ser. No. 11/503,186, filed Aug. 14, 2006 now abandoned, which is a Divisional of U.S. Ser. No. 09/865,409, filed May 25, 2001, now U.S. Pat. No. 7,116,728, the entire contents of each of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to communications receivers and more particularly to techniques for generating precise quadrature reference signals for use in the same.
2. State of the Art
Direct conversion receivers are known in the art as exemplified by U.S. Pat. No. 6,061,551, incorporated herein by reference. Such receivers have various advantages over conventional superheterodyne receivers. Regardless of the receiver architecture, however, there is typically a need to generate quadrature reference signals, e.g., a pair of local oscillator (LO) signals phased-shifted by 90°. Both analog and digital techniques have been employed for this purpose. In the case of an analog phase-shift network, because the phase-shift network is narrowband, inaccuracies result at frequencies separated from the nominal design frequency. As data rates and constellation complexity increase, these inaccuracies become a significant impairment. In the case of digital techniques, an input signal is required that is a frequency multiple of the desired LO frequency. This input signal is frequency divided, typically multiple times. Because of the high switching speeds involved, such circuitry tends to be fairly power hungry.
U.S. Pat. No. 4,475,088, incorporated herein by reference, describes an alternative architecture for achieving quadrature alignment, i.e., for generating a pair of quadrature signals having a precise 90.degree. phase offset. As illustrated in
There remains a need for a quadrature alignment technique that is simple in implementation and that achieves precise quadrature alignment.
The present invention, generally speaking, takes advantage of the properties of quadrature signals to achieve precise quadrature alignment in a simple fashion. In particular, the expectation of the product of quadrature signals is zero. In accordance with the teachings of the invention, a phase error detection network therefore operates by multiplying the received quadrature signals and low-pass filtering the product to produce an error signal. When the signals are in precise quadrature relationship, the error signal will be zero. Real-time feedback control may be used to drive the error to zero. In accordance with another aspect of the invention, a variable phase shift network is achieved using a dual delay line. The difference in delay between the two delay lines is adjusted in response to the error signal to obtain precise quadrature alignment. The principles of the invention may be applied in connection with traditional mixer architectures or with switch-mode (e.g., “aliased undersampling”) architectures.
The present invention may be further understood from the following description in conjunction with the appended drawing. In the drawing:
The present invention takes advantage of the recognition that when I and Q output signals are in quadrature they should be orthogonal, implying the following:
Referring now to
Reference signals 202 and 204 for the mixers 203 and 205 are produced using, for example, a dual delay line 216 the delay lines of which exhibit adjustable delays designated as τ1 and τ2, respectively. (An example of such a delay line is described in U.S. Pat. No. 5,306,971, incorporated herein by reference.) A local oscillator signal having a frequency designated as fLO is input to both delay lines of the dual delay line. In the illustrated embodiment, because conventional (e.g., Gilbert cell) mixers are used, fLO=fin.
The desired quadrature relation exists between the reference signals 202 and 204 when the following relationship is satisfied:
Alternatively, the adjustment may be performed in real time. Referring again to
Ideally, when the foregoing equation is satisfied, the error signal will be zero. Note however that, depending on the characteristics of other components in the system, the reference signals may have a phase offset different than 90° in order to obtain precise quadrature alignment of the received signals. This property, that the system is forgiving of potential forward-path impairments, results in increased robustness.
A particularly advantageous arrangement is obtained when the foregoing quadrature alignment technique is applied to a switch-mode receiver architecture as illustrated in
More particularly, because switching mixers are passive, 1/f noise is reduced, and depending on the switch drive waveform, an exceedingly high third-order input intercept point can be achieved. With no LO on-channel leakage, there is also avoided on-channel mixing with such leakage signals among themselves, which in conventional direct-conversion receiver architectures leads to DC offset shifts. Mixer conversion loss may be improved by varying the duty cycle of the switch drive signal.
Blocking tolerance come primarily from the high input second and third order input intercept points of the switching mixer. Further tolerance is gained by having the LO at a very different frequency from that of the signal and nearby blocking signals—as is the case with subharmonic operation. Subharmonic operation avoids the complexity of other methods used to generate on-frequency LO signals from off-frequency oscillators. Voltage controlled oscillator (VCO) pulling by input signal magnitude variations is also eliminated by the same techniques.
Advantageous switch drive circuits are shown in
Because the drive transistor QD is much smaller than the switching transistor QSW, the input capacitance Cgs1 of the drive transistor QD can be resonated using a series inductor of practical size. (If, on the other hand, the switching transistor were to be resonated directly, the required inductor would be of such small size as to not be practically realizable.) Furthermore, the input-to-output parasitic coupling capacitance Cgd1 of the drive transistor QD is sufficiently small that overdriving the drive transistor QD (using a sine wave) is not a concern.
In operation, as the input of the drive transistor QD is resonated, during the positive half-cycle, the drive transistor QD is turned on, causing the voltage VSS to be applied to the gate of the switching transistor QSW, abruptly turning it OFF. During the negative half-cycle, the drive transistor QD is turned off, causing the voltage VG to be applied through the resistor RL to the gate of the switching transistor QSW. The gate voltage rises in accordance with the time constant τ=RLCgs2, which governs the fall time of the switching transistor QSW, causing the switching transistor QSW to turn ON.
In the case of both circuits, the voltage VG used to turn on the switching transistor QSW can be controlled to control drive strength and attendant leakage.
Hence, the foregoing direct drive structure uses a very simple circuit implementation to achieve, simultaneously: minimum rise and fall switching times; minimum drive amplitude and low drive power (improved efficiency) for a desired switch current capability; reduced AM/PM distortion (due to lower feedthrough) and AM/AM distortion (by assuring more “rectangular” signals); and avoidance of gate-source diode forward biasing in MESFETs.
Alternatively, switch drive circuits may be used such as those described in U.S. Pat. No. 6,198,347, incorporated herein by reference.
Although the invention has been described in relation to direct downconversion receiver architectures, the same principles may be applied in conventional heterodyne or superheterodyne architectures.
Thus, there has been described a quadrature alignment technique for use in communications receivers that is simple in implementation and that achieves precise quadrature alignment. The alignment technique is particularly suitable for direct conversion receiver architectures including switch-mode receiver architectures. The quadrature alignment technique may be used in conjunction with a direct drive structure for power switching transistors to achieve improved efficiency and low distortion.
It will be appreciated by those of ordinary skill in the art that the invention can be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes which come within the meaning and range of equivalents thereof are intended to be embraced therein.