|Publication number||US7644296 B1|
|Application number||US 11/488,429|
|Publication date||Jan 5, 2010|
|Filing date||Jul 17, 2006|
|Priority date||Apr 7, 2006|
|Publication number||11488429, 488429, US 7644296 B1, US 7644296B1, US-B1-7644296, US7644296 B1, US7644296B1|
|Original Assignee||Altera Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Non-Patent Citations (5), Referenced by (8), Classifications (16), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit of provisional patent application No. 60/790,067, filed Apr. 7, 2006, which is hereby incorporated by reference herein in its entirety.
This invention relates to integrated circuits such as programmable logic device integrated circuits, and more particularly, to integrated circuits with configurable dynamic phase alignment circuitry.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the tools generate configuration data. The configuration data is loaded into a programmable logic device to configure the device to perform the functions of the custom logic circuit.
In a typical system, a programmable logic device integrated circuit and other integrated circuits are mounted on a circuit board. The circuit board contains conductive paths that interconnect the integrated circuits. A system may also have paths that interconnect integrated circuits on different boards. Programmable logic devices contain transceiver circuitry for transmitting and receiving data over these communications paths.
Programmable logic device transceiver circuitry includes input and output drivers. The input and output drivers may use differential signaling schemes in which a pair of signals are referenced to each other or single-ended signaling schemes, in which signals are referenced to ground. In high-speed environments, the input and output drivers are generally differential drivers and handle differential signals.
Some programmable logic device architectures rely extensively on complex hardwired transceiver circuitry. For example, programmable logic devices are available that include transceivers with dynamic phase alignment capabilities. These devices use multiphase clocks. Hardwired dynamic phase alignment circuitry is used to select an optimal clock phase for data capture operations.
While hardwired programmable logic device transceivers with dynamic phase alignment capabilities are appropriate for some logic designs, the inclusion of complex transceiver circuitry of this type is not always desired and can add needless overhead. As a result, other programmable logic device architectures forgo complex transceiver circuitry and only support limited transceiver functionality. Devices of this more limited type have transceivers without dynamic phase alignment capabilities. Although these devices use less hardwired circuitry to capture incoming data, the benefits of dynamic phase alignment are lost.
It would therefore be desirable to be able to provide an integrated circuit such as a programmable logic device integrated circuit with configurable dynamic phase alignment circuitry.
In accordance with the present invention, programmable logic device integrated circuits are provided that have user-configurable receivers with dynamic phase alignment circuitry. In designs in which dynamic phase alignment capabilities are needed, logic elements can be configured to perform dynamic phase alignment data capture and resynchronization functions. In designs in which dynamic phase alignment capabilities are not needed, resources are made available for implementing other user logic functions.
One or more phase-locked-loop circuits may be used to generate an eight-phase dynamic phase alignment clock signal. A configurable dynamic phase alignment clock distribution architecture is used to distribute the dynamic phase alignment clock signal to dynamic phase alignment circuits in multiple receivers.
Data capture registers are used to capture incoming data. Dynamic phase alignment control circuitry systematically makes measurements during data capture operations while adjusting a clock signal selection multiplexer that selects a given one of the multiple phases of the dynamic phase alignment clock signal. After capturing data using all of the available phases of the dynamic phase alignment clock signal, the dynamic phase alignment control circuitry identifies an optimal phase of the dynamic phase alignment clock to use in capturing data during normal device operation. The dynamic phase alignment control circuit then adjusts the clock selection multiplexer to ensure that normal data capture operations are performed using the optimal clock phase.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
The present invention relates to integrated circuits containing transceivers with configurable dynamic phase alignment circuitry. The dynamic phase alignment circuitry is formed at least partly from programmable logic. The programmable logic is programmed to perform desired dynamic phase alignment functions using configuration data. With one suitable arrangement, the dynamic phase alignment circuitry is implemented by loading configuration data into volatile memory elements such as random-access-memory (RAM) cells in the integrated circuit.
The integrated circuits used with the present invention may be programmable logic device integrated circuits or programmable integrated circuits that contain programmable circuitry but that are not typically referred to as programmable logic devices. For example, the invention may be used with digital signal processing circuits containing programmable circuitry, microprocessors containing programmable circuitry, application specific integrated circuits containing programmable circuitry, or any other suitable integrated circuit. The present invention will generally be described in the context of programmable logic device integrated circuits as an example.
An illustrative programmable logic device 10 in accordance with the present invention is shown in
Programmable logic devices contain programmable elements 20. Some programmable logic devices are programmed by configuring their programmable elements 20 using mask programming arrangements. A mask-programmed device is configured during semiconductor manufacturing. Other programmable logic devices are configured after semiconductor fabrication operations have been completed (e.g., using electrical programming or laser programming to program their programmable elements). In general, programmable elements 20 may be based on any suitable programmable technology, such as fuses, antifuses, electrically-programmable read-only-memory technology, random-access memory cells, mask-programmed elements, etc.
Many programmable logic devices are electrically programmed. With electrical programming arrangements, the programmable elements 20 may be formed from memory cells. During programming, configuration data is loaded into the memory cells using pins 14 and input/output circuitry 12. Memory cells are typically formed from random-access-memory (RAM) cells. Because the RAM cells are loaded with configuration data, they are sometimes referred to as configuration RAM cells (CRAM).
Programmable elements 20 each provide a corresponding static control output signal that controls the state of an associated logic component in programmable logic 18. The output signals are typically applied to the gates of metal-oxide-semiconductor (MOS) transistors.
The circuitry of device 10 may be organized using any suitable architecture. As an example, the logic of programmable logic device 10 may be organized in a series of rows and columns of larger programmable logic regions 22 each of which contains multiple smaller logic regions 24 as shown in
In some logic devices 10, the larger portions of logic such as logic region 22 may be referred to as “logic array blocks” (LABs) and the smaller portions of logic such as logic regions 24 may be referred to as logic elements (LEs). This is merely one illustrative logic device arrangement 10. For clarity, the present invention will sometimes be described in terms of “logic elements” 24. In general, however, the logic of device 10 may be provided using any suitable programmable logic device architecture.
An illustrative system environment for a programmable logic device 10 is shown in
System 38 may include processing circuits 44, storage 46, and other system components 48 that communicate with device 10. The components of system 38 may be located on one or more boards such as board 36 or other suitable mounting structures or housings. As shown in the example of
Configuration device 40 may be supplied with the configuration data for device 10 over a path such as path 52. Configuration device 40 may, for example, receive the configuration data from configuration data loading equipment 54 or other suitable equipment that stores this data in configuration device 40. Device 40 may be loaded with data before or after installation on board 36.
It can be a significant undertaking to design and implement a desired logic circuit in a programmable logic device. Logic designers therefore generally use logic design systems based on computer-aided-design (CAD) tools to assist them in designing circuits. A logic design system can help a logic designer design and test complex circuits for a system. When a design is complete, the logic design system may be used to generate configuration data for electrically programming the appropriate programmable logic device.
As shown in
In a typical scenario, logic design system 56 is used by a logic designer to create a custom circuit design. The system 56 produces corresponding configuration data which is provided to configuration device 40. Upon power-up, configuration device 40 and data loading circuitry on programmable logic device 10 is used to load the configuration data into the CRAM cells 20 of device 10. Device 10 may then be used in normal operation of system 38.
During normal operation, data sources such as integrated circuit data sources transmit data to programmable logic device 10 over communications links. An illustrative system 38 in which a transmitter 60 is transmitting data to a programmable logic device 10 is shown in
Transmitter 60 transmits a reference clock signal REF CLK to programmable logic device 10 over reference clock path 76. Corresponding data lines 74 are used to convey data signals such as data signals D1 and D2. Paths such as paths 74 and 76 may be differential paths that contain a pair of conducing lines carrying differential signals. There may be any suitable number of transmitters, data lines, and clocks in a system. The example of
Programmable logic device 10 contains transceiver circuitry 62. Transceiver circuitry 62 contains transmitters for transmitting data to other integrated circuits. Transceiver circuitry 62 also contains receiver circuitry such as receivers 66. Each receiver receives data from a different data path. For example, one receiver 66 receives data signal D1 and another receiver 66 receives data signal D2. The received data is processed by receivers 66 and is provided to logic 64 on parallel data paths 84. Logic 64 may include hardwired logic and user-configured programmable logic.
Phase-locked-loop circuit 68 is used to capture the reference clock. Phase-locked-loop circuit 68 produces a corresponding rate-matched system clock on path 70 (SYS CLK). The system clock in a typical application may have a frequency of about 400 MHz. Phase-locked-loop circuit 68 also produces a parallel clock signals PARALLEL CLOCK on line 72. The signal PARALLEL CLOCK has a slower frequency than the signal SERIAL CLOCK and is suitable for processing the data that has been received from transmitter 60 after serial-to-parallel conversion. In a typical arrangement, the serial data that is transmitted on a communications path 74 has a data rate that is 8-10 times that of the parallel data rate for the same data following serial-to-parallel conversion.
The transceiver circuitry 62 is able to accurately capture data from high-speed data streams transmitted over data paths 74 using a dynamic phase alignment scheme. With dynamic phase alignment techniques, the clock signal that is used to capture incoming data is split into multiple phases. Dynamic phase alignment circuitry in the transceiver circuitry 62 is used to determine which of the multiple clock phases produces the best results when used to capture incoming data.
To support dynamic phase alignment operations, phase-locked-loop circuit 68 produces a multiphase clock signal on path 82. The multiphase clock signal is based on the received reference clock 76. Because the multiphase clock signal is used by dynamic phase alignment circuitry on programmable logic device 10, the multiphase clock signal is sometimes referred to as a dynamic phase alignment (DPA) clock. In general, any suitable number of phases may be used in the DPA clock. For example, the DPA clock may have eight phases (DPA0, DPA1, . . . DPA7). If desired, the DPA clock may have fewer phase or more phases. Schemes with fewer clock phases are less accurate, but are less difficult to implement. Schemes with more clock phases require additional circuitry and tighter tolerances, but provide more accuracy.
As shown in
There may be any suitable number of phase-locked-loop circuits 68 and receivers 66 on a programmable logic device integrated circuit. A typical device architecture is shown in
By configuring switches 86, a user can select which dynamic phase alignment clock signals are driven onto paths 82. For example, if one phase-locked-loop circuit 68 is used to generate the dynamic phase alignment clock signal, the switches 86 can be configured so that this single multiphase dynamic phase alignment clock signal is routed to the dynamic phase alignment clock distribution paths 82 on all four edges of programmable logic device integrated circuit 10. If, as another example, two phase-locked-loop circuits 68 are used to generate dynamic phase alignment clock signals, the switches 86 can be used to route the dynamic phase alignment clock signals from one circuit 68 to the topmost and right-hand paths 82 and to route the dynamic phase alignment clock signals from the other circuit 68 to the lowermost and left-hand paths 82. These are merely illustrative examples. In general, the switches 86 can be configured to route the dynamic phase alignment clock signals on paths 82 in any suitable arrangement.
The dynamic phase alignment clock signals from a single phase-locked-loop circuit 68 are typically distributed to multiple receivers 66, so phase-locked-loop circuitry 68 need not be needlessly duplicated on circuit 10. There may be any suitable number of receivers 66 in a given programmable logic device integrated circuit 10. As an example, each of the four sides of the programmable logic device integrated circuit 10 may have from 20-30 separate receivers 66 each of which receives serial data signals from a corresponding data path 74 (
Illustrative phase-locked-loop circuitry and receiver circuitry 88 is shown in
Dynamic phase alignment clock selection multiplexer M3 receives the eight-phase dynamic phase alignment clock signals on the eight corresponding lines of path 82. Multiplexer M3 connects one of its eight inputs to its output. The setting of multiplexer M3 is controlled by a multibit control signal received from dynamic phase alignment control circuit 102 over path 100.
During training (set up) operations, the dynamic phase alignment control circuit 102 varies the setting of multiplexer M3, so that different selected phases of the dynamic phase alignment clock signal are presented at the output of multiplexer M3. The dynamic phase alignment control circuit 102 evaluates the success of data capture operations for each setting. After identifying an optimal one of the eight phases of the dynamic phase alignment clock signal, dynamic phase alignment control circuit 102 adjusts the multiplexer M3 so that the optimal phase of the dynamic phase alignment clock is provided at the output 136 of the multiplexer. The device 10 may then be operated normally. The optimal phase is sometimes referred to as the recovered clock signal REC CLK.
Circuit 66 receives incoming data from a corresponding communications path 74. Differential-to-single-ended buffer 112 generates a corresponding single-ended data signal DATA on path 114. Incoming data is typically encoded using a double-date-rate scheme. During processing by circuitry 66, the incoming double-data-rate signal DATA is converted into two corresponding data streams DATA1 and DATA2 on lines 104 and 106. The signals DATA1 and DATA2 are provided to logic 64 (
The data signal DATA on path 114 is processed using registers 108 and 110 (labeled R1, R2, R3, R4, R5, and R6) and multiplexers 98 (labeled M1 and M2). Registers 108 have non-inverting clock inputs and capture data on rising clock edges. Registers 110 have inverting clock inputs and capture data on falling clock edges. Multiplexers 98 are used to selectively bypass register R3 and R4.
Registers R1 and R2 are data capture registers. Data capture registers R1 and R2 are clocked by the selected phase of the dynamic phase alignment clock signal at the output of multiplexer M3. During each rising clock edge, a bit of the data signal DATA on line 114 is captured by register R1. During each falling clock edge, a bit of the data signal DATA on line 114 is captured in register R2.
Registers R3, R4, R5, and R6 and multiplexers M1 and M2 serve as resynchronization circuitry that converts the data flowing through registers R1 and R2 from the REC CLK clock domain to the SYS CLK clock domain. The recovered clock REC CLK is used to capture the incoming data stream DATA into registers R1 and R2. Registers R3, R4, R5, and R6 and multiplexers M1 and M2 ensure that the captured data can be used by logic 64. Logic 64 uses clock signals SYS CLK (prior to deserialization) and PARALLEL CLOCK (following deserialization). Signals SYS CLK and PARALLEL CLOCK are phase-aligned with each other, but are not phase aligned with the recovered clock signal REC CLK. Accordingly, the resynchronization circuitry formed from registers R3, R4, R5, and R6 and multiplexers M1 and M2 is used to convert between clock domains.
Double-data-rate (DDR) data can be captured using a full-rate clock scheme or a half-rate clock scheme. A user of programmable logic device 10 can configure circuitry 88 to perform full-rate capture operations or half-rate capture operations as desired.
A timing diagram showing data and clock signals in a full-rate clock scheme is shown in
During training, a training sequence is transmitted to programmable logic device integrated circuit 10 from the transmitter 60. A typical training sequence is composed of alternating ones and zeros, as shown in the example of
The dynamic phase alignment control circuit 102 controls multiplexers M1 and M2 via control paths 116. The multiplexers M1 and M2 can be operated with either their “A” inputs or their “B” inputs connected to their outputs. With one suitable arrangement, testing starts with the “B” inputs of multiplexers M1 and M2 connected to their outputs. When it is determined that the rising edge of the currently selected dynamic phase alignment clock phase falls within a predetermined range of the rising edge of the system clock SYS CLK, the dynamic phase alignment control circuit 102 issues multiplexer control signals on path 116 to switch the “A” inputs of multiplexers M1 and M2 to their outputs. This ensures that the registers of circuitry 66 will have sufficient timing margins to operate properly.
Consider, as an example, the potential capture of the signal DATA at time t6. Multiplexer M3 is adjusted so that the dynamic phase alignment signal DPA6 is routed to the clock input of register R1. At time t6, the leading edge of signal DPA6 goes high. As shown in the third-to-last trace in
If the “B” input of multiplexer M1 is connected to its output, resynchronization register R3 is bypassed and the data signal Q at the output of register R1 is captured by register R5. Register R5 has a noninverting clock input, so register R5 captures data at its input on the rising edge of the system clock signal SYS CLK, as shown in the second-to-last trace of
If, however, the “A” input of multiplexer M1 is connected to its output, resynchronization register R3 is switched into use by dynamic phase alignment control circuit 102. In this situation, the data signal Q at the output of register R1 is captured by register R3. Register R3 has an inverted clock input, so register R3 captures data on the falling edge of system clock signal SYS CLK, as shown in the last trace of
As this example demonstrates, the two different resynchronization registers R3 and R5 exhibit significantly different timing margins. When R5 is switched into use, there is a time T1 of only two eighths of a clock cycle (i.e., T1=t8−t6) between when the data captured in R1 becomes valid and the rising edge of the SYS CLK signal that triggers R5. When R3 is switched into use, there is a time T2 of six eighths of a clock cycle (i.e., T2=t12−t6) between the time at which the output of R1 becomes valid and the time at which the signal at the input of R3 is captured. The data that is captured by register R1 at time t6 will therefore be resynchronized most reliably if resynchronization register R3 is used.
Dynamic phase alignment circuit 102 adjusts the multiplexer M1 to ensure a sufficient setup time for the resynchronization register. Any suitable criteria may be used to determine when to switch the multiplexer M1. With one suitable approach, the multiplexer M1 is switched whenever necessary to avoid a setup time less than two eighths of a clock cycle or any other suitable predetermined threshold value. In the present example, the separation T1 between the rising edge of the selected dynamic phase alignment clock phase DPA6 and the rising edge of SYS CLK would be two-eighths of a clock cycle if register R5 were to be used. Because this value is too small, the dynamic phase alignment circuit 102 adjusts multiplexer M1 to connect its “A” input to its output. This switches resynchronization register R3 into use and ensures sufficient time (T2) for resynchronization register R3 to capture the data from data capture register R1.
Although this example involved the use of registers R1, R3, and R5 and multiplexer M1, the same timing margin concerns apply to registers R2, R4, and R6 and multiplexer M2. Dynamic phase alignment control circuit 102 switches both multiplexer M1 and multiplexer M2 as needed to ensure that the resynchronization registers have sufficient margin to operate satisfactorily.
Illustrative steps involved in using the circuitry 88 of
At step 118, dynamic phase alignment control circuit 102 performs initialization operations. Dynamic phase alignment control circuit 102 implements a control state machine. The circuitry of dynamic phase alignment control circuit 102 is preferably implemented using programmable logic 18 (
At step 120, the dynamic phase alignment control circuit 102 adjusts the dynamic phase alignment clock phase selection multiplexer M3 so that the chosen phase of the clock is passed to line 136. For example, if the current value of CHOSEN DPA CLOCK PHASE is DPA4, dynamic phase alignment control circuit 102 adjusts multiplexer M3 so that the signal DPA4 is routed to line 136. The dynamic phase alignment control circuit 102 also adjusts the multiplexers M1 and M2 according to the value of CHOSEN INPUTS. For example, if the value of CHOSEN INPUTS is “B,” the dynamic phase alignment control circuit 102 adjusts multiplexers M1 and M2 so that their “B,” inputs are connected to their respective outputs. After the adjustments of step 120, either a first set of resynchronization registers (R3, R4, R5, and R6) is switched into use or a second set of resynchronization registers (R5 and R6) is switched into use.
At step 122, the data signal DATA on line 114 is captured using capture registers R1 and R2. During step 122, the DATA signal transmitted from transmitter 60 is a training pattern (e.g., alternating ones and zeros). Register R1 has a noninverting clock input, so register R1 captures the signal DATA on the rising edges of the chosen dynamic phase alignment clock. Register R3 has an inverting clock input, so register R3 captures the signal DATA on the falling edges of the chosen dynamic phase alignment clock. As data is captured with the data capture registers, the resynchronization registers perform clock domain conversion. During clock domain conversion, the set of resynchronization registers that has been switched into use is used to change the clock domain of the captured data from the CHOSEN DPA CLOCK PHASE domain to the SYS CLK domain. The resulting captured output data is provided on lines 104 and 106 as data signals DATA1 and DATA2.
Dynamic phase alignment control circuit 102 monitors the captured data corresponding to the currently active dynamic phase alignment clock phase and stores these signals for processing at step 124. In the present example, the dynamic phase alignment control circuitry 102 monitors the DATA1 signal on line 104 and stores this data. Any suitable arrangement may be used to store the captured data signals. With one suitable approach, the captured signals may be stored in volatile memory on programmable logic device integrated circuit 10 in the form of a capture table of the type shown in
As shown in
At step 126, if a complete set of eight phase measurements has not yet been made, the value of CHOSEN DPA CLOCK PHASE is updated. The value of CHOSEN DPA CLOCK PHASE is incremented if CHOSEN DPA CLOCK PHASE is less than DPA7. If the value of CHOSEN DPA CLOCK PHASE is DPA7, updating is performed by setting CHOSEN DPA CLOCK PHASE to DPA0 (i.e., by looping back from the last row to the first row of the capture table).
At step 128, the value of CHOSEN INPUTS is updated if necessary to ensure proper timing margins are maintained in the resynchronization registers. As described in connection with
After measurements have been made using all eight dynamic phase alignment clock phases, the dynamic phase alignment control circuitry 102 analyzes the results stored in the data capture table (step 132).
The captured data signals in the capture table reveal the time positions of the DATA signal edges. If a given value of CHOSEN DPA CLOCK PHASE produces clean captured data, the dynamic phase alignment control circuit 102 can conclude that the given value of CHOSEN DPA CLOCK PHASE is not at a DATA signal edge. Captured data that is not clean indicates the presence of an edge.
For example, consider the data of the capture table 138 of
The proximity of the edge of DPA6 to the edge of DATA is illustrated in
During the analysis of step 132, the dynamic phase alignment control circuit 102 determines which clock phases resulted in clean measurements and which clock phases resulted in noisy measurements. Because noisy measurement correspond to data edges, the dynamic phase alignment control circuit 102 can determine the optimal clock phase for capturing data by identifying the midpoint between the data edges. In the example of
If desired, the dynamic phase alignment control circuit 102 can take into account the amount of noise measured for each clock phase. For example, a measurement of one zero and nine ones is less noisy (and therefore farther from the data edge) than a measurement of five zeros and five ones. Using information on the amount of noise in the captured data for each phase, the dynamic phase alignment control circuit 102 can identify the optimal dynamic phase alignment clock phase with enhanced accuracy.
After the optimal dynamic phase alignment clock phase has been identified at step 132, the dynamic phase alignment control circuit 102 adjusts multiplexer M3 so that the optimal dynamic phase alignment clock phase (DPA3 in this example) is provided to line 136 as the recovered clock signal REC CLK. The programmable logic device integrated circuit 10 may then receive transmitted data normally using the circuitry of
If desired, the dynamic phase alignment circuitry of
As shown in the illustrative data capture table 140 of
The circuitry of
Components in circuitry 88 that are preferably implemented using hardwired circuitry include phase-locked-loop 68, differential-to-single-ended input buffers 112 and 90, and multiplexer M3. The use of hardwired circuitry to implement these components helps to minimize the amount of on-chip real estate and programmable resources that are consumed in implementing the dynamic phase alignment logic and helps to ensure that desired levels of timing performance are obtained.
Components of circuitry 88 that are preferably implemented using programmable logic include the data capture registers R1 and R2, resynchronization registers R3, R4, R5, and R6, multiplexers M1 and M2, and dynamic phase alignment control circuitry 102. Dynamic phase alignment control circuitry 102 may be implemented from general purpose programmable logic resources such as a group of tens or hundreds of logic elements 24 (
An illustrative logic element 24 is shown in
The table of
The second column of table 158 indicates which circuit resource in
The third column of
The fourth column of table 158 indicates how multiplexer ML1 is configured for each logic element (i.e., whether the setting for ML1 directs its “1” input or its “0” input to be connected to its output). For example, in the third row of the fourth column of table 158, the entry “1” indicates that multiplexer ML1 is configured to connect its “1” input to its output in logic element LE3, so that the signals from look-up table 142 are routed to register 146.
The fifth column of table 158 indicates, for each logic element, whether register 146 is used. The entries in the fifth column also indicate which component is implemented using the register 146. For example, the third row of the fifth column of table 158 contains the entry “Y(R5)”, indicating that the register R5 in
The sixth column of table 158 shows how the multiplexer ML2 is always configured so that its “0” input is connected to logic element output 156.
Using the illustrative six-logic-element circuit implementation of table 158, the dynamic phase alignment receiver circuitry 66 of
A circuit diagram showing how multiplexer M3 and register R1 can be implemented using the resources of three programmable logic elements 24 is shown in
Illustrative steps involved in setting up and using a programmable logic device integrated circuit 10 containing receivers with dynamic phase alignment circuitry are shown in
At step 176, a user provides a desired custom logic design to computer-aided design tools on logic design system 56 (
With one suitable arrangement, each dynamic phase alignment circuit that is formed can be implemented using a hardwired multiplexer M3 and six corresponding user-configured logic elements 24. Switches 86 can be used to distribute dynamic phase alignment clock signals over multiple edges of the device.
At step 178, the logic design system 56 processes the user's desired logic design and produces corresponding configuration data.
At step 180, the configuration data is loaded into the programmable elements 20 of the programmable logic device integrated circuit 10, thereby configuring the programmable logic device integrated circuit to perform the functions of the desired logic design.
At step 182, as training data is being transmitted from transmitter 60 (
After the optimal clock phase has been identified at step 182, the dynamic phase alignment control circuit 102 adjusts multiplexer M3 to route this phase of the clock signal to the output line 136 as the recovered clock signal REC CLK (step 184). During step 184, the recovered clock signal REC CLK is used to capture data. The programmable logic device 10 operates normally and data that has been captured and synchronized (e.g., DATA1 and DATA2) is processed by logic 64 (
The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.
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|U.S. Classification||713/401, 713/503, 713/501|
|International Classification||G06F1/06, G06F1/04|
|Cooperative Classification||H03L7/0814, H04J3/047, H04L7/0008, H03M9/00, H03L7/087, H04L7/0337|
|European Classification||H04L7/033E, H03L7/081A1, H03L7/087, H04J3/04D, H03M9/00|
|Jul 17, 2006||AS||Assignment|
Owner name: ALTERA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BURNEY, ALI;REEL/FRAME:018071/0151
Effective date: 20060629
|Dec 21, 2010||CC||Certificate of correction|
|Mar 18, 2013||FPAY||Fee payment|
Year of fee payment: 4