|Publication number||US7648880 B2|
|Application number||US 12/142,394|
|Publication date||Jan 19, 2010|
|Filing date||Jun 19, 2008|
|Priority date||Dec 23, 2002|
|Also published as||CN1294657C, CN1531103A, US7078773, US7442612, US20040119115, US20060252241, US20080286930|
|Publication number||12142394, 142394, US 7648880 B2, US 7648880B2, US-B2-7648880, US7648880 B2, US7648880B2|
|Inventors||Kevin K. Chan, Hussein I. Hanafi, Paul M. Solomon|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (3), Classifications (11), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of U.S. application Ser. No. 11/481,532, filed Jul. 6, 2006, which is a divisional of U.S. application Ser. No. 10/328,258, filed Dec. 23, 2002, now U.S. Pat. No. 7,078,773, issued on Jul. 18, 2006.
The present invention relates to double-gate field effect transistors (DGFETs), and in particular to DGFETs that include self-aligned isolation regions. The present invention is also directed to a method of fabricating DGFETs having the aforementioned features using nitride or another like protective material to encapsulate the Si-containing channel during formation of the self-aligned isolation regions.
In order to make integrated circuits (ICs) such as memory, logic and other devices, of higher integration density than currently feasible, one has to find a means to further scale down the FET devices that are present therein. Moreover, as FET dimensions are scaled down, it becomes increasingly difficult to control short-channel effects by conventional means. Short-channel effects, as well known to those skilled in the art, are the decrease in threshold voltage, Vt, in short-channel devices, i.e., sub-0.1 micron, due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.
An evolution beyond the standard single gate metal oxide semiconductor field effect transistor (MOSFET) is the double-gate MOSFET, where the device channel is confined between top and bottom gate dielectric layers. This structure, with a symmetrical gate structure, can be scaled to about half of the channel length as compared to a conventional single gate MOSFET structure. It is well known that a dual gate or double-gate MOSFET device has several advantages over conventional single gate MOSFET devices. Specifically, the advantages for dual gate MOSFET devices over their single gate counterparts include: a higher transconductance, lower parasitic capacitance, and improved short-channel effects. For instance, Monte-Carlo simulation has been previously carried out on a 30 nm channel dual gate MOSFET device and has shown that the dual gate device has a very high transconductance (2300 mS/mm) and fast switching speeds (1.1 ps for nMOSFET).
Moreover, improved short-channel characteristics are obtained down to 20 nm channel length with no doping needed in the channel region. This circumvents the tunneling breakdown, dopant quantization, and dopant depletion problems associated with channel doping that are normally present with single gate MOSFET devices.
Some examples of prior art double-gate MOSFETs are found in the following references:
U.S. Pat. No. 5,188,973 describes a double-gate structure in which the bottom gate is not self-aligned to the top gate. This prior art double-gate structure is quite different from the inventive double-gate structure described herein because the inventive DGFET includes self-aligned isolation oxide regions that are formed while the Si channel region is encapsulated with nitride. No such self-aligned oxide isolation regions and encapsulation is disclosed in the '973 patent.
U.S. Pat. Nos. 5,140,391 and 5,349,228 describe other types of double-gate structures. In these prior art double-gate structures, the Si channel region is not encapsulated with nitride during formation of oxide isolation regions. Moreover, these prior art structures do not include self-aligned oxide isolation regions.
To date, prior art methods for fabricating double-gate MOSFETs have either been very complex or have severe drawbacks in terms of parameter control. Moreover, some of the structures known in the art have large parasitic capacitance between the back-gate and the source/drain regions. This can be reduced by increasing the back-gate dielectric thickness, but with the penalty of reduction of back-gate control, and poorer scaling properties. When low capacitance is desired, the back-gate dielectric should be approximately 20× thicker than the front gate dielectric, but when greater effective control is desired, the back-gate dielectric should be approximately 2-4× thicker than the front gate.
Co-assigned U.S. Pat. No. 5,773,331 describes a structure and method for fabricating a double-gate MOSFET structure in which the above problems have been solved. In particular, the '331 patent describes a double-gate MOSFET having sidewall source and drain contacts and bottom and top gate oxides that are self-aligned. The structure disclosed in the '331 patent has low parasitic capacitance to the bottom gate and a reduced drain and source resistance as compared to other prior art double-gate MOSFETs.
In the '331 patent, the double-gate MOSFET having the above-mentioned characteristics is obtained by the steps of: forming a channel layer; forming a top gate insulator layer on the channel layer; forming a top gate on the top gate insulator; forming a gate pillar on the top gate; forming insulating sidewall layers adjacent to the top gate and the gate pillar; forming an integral source/drain region within the channel layer by introduction of dopants; forming conductive amorphous sidewalls on either side of, and adjacent to the insulating sidewall layers, one of the amorphous silicon sidewalls being connected to the drain region and the other being connected to the source region; and etching the channel layer using the top gate, gate pillar, insulating sidewall layers and amorphous silicon sidewalls as a mask, thereby transferring the lateral extension of the mask into the channel layer, providing for a channel with integral source/drain regions being raised with respect to the support structure.
Despite being capable of providing self-aligned top and bottom gates, the prior art double-gate MOSFET disclosed in the '331 patent does not provide self-aligned oxide isolation regions and complete nitride encapsulation of the Si channel region. As such, the '331 patent does not provide a DGFET which has its lowest possible parasitic capacitance.
The present invention provides a DGFET and method for forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the Si-containing channel to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further. The term “Si-containing” is used throughout the specification to indicate a semiconducting material that includes Si. Illustrative examples of such Si-containing materials include Si, SiGe, SiC, SiGeC and other like Si-containing semiconductors.
It has been determined by the applicants of the present invention that protecting the sidewalls of the Si-containing region with a nitride or another like protective material eliminates the problem of sidewall oxidation of the channel, which typically occurs in the absence of encapsulation. In addition, it has been determined that the nitride layer under the back-gate dielectric blocks oxidation of the Si-containing channel from the bottom. Following oxidation and formation of the self-aligned isolation regions, the protective material, e.g., nitride, from the sidewalls of the Si-containing channel is removed so as to expose an edge of the Si-containing channel that can be extended by means of Si-containing overgrowth forming Si-containing regions atop the self-aligned isolation region. The Si-containing regions can be implanted forming extended source/drain regions therein and a silicide may be formed atop the extended source/drain regions.
The DGFET of the present invention, which has substantially reduced parasitic capacitance, comprises:
a doped back-plane region having isolation regions located adjacent thereto;
a back-gate dielectric stack including at least a bottom back-gate nitride located atop a surface portion of said doped back-plane region not containing said isolation regions;
a Si-containing layer having edges located atop said back-gate dielectric stack, each of said Si-containing edges including a source/drain region;
a front gate dielectric located atop portions of said Si-containing layer;
a front gate located atop said front gate dielectric; and
Si-containing regions located adjacent to said front gate and over said isolation regions, said Si-containing regions being in contact with said source/drain regions.
In a preferred embodiment of the present invention, the isolation regions are self-aligned with the front gate.
The present invention also provides a method of fabricating the above-mentioned DGFET. Specifically, the method of the present invention comprises the steps of:
providing a structure which includes at least a doped back-plane region, a back-gate dielectric stack including at least a bottom back-gate nitride formed atop said doped back-plane region, a Si-containing layer having edges formed atop said back-gate dielectric stack, a front gate dielectric formed atop said Si-containing layer, and a front gate formed atop said front gate dielectric, said structure having isolation trench regions adjacent to at least said doped back-plane region;
forming insulating spacers on exposed vertical sidewalls of said front gate;
forming protective spacers on said structure about said insulating spacers and covering said edges of said Si-containing layer;
forming isolation regions in regions of said structure which are adjacent to, and overlaying a portion of said doped back-plane region, whereby said protective spacers and said bottom back-gate nitride protect said Si-containing layer from oxidizing;
removing said protective spacers exposing said edges of said Si-containing layer; and
selectively growing Si-containing regions above and in contact with said edges.
The method of the present invention further includes forming extended source/drain regions in portions of the Si-containing regions as well as forming silicide regions over the extended source/drain regions.
The present invention, which provides self-aligned isolation DGFETs and a method of fabricating the same, will now be described in more detail by referring to the drawings that accompany the present application. It is noted that in the drawings and description that follows an NFET having a P-doped back-plane is described. Although such a structure is shown and described, the present invention contemplates a structure having the opposite polarity, i.e., a PFET having an N-doped back-plane. The structure having the opposite polarity is fabricated by changing the dopant species described herein below to the opposite polarity.
The other components shown and labeled in
The method of forming the self-aligned isolated DGFET of the present invention shown in
The structure illustrated in
The Si-containing layer 18 is formed by a conventional deposition process including, for example, chemical vapor deposition (CVD), plasma-assisted CVD, evaporation or chemical solution deposition. The Si-containing layer 18 may have any thickness when it is first applied to the transfer wafer. Typically, the Si-containing layer 18 has an initial thickness of from about 50 to about 500 mm, which may be thinned after performing a subsequent bonding process.
The back-gate nitride 15 is then formed atop the Si-containing layer 18 by utilizing a conventional deposition process or, alternatively, the back-gate nitride 15 may be formed by a thermal growing process. The thickness of the back-gate nitride 15 may vary, but typically, the back-gate nitride 15 has a thickness of from about 1 to about 5 nm.
Next, the back-gate dielectric 16 is formed atop the back-gate nitride 15 utilizing a conventional deposition process such as CVD. Alternatively, the back-gate dielectric 16 may be formed by a thermal processing step. The back-gate dielectric 16 may be composed of an oxide or oxynitride, with preference given to oxide dielectrics. Suitable examples of oxides that can be employed as the back-gate dielectric 16 include, but are not limited to: SiO2, Al2O3, ZrO2, HfO2, Ta2O3, TiO2, perovskite-type oxides and combinations and multilayers thereof. The thickness of the back-gate dielectric 16 may vary, but typically, the back-gate dielectric 16 has a thickness of from about 2 to about 20 nm.
The polysilicon back-plane region 14 is then formed atop the back-gate dielectric 16 utilizing a conventional deposition process such as CVD. The polysilicon back-plane region 14 has a thickness of from about 50 to about 500 nm. Next, the bottom insulator 12 is formed atop the polysilicon back-plane 14 utilizing a conventional deposition process or a conventional thermal growing process. The bottom insulator 12 may be an oxide, nitride or oxynitride, with preference given to oxides such as SiO2. The thickness of the bottom insulator 12 may vary, but typically the bottom insulator 12 has a thickness of from about 100 to about 400 nm.
After the transfer wafer containing layers 18, 16, 15, 14, and 12 is provided, the exposed surface of the bottom insulator 12 is bonded to the handle wafer 10 using a conventional bonding process that is well known to those skilled in the art. After bonding, the transfer wafer is removed from the bonded structure leaving the Si-containing layer 18 exposed. Specifically, the transfer wafer may be removed by grinding and etching. During the grinding and etching process, the Si-containing layer 18 may be thinned to a thickness of less than 20 nm. A portion of this thinned Si-containing layer 18 is used in the present invention as the body region of the DGFET.
After the removal of the transfer wafer and thinning of the Si-containing layer 18, the pad oxide 20 is formed atop the thinned Si-containing layer 18 by utilizing a conventional deposition process or by utilizing a conventional thermal oxidation process. Notwithstanding which technique is employed, the pad oxide 20 typically has a thickness of from about 2 to about 10 nm, with a thickness of from about 3 to about 5 nm being more highly preferred.
The polish stop layer 22, which may be composed of a nitride and/or oxynitride, is then formed atop the pad oxide 20 utilizing a conventional deposition process well known to those skilled in the art. The thickness of the polish stop layer 22 may vary and is of no significant importance to the present invention.
The above description provides one means for providing the initial structure shown in
After forming the initial structure shown in
Following the etching step, the patterned photoresist is removed utilizing a conventional stripping process, and a second photoresist (not shown) is applied and patterned by lithography to include a deep trench pattern. The deep trench pattern is then transferred into the previously etched structure by etching through exposed portions of the polysilicon back-plane region 14 and the bottom insulator 12 stopping atop an upper surface of the handle wafer 10. Following the transfer of the deep trench pattern into the structure, the second photoresist is removed utilizing a conventional stripping process.
After forming the isolation trench opening 24 into the structure, a trench oxide liner 26 is formed via a thermal oxidation process so as to cover at least the exposed sidewalls of the Si-containing layer 18 and the polysilicon back-plane region 14. The isolation trench opening 24 containing trench oxide liner 26 is then filled with dielectric trench material 28 such as a CVD oxide or tetraethylorthosilicate (TEOS) and planarized to the polish stop layer 22 providing the planar structure shown, for example, in
A first implantation mask (not shown) is then formed on portions of the structure, and thereafter ions of a first conductivity type, e.g., N or P, are ion implanted into the polysilicon back-plane region of the structure which does not include the first implantation mask. The first implantation mask is removed and a second implantation mask covering at least the previously ion implanted region is then formed. After forming the second implantation mask, ions of a second conductivity type, e.g., N or P, which differ from the first conductivity type are ion implanted into polysilicon back-plane region not containing the second implantation mask. The dosage of the ions used during these implantations may vary and may be optimized depending on the type of device being formed. After the second ion implantation process, the second ion implantation mask is removed and then the structure is subjected to an annealing process which is performed utilizing conditions that activate and drive the dopant ions upward through each polysilicon back-plane region until the region is uniformly doped. In the present invention, this annealing is typically performed in an inert gas ambient at a temperature of about 950° C. or greater for a time period of from about 30 minutes or less.
After forming the doped back-plane regions, the polish stop layer 22 is removed from the structure utilizing an etching process that is selective in removing the polish stop material as compared to oxide. This etching step of the present invention removes the polish stop layer 22 from the structure and exposes the underlying pad oxide 20. For example, phosphoric acid can be used in selectively removing the polish stop layer 22 from the structure. After the polish stop layer 22 has been removed from the structure, the exposed pad oxide layer, i.e., layer 20, is selectively removed so as to expose the Si-containing layer 18. Any conventional etching process that is selective in removing oxide as compared to Si can be employed. For example, dilute hydrofluoric acid can be used in selectively removing the pad oxide layer 20 from the structure.
After the pad oxide layer 20 has been selectively removed, a front (or top) gate dielectric 34 is formed atop the exposed surfaces of the Si-containing layer 18. The front gate dielectric 34 may be composed of the same or different dielectric material as the back-gate dielectric 16 as well as nitrides. Moreover, the front gate dielectric 34 may be formed utilizing any conventional deposition process such as CVD. The thickness of the front gate dielectric 34 may vary, but typically the front gate dielectric 34 has a thickness of from about 1 to about 5 nm.
A gate electrode material such as polysilicon, a conductive metal, a silicide, or any combination thereof, including multilayers is formed atop the structure utilizing a conventional deposition process and then a mask material such as an oxide or nitride or oxynitride is formed via a conventional deposition process atop the gate electrode material. The preferred material for the gate electrode is polysilicon.
The mask and the gate electrode material are then patterned providing a patterned gate electrode 36 and a patterned mask 38 atop a portion of the front gate dielectric 34 that lies atop the P-doped back-plane region 32. The patterning is achieved utilizing a patterned resist mask (not shown) and etching. The resultant structure including the front gate dielectric 34, the patterned gate electrode 36 and the patterned mask 38 is shown, for example, in
Insulating spacers 40 are formed atop portions of the front gate dielectric 34 as well as the exposed sidewalls of at least the patterned gate electrode material 36 and a portion of the patterned mask 38. The insulating spacers 40 are composed of an insulating material including, for example, silicon dioxide, which can withstand a silicon nitride etch. The insulating spacers 40 are formed by deposition of an insulating material and etching. These spacers typically have a lateral thickness of from about 0.5 to about 3 nm, with a lateral thickness of from about 1 to about 2 nm being more highly preferred. The structure that is formed after the above steps have been performed is shown, for example, in
In an optional embodiment (not shown), the exposed edges 46 of the Si-containing layer 18 may be implanted with source/drain implants at this point of the present invention. If performed at this stage of the process, an angled ion implantation process is used in forming the source/drain regions in the Si-containing layer 18.
Next, the exposed portions of the back-gate dielectric 16 are removed stopping atop a surface of the back-gate nitride 15. Portions of the back-gate dielectric 16 are removed at this point of the present invention utilizing a selective etching process such as a chemical wet etch that is selective against removing nitride. The resultant structure after this etching process has been performed is shown, for example, in
After formation of the protective spacers 42, the structure shown in
After formation of the self-aligned isolation region 44, the spacers 42 as well as a portion of the back-gate nitride 15 which previously contained the spacers 42 are removed from the structure utilizing an etching process that is selective in removing nitride. The removal of the protective material from the structure again exposes the edges 46 of Si-containing layer 18. The amount of over etch should be controlled so as not to undercut the nitride all the way to the recessed back-gate.
If not previously formed, source/drain regions 50 may now be formed into the exposed edges 46 utilizing an angled ion implantation process. The exposed edges 46 containing the source/drain regions 50 serve as a seed region to grow a Si-containing region. The resultant structure that is formed after the above processing steps have been performed is illustrated in
Following formation of the contact regions 52, a resist mask (not shown) is formed atop portions of the structure which overlays the N-doped back-plane region 30, and extended source/drain regions 54 are formed in the exposed regions of the contact regions 52 utilizing a shallow ion implantation process. The shallow implantation process is required to ensure that the dopants are not implanted into portions of the Si-containing layer 18 that serve as the channel of the DGFET of the present invention. The above steps of resist blocking and ion implantation can be used in forming the implants for the PFET (not shown).
Spacers 56 are then formed atop the extended source/drain regions 54 utilizing conventional deposition and etching. Note that portions of the spacers 56 are into contact with exposed vertical surfaces of the insulating spacers 40. The mask 38 located atop the patterned gate electrode 36 is then removed.
A resist mask (not shown) is then formed atop portions of the structure and the exposed portions of the self-aligned isolation regions 44 formed atop the doped back-plane regions are removed utilizing a selective etching process such as RIE. After the selective etching process has been performed, the resist mask mentioned above is stripped from the structure.
Another resist mask (not shown) is formed, and then deep implants of an N-type dopant are performed into portions of the exposed N-doped back-plane region 30, portions of exposed epi-Si source/drain contact region 52, and portions of the gate electrode 36. In
While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
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|U.S. Classification||438/283, 257/E21.421|
|International Classification||H01L21/336, H01L29/786, H01L21/76, H01L21/265|
|Cooperative Classification||H01L29/66772, H01L29/78648|
|European Classification||H01L29/66M6T6F15C, H01L29/786D2, H01L29/786D|
|Aug 30, 2013||REMI||Maintenance fee reminder mailed|
|Jan 19, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Mar 11, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140119
|Sep 3, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK
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Effective date: 20150629
|Oct 5, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001
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