|Publication number||US7649797 B2|
|Application number||US 12/031,110|
|Publication date||Jan 19, 2010|
|Filing date||Feb 14, 2008|
|Priority date||Feb 28, 2007|
|Also published as||US20080205183|
|Publication number||031110, 12031110, US 7649797 B2, US 7649797B2, US-B2-7649797, US7649797 B2, US7649797B2|
|Inventors||Soo-Man Hwang, Ho-Cheol Lee|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Referenced by (2), Classifications (11), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2007-0019964 filed on Feb. 28, 2007, the subject matter of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a self-refresh circuit and operation within a semiconductor memory device. More particularly, the invention relates to a self-refresh control circuit, a semiconductor memory device including a self-refresh control circuit, and a method of controlling a refresh operation in a semiconductor memory device.
2. Description of the Related Art
Random access memory (RAM) is widely used to store data and/or related commands within a system or host device. RAM has several advantages over other forms of memory including an ability to access all addresses in the RAM at substantially the same speed.
RAM may be further classified as static RAM (SRAM) and a dynamic RAM (DRAM). SRAM preserves stored data so long as the SRAM is powered. This data preservation capability within SRAM is enabled by a relatively complicated configuration of four or six transistors arranged in a symmetric latch structure. As a result, SRAM is relatively costly to manufacture and difficult to integrate. In contrast, DRAM may be implemented with a single access transistor and a corresponding storage node such as a capacitor. Accordingly, DRAM is cheaply manufactured and relatively easy to integrate. Unfortunately, DRAM gradually loses stored data because the storage node commonly suffers from current leakage. This DRAM characteristic conventionally mandates the inclusion of a refresh circuit adapted to periodically restore lost charge indicative of stored data to the storage node. The periodicity of the refresh operation is referred as “a refresh rate.”
Different operating modes for the system or host device incorporating DRAM will often dictate the refresh rate and other related parameters for the refresh operation. During a standby mode or similar powered-down mode of operation for a system or host device, the data stored in DRAM is often preserved by application of a so-called “self-refresh operation”. Thus, by means of an effective self-refresh operation, DRAM may be implemented to mimic the performance advantages of SRAM, albeit generally at lower cost.
As is conventional, memory cell array 20 includes a plurality of memory cells coupled to word lines and bit lines. The memory cells are typically divided into designated block units and/or bank units. For convenience of illustration, only a single memory cell is illustrated in memory cell array 20 of
Voltage generator 30, which may be referred to as a boosting circuit, generates a high voltage by boosting a power supply voltage using internal pumping capacitors. The generated high voltage is provided to circuitry associated with memory cell array 20.
Row selection circuit 40 includes a row decoder 41 and a word line driving circuit 42. Row decoder 41 decodes a row address signal RADD and provides a decoded row address signal DRADD driving a selected word line (i.e., WLj). Word line driving circuit 42 includes a plurality of drivers respectively coupled to word lines. Only one driver is illustrated in
In general, a voltage higher than the power supply voltage is applied to the selected word line in order to turn ON the access transistor TA. Voltage generator 30 generates such this high voltage in response to the word line enable signal WEN and provides the high voltage to internal circuits such as word line driving circuit 42.
It takes a predetermined period of time to charge the pumping capacitor(s) used to implement voltage generator 30. Accordingly the output voltage may not be sufficiently boosted during an initial stage of the boosting operation, if the boosting operation is performed in synchronization with the word line enable signal WEN. Thus, if the selected word line is enabled while the output voltage VOUT is insufficiently charged, the stored data may be altered by application of an abnormal refresh operation. To prevent the abnormal refresh operation, the word line enable signal WEN should be activated in the refresh mode longer than in a read mode. Nevertheless, the word line may be developed while the output voltage VOUT has an insufficient level, thereby causing the abnormal refresh operation.
Accordingly, conventional self-refresh operations experience problems associated with abnormal refresh operation and/or the excessive power consumption.
In one embodiment, the invention provides a refresh control circuit in a semiconductor memory device, comprising; a refresh period controller configured to generate a control signal in response to a self-refresh signal, wherein the control signal indicates a nominal initiation of a refresh period, a voltage generator configured to generate an output voltage in response to the control signal, wherein the output voltage is boosted from a low voltage to a high voltage during the refresh period, and a word line enable circuit configured to generate a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage.
In another embodiment, the invention provides a semiconductor memory device, comprising; a memory cell array including a plurality of memory cells coupled to word lines and bit lines, respectively, a refresh control circuit configured to generate an output voltage and a word line enable signal in response to a self-refresh signal indicating a nominal initiation of a refresh period, wherein the output voltage is boosted during the refresh period, the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage, and a row selection circuit configured to enable a selected word line in relation to a row address signal, the output voltage, and the word line enable signal.
Embodiments of the present invention now will be described with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited being limited to only the illustrated embodiments. Rather, these embodiments are provided as teaching examples. Throughout the drawings and written description, like reference numerals refer to like or similar elements.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Refresh control circuit 900 generates an output voltage VOUT and a word line enable signal WEN in response to a self-refresh signal SREF, such that the output voltage VOUT is boosted during a refresh period and the word line enable signal WEN is activated following a delay associated with each refresh period. The word line enable signal delay may be determined in relation to the time required to sufficiently boost the output voltage VOUT. The self-refresh signal SREF may be provided by a command decoder (not shown), such as the type commonly used to decode commands received from an external system or device, such as a memory controller.
In the illustrated example of
However, returning to
When semiconductor memory device 1000 is operating in self-refresh mode, the associated self-refresh operation may be performed periodically without repeated external commands. To accomplish this, semiconductor memory device 1000 utilizes address counter 700 and selection circuit 600. Address counter 700 generates an internal row address signal IRADD that may be changed during the refresh period. Selection circuit 600 selects between the internal row address signal IRADD and an external row address signal XRADD in response to the self-refresh signal SREF, and outputs the selection as row address signal RADD to row selection circuit 500. In one embodiment, selection circuit 600 may be implemented using a multiplexer that selects the internal row address signal IRADD when the self-refresh signal SREF is activated, or selects the external row address XRADD when the self-refresh signal SREF is deactivated.
Refresh period controller 100 a generates a control signal CNT in response to a self refresh signal SREF. As illustrated in
For example, refresh period controller 100 a may be implemented using a pulse generator and a counter counting clock cycles and generating (activating) the control signal CNT on the basis of a predetermined number of counted clock cycles in order to define the duration of the refresh period tREF. The predetermined number of clock cycles may be provided as part of a mode register set (MRS) signal, for example, using conventional techniques. Alternatively, a frequency control circuit such as a phase-locked loop or a delay-locked loop may be used to generate a clock signal having a frequency defined in relation to the current operating conditions of the semiconductor memory device. In such a case, the control signal CNT may be provided by dividing the clock signal to determine the refresh period tREF. Typically, the leakage current associated with the memory cells of memory cell array 400 increases with operating temperature. Thus, refresh period controller 100 a may further comprise (or be associated with) a temperature detector providing data indicative of the current operating temperature “temp”. In this manner, the output of the frequency control circuit may be adjusted for temperature, which in turn adjusts the timing and/or duration of the refresh period.
Voltage generator 200 a generates an output voltage VOUT in response to the control signal CNT such that the output voltage VOUT is boosted during each refresh period tREF. Voltage generator 200 a may be configured to receive a power supply voltage VCC and generate the output voltage VOUT using conventional techniques. Further, as is conventionally understood, voltage generator 200 a is configured to periodically pump up the power supply voltage VCC to a high voltage VPP.
The output voltage VOUT will nominally be maintained at the lower VCC level during a standby mode or similar power-down mode of operation. Various configurations and related operating principals for voltage generator 200 a are well known to those skilled in the art. However, in one embodiment of the invention, voltage generator 200 a comprises a boost circuit 202 a including one or more pumping capacitor(s), and a boost controller 201 a controlling operation of boost circuit 202 a. In this case, boost controller 201 a generates a pumping signal in response to the control signal CNT, such that the pumping signal is activated during the refresh period. Boost circuit 202 a may be used to boost the output voltage VOUT in response to the pumping signal.
Word line enable circuit 300 a generates a word line enable signal WEN in response to the control signal CNT. The word line enable signal WEN is activated following a delay tD1 after the actuation of the control signal CNT (i.e., after an indication of the nominal initiation of the refresh period tREF). That is, the refresh period tREF is actually initiated after the indication of the nominal initiation of the refresh period tREF by the control signal CNT. The word line enable signal delay tD1 may be determined in relation to an amount of time necessary to sufficiently boost the output voltage VOUT. This delay will vary with the configuration of the voltage generator 200 a and the overall performance characteristics of semiconductor memory device 1000.
In the embodiment illustrated in
The collective operation of these two circuits forming the word line enable circuit 300 a of the illustrated example, determines the refresh period tREF and a timed occurrence of the word line enable signal WEN as a function of an WEN active period tA and a precharge period tP.
The operation of refresh control circuit 900 a of
As illustrated in
As already noted, the word line enable signal delay tD1 may be determined in relation to the time required to sufficiently boost the output voltage VOUT. This delay value may be determined, for example, by the use of a simulation modeling the performance characteristics of voltage generator 200 a in relation to overall semiconductor device design.
As such, the word line enable signal WEN may be activated when the output voltage VOUT is fully boosted up from its low voltage level VCC to its high voltage level VPP. With this timing definition, the abnormal refresh operation that plagues the conventional semiconductor memory device may be avoided (i.e., the insufficient application of voltage to the word line can be prevented) and at the same time excessive power consumption may be avoided.
Delay circuit 320 a may be used to determine whether the initial word line enable signal WEN0 is delayed or not according the operating mode of the semiconductor memory device. Thus, delay circuit 320 a may be configured to generate the word line enable signal WEN by delaying the initial word line enable signal WEN0 for the defined delay period tD1 while the self-refresh signal SREF is activated (i.e. during a self-refresh mode), but by merely outputting without delay the initial word line enable signal WEN0 as the word line enable signal WEN while the self-refresh signal SREF is deactivated (i.e. during a write mode or a read mode).
Delay unit 325 delays the initial word line enable signal WEN0 by the delay period tA1 in order to generate a delayed version of the word line enable signal WEN. First transfer gate TG1 operates in response to complementary versions the self-refresh signal SREF and is turned ON while the self-refresh signal SREF is deactivated. As such, first transfer gate TG1 passes the initial word line enable signal WEN0 as the word line enable signal WEN without delay during “normal” operating modes, such as read/write modes. Second transfer gate TG2 is turned ON and passes the delay version of the word line enable signal from delay unit 325 while the self-refresh signal SREF is activated.
In certain embodiments of the invention, transfer gates TG1 and TG2 may be replaced with arbitrary switching elements that operate in response to the self-refresh signal SREF, and delay unit may be implemented with an inverter chain.
The self-refresh mode of operation may be terminated for many reasons including receipt of an external commands CMD. When the self-refresh mode is terminated, voltage generator 200 a maintains the output voltage VOUT at a level approximately equal to the high voltage VPP. Assuming a time duration tSRX between termination of the self-refresh mode and a next command ACT, it is possible that an abnormal operation may occur if the output voltage VOUT drifts to an insufficient level. In order to prevent this occurrence, the boost controller in voltage generator 200 a may further activate the pumping signal VCRT at the termination point Tx in response to the deactivation of the self-refresh signal SREF.
However, in contrast to the embodiment of
Hereinafter, the operation of refresh control circuit 900 b illustrated in
The respective elements in the refresh control circuit according to the foregoing embodiments of the invention may perform other functions in addition to those described in relation to the refresh operation, and may be variously disposed in respective functional circuit blocks within the overall architecture of the semiconductor memory device.
Even though the present invention has been described in the context of a DRAM including DRAM memory cells requiring periodic refresh, it will be understood that the teachings of the invention may be applied to any type of semiconductor device comprising data storage circuits benefiting from periodic refresh during a standby mode or similar power-down mode of operation.
Embodiments of the invention provide a semiconductor device having overall power consumption reduced by improved control over the timings of a word line enable signal and a voltage applied to word lines during a self-refresh mode of operation. Further, abnormal operations caused by insufficiently boosted word line voltages may be prevented, thereby improving performance of the semiconductor memory device.
While the example embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5594704 *||Apr 10, 1995||Jan 14, 1997||Mitsubishi Denki Kabushiki Kaisha||Synchronous semiconductor memory device|
|US6134167 *||Jun 4, 1998||Oct 17, 2000||Compaq Computer Corporation||Reducing power consumption in computer memory|
|US6426908 *||Feb 23, 2000||Jul 30, 2002||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device with reduced current consumption in data hold mode|
|US6504787||Nov 16, 2001||Jan 7, 2003||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device with reduced power consumption during refresh operation|
|US20020186609 *||Nov 16, 2001||Dec 12, 2002||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device with reduced power consumption during refresh operation|
|US20050231267 *||Apr 19, 2005||Oct 20, 2005||Hynix Semiconductor Inc.||High voltage generation circuit|
|US20050275977 *||Jun 14, 2004||Dec 15, 2005||Joshi Rajiv V||Multi-level power supply system for a complementary metal oxide semiconductor circuit|
|JP2001283586A||Title not available|
|KR20030039950A||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US9028141 *||Oct 20, 2011||May 12, 2015||Hynix Semiconductor Inc.||On die thermal sensor of semiconductor memory device|
|US20120033507 *||Feb 9, 2012||Chun-Seok Jeong||On die thermal sensor of semiconductor memory device|
|U.S. Classification||365/222, 327/536|
|Cooperative Classification||G11C11/4074, G11C11/4087, G11C2211/4065, G11C11/406, G11C11/40615, G11C2211/4068|
|European Classification||G11C11/406I, G11C11/406|
|Feb 15, 2008||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO., LTD.,KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HWANG, SOO-MAN;LEE, HO-CHEOL;REEL/FRAME:020524/0253
Effective date: 20080213
|Mar 14, 2013||FPAY||Fee payment|
Year of fee payment: 4