|Publication number||US7663632 B2|
|Application number||US 09/981,484|
|Publication date||Feb 16, 2010|
|Filing date||Oct 17, 2001|
|Priority date||Jun 15, 1999|
|Also published as||EP1061434A2, EP1061434A3, EP1061434B1, EP1688907A2, EP1688907A3, EP1688907B1, EP2309376A2, EP2309376A3, EP2309376B1, EP2323029A2, EP2323029A3, US6424320, US8310489, US20030137483, US20100085366|
|Publication number||09981484, 981484, US 7663632 B2, US 7663632B2, US-B2-7663632, US7663632 B2, US7663632B2|
|Inventors||Edward G. Callway|
|Original Assignee||Ati Technologies Ulc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (31), Non-Patent Citations (7), Referenced by (7), Classifications (20), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuing application and claims the benefit under 35 U.S.C. § 120 of U.S. patent application Ser. No. 09/333,736, filed Jun. 15, 1999, now U.S. Pat. No. 6,424,320 and is owned by instant assignee.
The present invention generally describes a method and apparatus for providing video signals and more specifically describes a method and apparatus for rendering video signals from multiple video adapters.
Video graphic adapters (VGA) are used to render video signals to be displayed on display devices such as computer monitors. In operation, VGAs will generally receive graphics information from a system, such as a computer system, and perform the necessary graphics calculations upon the received information in order to render graphics signals. Graphics calculations are performed for many different types of information, including lighting information, user view information, texture information, and Z-plane data information, which indicates where one device is relative to another device. Once all calculations have been performed upon an object, the data representing the object to be displayed is written into a frame buffer. Once the graphics calculations have been repeated for all objects associated with a specific frame, the data stored within the frame buffer is rendered to create a video signal that is provided to the display device.
The amount of time taken for an entire frame of information to be calculated and provided to the frame buffer becomes a bottleneck in a video graphics system as the calculations associated with the graphics become more complicated. Contributing to the increased complexity of the graphics calculations is the increased need for higher resolution video, as well as the need for more complicated video, such as 3-D video or stereoscopic video. The video image observed by the human eye becomes distorted or choppy when the amount of time taken to provide an entire frame of video exceeds the amount of time which the display must be refreshed with a new graphic, or new frame, in order to avoid perception by the human eye.
The use of multiple graphic adapters has been proposed in order to provide data to the frame buffer at a rate fast enough to avoid detection by the human eye. Current methods of using multiple graphics devices have partitioned the graphics associated with each such that each one of the multiple processors is responsible for rendering a portion of each frame. Each processor renders a portion of a frame in order to assure data is provided to the frame buffer within a required amount of time.
Once such partitioning method split the screen into odd and even display lines, whereby one video adapter would render all of the odd lines associated with a specific frame, while the second device would render all of the even lines associated with the frame. Another prior art method split the screen into two discrete areas, such as a top and a bottom half, whereby each display device would be responsible for rendering one portion of the screen. However, problems with these implementations occur.
One problem with present implementations is that all of the video data from the system needs to be sent to both of the data graphics devices. For example, in the implementation where the graphics device split the odd and even lines it is necessary for each video device to receive the object's video information from the system. The amount of data sent by the system to the graphics adapters in effect doubles, because each graphics adapter needs all the information. In an implementation where the data is be sent to both devices at the same time, there is hardware and/or software overhead associated with controlling the reception of the data.
Workload distribution is another problem associated with known graphics systems having multiple adapters. When each of the two graphics devices is processing a portion of a single frame, a likelihood exists that the amount of work to be done by one of the processors for a given frame will be significantly greater than the amount of work being done by the other video device. For example, where a first video device is to render the video for the top half of the screen, it is likely that it will have fewer calculations to perform than the device calculating the graphics for the bottom half of the frame. One reason for this disparity in workload distribution is because it is common for the top half of a frame to contain skyscape information which is less computationally intensive than for the objects associated with action video often found on the bottom half of a display device or frame. When the workload distribution is not even, one graphics device will in effect end up stalling while the second graphics device completes its calculations. This is inefficient.
Yet another problem associated with the prior embodiments is that each of the graphics devices has to calculate the shape of each and every object on the frame. Each device must calculate each object's shape in order to determine whether or not the object, or a portion of the object, must be further processed by the graphics engine associated with the graphics device. An associated problem is that when an object straddles the demarcation line between an area that the first graphics device is to process and an area that the second graphics device is to process, it is necessary for both devices to process the object. For example, when a portion of an object is in the top half of the screen, and a portion on the bottom half of the screen, calculations associated with the object are calculated by both graphic devices.
Yet another problem with the known implementations of multiple graphic devices is the need to carefully match the digital-to-analog converters (DACs) associated with each VGA. The DACs of each VGA provide a plurality of voltages, one for each video component, such as the red/green/blue components. If the DACs are not carefully matched, it is possible for colors viewed on a display device to have slightly different shades of color because of the lack of calibration between the devices' DACs.
Therefore, it would be desirable to have a method and apparatus that allows the use of multiple video graphics devices that overcome the problems associated with the prior art.
Multiple Video Graphics Adapters (VGAs) are used to render video data to a common port. In one embodiment, a first VGA renders an entire frame of video and provides it to the output port through a switch. The next adjacent frame will be calculated by a separate VGA and provided to the output port through the switch. A voltage adjustment is made to a digital-to-analog converter (DAC) of at least one of the VGAs in order to correlate the video-out voltages being provided by the VGAs. This correlation assures that the color being viewed on the screen is uniform regardless of which VGA is providing the signal. A dummy switch receives the video-output from each of the VGAs. When a VGA is not providing information to the output port, the dummy switch can be selected to provide the video-output of the selected VGA a resistance path which matches the resistance at the video port. This allows the video graphics controller to maintain a constant thermal state to avoid further variations.
In another embodiment the System Bridge 170 would not be used. By providing appropriate control signaling, the Adapters 110 and 120 can be coupled to a common AGP or PCI bus system bus.
In yet another embodiment, one adapter can be coupled to a PCI bus, while a second adapter would be coupled to an AGP bus. In such a manner, it would be possible to selectively provide a specific frame of data to one adapter or another.
In the implementation of
It is necessary to synchronize the operations of the VGAs 110 and 120 in order to ensure that the video signals received from VGA 110 and 120 at Video Port1 provide a contiguous video-out signal. In the implementation illustrated, the VGA 110 acts as a master in that it has a dedicated oscillator 112 providing a reference signal. The first VGA 110 is connected to the Controller 130 through the signal labeled VGA1 CONTROL. Included in VGA 1 CONTROL is the vertical synchronization (synch) signal generated by the VGA 110 and the horizontal synchronization signal generated by the VGA 110. The vertical and horizontal synch signals represent periodic signals used by the controller 130 in order to synchronize the vertical and horizontal synch signals of the VGA 120 to those of the VGA 110.
The controller 130 provides a signal labeled SYNCH CONTROL to the VGA 120. The SYNCH CONTROL signal can be a clock signal, whereby the entire VGA operates based on the clock, or it can be some other type of synchronization control mechanism indicating that the generation of a horizontal or vertical synch signal should be sped up or slowed down in order to be synchronized to the VGA 110. In addition, the VGA 120 provides interfaces to the Controller 130 through the signal labeled VGA 2 CONTROL.
The VGA 110 provides a signal labeled RGB1, which represents a plurality of video-output components. In the specific example of
VGA 120 also provides color component signals labeled RGB2, which is analogous to the RGB1 signal discussed above. The RGB2 signal is provided to a second input port of switch 143 and a second input port of switch 141. In addition, each of the signals RBG1 and RGB2 are provided respectively to the first and second input port of switch 142.
Switch 143 receives a select signal labeled PORT1 SELECT from Controller 130 to indicate which of the received color component signals RGB1 and RGB2 should be provided to the port 151. The output of switch 143 is labeled RGB OUT1. Likewise, the switch 141 is connected to the Controller 130 to receive a signal labeled PORT2 SELECT. The PORT2 SELECT signal will select one of the color component signals RGB1 or RGB2. The output port of switch 141 is labeled RGB OUT2. It will be recognized by one of ordinary skill in the art that in other embodiments, it will be possible for only one of the video-out ports to have access to both of the VGAs. For example, it would be possible for only Video Port1 to receive RGB signals from both the VGA 110 and the VGA 120.
The switch 142 operates as a “dummy” switch in that in the embodiment shown it does not provide data to a user accessible video-out port. The video switch 142 is controlled by Controller 130. In operation, the Controller 130 selects the VGAs RGB signal from the VGA that is not driving video to an output port. This allows for the VGA to provide a signal to the dummy switch, allowing for thermal consistency to be maintained by the VGAs when not driving a user accessible signal. In other words, when a VGA is not currently driving either Video Port1 or Video Port2, its RGB signal would be selected by switch to drive the resistor R. The resistance value of the resistor R would be such that it would be approximately equal to that seen by the video-output ports 151, and 152. In this implementation, the load seen by a VGA at its RGB output port would be approximately the same whether or not it is actively driving user accessible video or driving merely the dummy load labeled R.
In the specific implementation illustrated in System 100, the RGB OUT1 signal is received by a Video-Out Adjust 160. The Video-Out Adjust Portion 160 provides at least one signal labeled ADJUST CONTROL to the Controller 130. The signal ADJUST CONTROL is illustrated to be a bus of size M, in that multiple signals can be represented. In addition, the Video-Out Adjust 160 provides a signal labeled Adjust Signal to the VGA 120.
The Comparator 220 receives the signal G and a voltage reference signal labeled VREF. VREF represents a voltage to which the color component signal G is to be compared. In a specific embodiment, the VREF signal is chosen to have a value approximately three-quarters of the maximum voltage value that the color component signal G can obtain. In other words, if 0.7 volts is the maximum value that the color component signal G can obtain, the VREF value will be chosen to be approximately 75% of 0.7 volts. In other embodiments, other voltage values can be used.
The Comparator 220 provides an output signal labeled COMPARE SIGNAL. The COMPARE SIGNAL will indicate when a match occurs between the voltage of the color component signal G and the VREF signal. In general, the COMPARE SIGNAL will toggle from an inactive state indicating the signals do not match to an active state indicating that the signals have matched. It will be understood by one of ordinary skill in the art that if the Comparator 220 were to comprise a simple differential amplifier, the COMPARE SIGNAL would maintain the active state indicating a match, even when the green signal attains a voltage level significantly higher than the VREF signal. In other words, in the embodiment illustrated, the toggling of the signal COMPARE SIGNAL from one state to another indicates a match has occurred. The signal labeled ADJUST CONTROL is received by the Adjust Signal Generator 230. The Adjust Signal Generator 230, in response to a signal from Control 130 received as part of the ADJUST SIGNAL CONTROL, provides a signal labeled ADJUST SIGNAL. In a specific embodiment, the ADJUST SIGNAL GENERATOR 230 is a variable reference source. The ADJUST SIGNAL provides a value for calibrating the DAC values of at least one of the VGAs.
The VGA 110 is connected to a VIDEO RAM 121, which store information, such as frame buffer and color palette information, associated with the VGA 110. In a similar manner, the VGA 120 is connected to a VIDEO RAM 122 which will be maintain frame buffer and color palette information associated with the VGA 120.
In operation, at least a portion of the VGA1 CONTROL signal is received by the first video controller 310. As illustrated, the VGA1 CONTROL signal comprises N signals that are received by the first video-out controller. In addition, the VGA1 Control signals are received by the Synchronize Device 350. It should be noted that M and N may be the same value. Likewise, the signal VGA2 CONTROL is received by the second video-out controller labeled VIDEO OUT2 CONTROL 320, and the Synchronize Device 350. Information transmitted over the LOCAL BUS is also received by the video-out controllers 310 and 320. It should be noted that information over the Local Bus will generally be received by the controller 130 at a single port, whereby the data can be provided to one or both of the two video-out controllers as appropriate.
The first video-out controller 310 provides a first port select signal labeled PORT1 SELECT to the switch 143 in order to provide a color component signal from one of the VGA 110 or 120. Likewise, the second video-out controller 320 provides a signal labeled PORT2 SELECT to the switch 141 in order to select one of the color component signals from the first VGA and the second VGA. The first video-out controller 310 and the second video-out controller 320 respectively provide signals labeled VIDEO1 CONTROL and VIDEO2 CONTROL to the ports 151 and 152 respectively. These video control signals generally include the horizontal and vertical synchronization signals, which are provided with the color component information. Each of the first and second video controllers 310 and 320 can provide requests to the Dummy Port Select Controller 360. When requested, the Dummy Port Select Controller 360 selects one of the two color component signals through switch 142 to be provided to the load resistor R.
The controller 130 further includes a synchronization device 350. In the embodiment illustrated, the vertical and/or horizontal synchronization signals are received by the phase locked loop (PLL) 352 from each of the first VGA 110, and the second VGA 120. By synchronizing the vertical and horizontal synchronization signals of each VGA, it is possible to use a voltage-controlled oscillator 353 in order to provide a synchronization control signal. In the specific example illustrated, the signal labeled SYNCH CONTROL SIGNAL is provided to the VGA 120, and will generally be a clock signal that can be sped up or slowed down based upon the desired synchronization.
In other embodiments, the synchronization device 350 can be used to indicate to one and/or both of the controllers 310 and 320 when to delay by one or more clock cycles, or when to advance the synchronization output by one or more clock cycles. In this manner, it is possible to maintain synchronization between the devices.
The basic operation and connectivity of
At step 420, the first signal is provided to a first node. With reference to
Next, at step 430, a value associated with the first signal and the first output node is determined. With reference to
At step 440, a second signal is generated at a second graphics device. With reference to
At step 450, the second signal from stage 440 is provided to the first output node. In operation, this requires the controller 130 of
At step 460, an adjustment is made to the second VGA device until the value of the second signal, at the first output node, substantially matches the predetermined voltage reference value VREF. This corresponds to varying the ADJUST SIGNAL of
At a step 470, the steps 410 through 460 are repeated for different color components signals, and/or different VREF values.
As illustrated, the curve 601 is not necessarily a linear curve, because the analog output values of the DAC can vary over the DAC's range. Likewise, the curve 602 represents the analog value of the color component provided at the output from the second VGA 120 for the range of digital DAC values. Range 610 represents the difference between the curves 601 and 602 at a digital DAC value of 191. The value 191 represents 75% of the maximum DAC value of 255. In general, the signal difference 610 will be referenced in terms of a voltage value. By implementing the methods disclosed herein, the voltage difference 610 can be minimized.
One of ordinary skill in the art will recognize that by changing the voltage reference value, and allowing for multiple adjustments at various curve points, it would be possible to adjust for the other value such as 710 as well. In another implementation, the video-out controller 330 can provide information to a video palette which can be stored in video ram or within the VGAs 110 and 120. For example, a video palette associated with the VGA 120 can be stored in the Video Ram 122 or within the VGA 120. Such a palette provides the colors available for output by the DAC. By storing the palette colors in a piecewise manner, such as a piecewise linear representation, it is possible to adjust the actual color displayed based upon the desired brightness. This can be accomplished by making a coarse adjustment to minimize the voltage difference 610, as illustrated in
One way to adjust the palette members is to vary the voltage reference VREF illustrated in
The specific method of
The ADJUST CONTROL SIGNAL illustrated in
At a step 520, a third signal is generated by a second device, such as the second VGA 120. The third signal is also representative of the first color component signal, but for a second frame of video.
At step 530, the first signal is provided to a first port during a first time period. Next, at step 540, the third signal is provided to the first port during a second time period, where the second time period is sequentially adjacent in time to the first time period. Next, at step 550, the second signal is provided to the first port during a third time period, wherein the third time period is sequentially adjacent in time to the second time period. In effect, the steps 530, 540, and 550 provide a first frame of video from the first VGA 110 at the port 151, a second frame of video from the second VGA 120 to the port 151, and a third frame of video from the VGA 110 to the port 151.
In accordance with the present invention, the steps 510 through 550 are advantageous in that the workload distribution is approximately even because each VGA processes an entire frame of video, each frame of data is sent only one time to one VGA, each shape of a frame is calculated only once by one VGA, and there is no straddle data to burden down both processors. In addition, the voltage equalization as described within the method of
It should be further understood that the specific steps of
One of ordinary skill in the art will recognize that variations of the present invention may occur. For example, the present invention can be implemented for a specific color component, or for multiple color components. In addition, the gross color adjust described herein as being performed using the ADJUST SIGNAL from the Video Out Adjust 160, can be accomplished by modifying the video palette information associated with one or both of the first and second VGA 110 and 120. In addition, the functionality of controller 130 may be incorporated within either or both of adapters 110 and 120. In yet another embodiment, the functionality of Controller 130 can be implemented under software control of the system or one or both of the adapters 110 and 120.
Throughout this specification, the term “connected” has been used in order to indicate the relationship between blocks. It should be understood that while the term “connected” has been used, it would be equally appropriate to have the portions coupled together in that two portions coupled together may have intervening components.
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|U.S. Classification||345/502, 345/589, 345/504|
|International Classification||G09G5/06, G09G5/36, G09G5/02, G06F3/14, G09G5/399, G06F15/16|
|Cooperative Classification||G09G2340/12, G09G5/003, G09G2320/0271, G09G5/06, G09G5/399, G06F3/1438, G09G2360/18, G09G5/363, G09G2320/0233, G09G5/36, G09G2320/0693|
|Nov 30, 2009||AS||Assignment|
Owner name: ATI TECHNOLOGIES ULC, CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ATI INTERNATIONAL SRL;REEL/FRAME:023574/0593
Effective date: 20091118
Owner name: ATI TECHNOLOGIES ULC,CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ATI INTERNATIONAL SRL;REEL/FRAME:023574/0593
Effective date: 20091118
|Jan 18, 2011||CC||Certificate of correction|
|Mar 18, 2013||FPAY||Fee payment|
Year of fee payment: 4