US 7664915 B2 Abstract An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
Claims(24) 1. An apparatus comprising:
a first data processing path to receive a block of data, the first data processing path including a first accumulate buffer to store the block of data and a first arithmetic logical unit to perform a first operation on the block of data; and
a second data processing path to receive the block of data, the second data processing path including a second accumulate buffer to store the block of data and a second arithmetic logical unit to perform a second operation on the block of data, the first data processing path and the second data processing path sharing a multiplier, the multiplier to perform a multiply operation on the block of data, each of the data processing paths to process the block of data in parallel to provide a first result block of data and a second result block of data in a single pass of the block of data through the data processing paths, the first arithmetic logical unit has a first programmable polynomial and the second arithmetic logical unit has a second programmable polynomial.
2. The apparatus of
3. The apparatus of
4. The apparatus of
5. The apparatus of
6. The apparatus of
7. The apparatus of
8. The apparatus of
9. The apparatus of
10. The apparatus of
11. A method comprising:
storing a block of data in a first accumulate buffer in a first data processing path;
storing the block of data in a second accumulate buffer in a second processing path, the first processing path and the second processing path sharing a multiplier;
performing, by a first arithmetic logical unit a first operation on the block of data; and
performing, by a second arithmetic logical unit a second operation on the block of data, the first data processing path and the second data processing path processing the block of data in parallel to provide a first result block of data and a second result block of data in a single pass of the block of data through the data processing paths the first arithmetic logical unit has a first programmable polynomial and the second arithmetic logical unit has a second programmable polynomial.
12. The method of
13. The method of
14. The method of
15. The method of
16. The method of
17. The method of
18. The method of
19. The method of
20. The method of
21. An article including a machine-accessible storage medium having associated information, wherein the information, when accessed, results in a machine performing:
storing a block of data in a first accumulate buffer in a first data processing path;
storing the block of data in a second accumulate buffer in a second processing path, the first processing path and the second processing path sharing a multiplier;
performing, by a first arithmetic logical unit a first operation on the block of data; and
performing, by a second arithmetic logical unit a second operation on the block of data, the first data processing path and the second data processing path processing the block of data in parallel to provide a first result block of data and a second result block of data in a single pass of the block of data through the data processing paths, the first arithmetic logical unit has a first programmable polynomial and the second arithmetic logical unit has a second programmable polynomial.
22. The article of
23. A system comprising:
a redundant array of independent disks (RAID) system having a plurality of Serial Attached Small Computer System Interface (SAS) disk drives; and
an acceleration unit to process data for the RAID system, the acceleration unit comprising:
a first data processing path to receive a block of data, the first data processing path including a first accumulate buffer to store the block of data and a first arithmetic logical unit to perform a first operation on the block of data; and
a second data processing path to receive the block of data, the second data processing path including a second accumulate buffer to store the block of data and a second arithmetic logical unit to perform a second operation on the block of data, the first data processing path and the second data processing path sharing a multiplier, the multiplier to perform a multiply operation on the block of data, each of the data processing paths to process the block of data in parallel to provide a first result block of data and a second result block of data in a single pass of the block of data through the data processing paths.
24. The system of
Description This disclosure relates to redundant array of independent disks (RAID) systems and in particular to acceleration of computations for a RAID-6 system. A Redundant Array of Independent Disks (RAID) combines a plurality of physical hard disk drives into a logical drive for purposes of reliability, capacity, or performance. Thus, instead of multiple physical hard disk drives, an operating system sees the single logical drive. As is well known to those skilled in the art, there are many standard methods referred to as RAID levels for distributing data across the physical hard disk drives in a RAID system. For example, in a level 0 RAID system the data is striped across a physical array of hard disk drives by breaking the data into blocks and writing each block to a separate hard disk drive. Input/Output (I/O) performance is improved by spreading the load across many hard disk drives. Although a level 0 RAID improves I/O performance, it does not provide redundancy because if one hard disk drive fails, all of the data is lost A level 5 RAID system provides a high level of redundancy by striping both data and parity information across at least three hard disk drives. Data striping is combined with distributed parity to provide a recovery path in case of failure. A level 6 RAID system provides an even higher level of redundancy than a level 5 RAID system by allowing recovery from double disk failures. In a level 6 RAID system, two syndromes referred to as the P syndrome and the Q syndrome are generated for the data and stored on hard disk drives in the RAID system. The P syndrome is generated by simply computing parity information for the data in a stripe (data blocks (strips), P syndrome block and Q syndrome block). The generation of the Q syndrome requires Galois Field multiplications and is complex in the event of a disk drive failure. The regeneration scheme to recover data and/or P and/or Q syndromes performed during disk recovery operations requires both Galois multiplication and inverse operations. The regeneration is typically performed using lookup tables for computation or through the use of a plurality of Galois-field multipliers which are limited to a specific polynomial. Features of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, in which like numerals depict like parts, and in which: Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims. The P syndrome may be generated by performing an exclusive OR (XOR) operation. XOR is a logical operation on two operands that results in a logical value of ‘1’, if only one of the operands has a logical value of ‘1’. For example, the XOR of a first operand having a value ‘11001010’ and a second operand having a value ‘10000011’ provides a result having a value ‘01001001’. If the hard drive that stores the first operand fails, the first operand may be recovered by performing an XOR operation on the second operand and the result. The P syndrome is the simple parity of data (D) computed across a stripe using ⊕(XOR) operations. In a system with n data disks, the generation of the P syndrome is represented by equation 1 below:
The computation of the Q syndrome requires multiplication (*) using a Galois Field polynomial (g). Arithmetic operations are performed on 8-bit (byte) Galois-field polynomials at very high performance. A polynomial is an expression in which a finite number of constants and variables are combined using only addition, subtraction, multiplication and non-negative whole number exponents. One primitive polynomial is x Byte-wise Galois-field operations are performed on a stripe basis, where each byte in the block is computationally independent from the other bytes. Byte-wise Galois-Field operations can accommodate as many as 255 (2^8−1) data disks. The system includes a memory In one embodiment the state machine The memory The acceleration unit In an embodiment, each ALU In an embodiment, each ALU The data processing unit Both data processing paths share multiplier The acceleration unit The data processing unit Multiplexer Multiplexer Multiplexers The 64-bit XOR The configuration registers The configuration register The source field The accumulate field The calculation mode field
XOR operations for modes 100, 101, 110 and 111 are performed by the 64-bit XOR The configuration register The multiplier coefficient field The GF polynomial field The acceleration unit Special multiplexer paths discussed in conjunction with The multiple paths also reduce wasteful multi-pass of data, that is, passing the same data from shared memory The acceleration unit In one embodiment, the acceleration unit As discussed previously, the P syndrome is computed by performing an XOR operation on the data blocks in the stripe to be stored across n data disk drives and is represented by equation 1 below:
Referring to The full-stripe Q syndrome may be calculated using factorization. Each coefficient g In an embodiment of the invention, the P and Q syndromes are computed on the same data in parallel. With both computations performed in a single-pass of the data through the acceleration unit As previously discussed, the P and Q syndromes are computed for data blocks in a stripe across a plurality of hard disks. In one embodiment, each block of data (strip) in the stripe may store 512 bytes. At block The respective acceleration unit configuration register In one embodiment an instruction to load the acceleration unit configuration register At block At block ALU ALU At block For example, to compute the P syndrome, an XOR operation is performed in ALU At block At block At block At block At block The (Dold⊕Dnew) expression is used in both equation 3 and equation 4 to compute the new P syndrome and the new Q syndrome. Thus, this expression may be computed once for Pnew and then used to compute Qnew. The acceleration unit At block At block At block ALU ALU At block At block The fields in configuration register At block At block At block At block At block Typically, D However, this requires two passes of the data. As shown above, both D Using the data processing unit D At block At block At block At block At block The configuration register At block Processing continues with block At block Processing continues with block At block The result is stored in accumulate buffer At block In addition to the methods for performing recovery from a double disk failure, partial P and Q update and computation of P and Q syndrome described in conjunction with The acceleration unit may be used to accelerate data processing operations other than those involving recovery of P, Q and data disks and computation of P and Q syndromes for a RAID-6 system. At block At block At block At block At block At block At block In another embodiment, the ALU in one data processing path may be configured to perform a result non-zero check and the ALU in the other data processing path configured to perform a compare check. The two operations may be performed in parallel on the same block of data. Enhanced Byte-search functions are useful in Public Key Cryptography Systems (PKCS) and Random Number Generators (RNG), for example, to search for Zero bytes or to find a variable pattern at the start of a message of the form 0*0x01*. In the latter case, the position of the variable pattern indicates the start of a well-formed message body. The search for the start of the well formed message body is very slow and requires a large amount of code space when performed in the micro engine The system The Host Central Processing Unit (CPU) The memory The ICH The ICH There are many serial storage protocol suites such as, Serial Attached Small Computer System Interface (SAS) and Serial Advanced Technology Attachment (SATA). A version of the SATA protocol is described in “Serial ATA: High Speed Serialized AT Attachment,” Revision 1.0a, published on Jan. 7, 2003 by the Serial ATA Working Group. A version of the SAS protocol is described in “Information Technology—Serial Attached SCSI—1.1,” Working Draft American National Standard of International Committee For Information Technology Standards (INCITS) T10 Technical Committee, Project T10/1562-D, Revision 1, published Sep. 18, 2003, by American National Standards Institute (ANSI). A version of the Fibre Channel (FC) protocol is described in the American National Standards Institute (ANSI) Standard Fibre Channel Physical and Signaling Interface-2 (FC-FS-2) Aug. 9, 2005 Specification. It will be apparent to those of ordinary skill in the art that methods involved in embodiments of the present invention may be embodied in a computer program product that includes a computer usable medium. For example, such a computer usable medium may consist of a read only memory device, such as a Compact Disk Read Only Memory (CD ROM) disk or conventional ROM devices, or a computer diskette, having a computer readable program code stored thereon. While embodiments of the invention have been particularly shown and described with references to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of embodiments of the invention encompassed by the appended claims. Patent Citations
Non-Patent Citations
Referenced by
Classifications
Legal Events
Rotate |