US 7683810 B2 Abstract In accordance with one or more embodiments data may be encoded into a code word that meets run length constraints and has a reduced running digital sum by encoding (N−y)−1 data bits and y flag bits into m first n-bit patterns that form a first N-bit code word, producing a second N-bit code word by encoding the (N−y)−1 data bits and the y flag bits into m second n-bit patterns in which corresponding first and second n-bit patterns combine to meet a first predetermined running digital sum threshold, and selecting the code word that satisfies selection criteria. The selection criteria may, for example, be the word with the fewest transitions, the word with the smallest running digital sum, and so forth.
Claims(22) 1. A method including the steps of:
producing a first N-bit code word by encoding (N−y)−1 data bits and y flag bits into first m n-bit patterns;
producing a second N-bit code word by encoding the (N−y)−1 data bits and the y flag bits into second m n-bit patterns in which corresponding first and second n-bit patterns combine to meet a first predetermined running digital sum threshold;
selecting one of the first N-bit code word and the second N-bit code word that satisfies selection criteria.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
^{y}−1 additional N-bit code words by encoding the (N−y)−1 data bits and y flag bits into 2^{y}−1 respective additional m n-bit patterns in which corresponding n-bit patterns from the first code word and respective additional code words combine to meet a first predetermined running digital sum threshold.8. The method of
9. The method of
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
15. An encoding system comprising
a first encoder for encoding (N−y)−1 data bits and y flag bits to produce first N-bit code word that consists of first m n-bit patterns;
a second encoder for encoding the (N−y)−1 data bits and y flag bits to produce a second N-bit code word that consists of second m n-bit patterns that are companions of corresponding first n-bit patterns, the respective patterns and companions having running-digital-sum absolute values that added together meet a first predetermined running digital sum threshold; and
a selector for selecting one of the first N-bit code word and the second N-bit code word that satisfies selection criteria.
16. The system of
17. The system of
_{1})−1 bits into m n_{1}-bit constrained segments and concatenating the constrained segments with m segments of n_{2 }unconstrained data bits.18. The system of
19. The system of
_{1}-bit constrained pattern in a multiple stage encoder that in each stage maps constrained segments and appended user bits to pairs of constrained segments.20. The system of
a segment decoder that segments the N-bit codeword into n-bit segments,
a data modifier that modifies the n-bit segments if one or more included flag bits are set to states other than a first state, and
a decoder that decodes N bits to (N−y)−1 bits.
21. The system of
maps the n-bit patterns to n
_{1}-bit constrained segments and n_{2}-bits of user data,in multiple stages maps the constrained segments to user bits and smaller constrained segments, and
in a last stage maps a constrained segment to user bits.
22. An encoding system comprising
a first encoder for encoding (N−y)−1 data bits and y flag bits to produce a first N-bit code word that consists of first m n-bit patterns that meet run length constraints and a running digital sum threshold;
a second encoder for encoding the (N−y)−1 data bits and y flag bits to produce a second N-bit code word that consists of second m n-bit patterns that are companions of corresponding first n-bit patterns, the respective patterns and companions having running-digital-sum absolute values that added together meet a companion running digital sum constraint;
2
^{y}−1 additional encoders that respectively encode the (N−y)−1 data bits and the y flag bits to produce 2^{y}−1 additional N-bit code words with respective code words including m next n-bit patterns that are companions of corresponding first n-bit patterns, the respective patterns and companions having running-digital-sum absolute values that added together meet a companion running digital sum constraint; anda selector for selecting one of the first N-bit code word, second N-bit code word and additional N-bit code words that satisfies selection criteria.
Description The invention relates generally to encoding using codes that satisfy run-digital-sum and run length limited conditions. Before recording or transmission, data are typically encoded in accordance with a modulation code, to modify bit patterns in the data that may adversely affect the demodulation and decoding of the data. Certain bit patterns, for example, long runs without transitions, may adversely affect timing recovery, while other patterns may affect signal to noise ratios, and so forth. Accordingly, the modulation codes generally include run length constraints, and are often also referred to as run length limited (RLL) codes. High rate codes, that is, codes that produce a code word with a small increase in overall bit count, are desirable for their efficiency. To avoid adversely affecting the rate of transmission, it is desirable to encode long data sequences with high rate codes. However, there is a trade off between efficiency and the complexities associated with manipulating the large sequence of data bits into correspondingly wide code words. Further, code complexities may increase when ran length constraints must be considered. A system that efficiently encodes data using a high rate RLL code is described in U.S. Pat. No. 6,839,004, which is hereby incorporated herein in its entirety by reference. Low DC content is also important for perpendicular bipolar storage systems. Thus, it is also desirable to utilize a modulation code that produces code words that have relatively low running digital sum (RDS) values. The RDS values are the sums produced by adding together the +1 and −1 values that correspond to the ones and zeros in the code words. Further, it is desirable to keep the overall number of magnetic transitions low, in order to avoid adversely affecting the signal to noise ratios. In accordance with one or more embodiments described herein data may be encoded into a code word that meets run length constraints and has a reduced running digital sum by encoding (N−y)−1 data bits and y flag bits into m first n-bit patterns that form a first N-bit code word, producing a second N-bit code word by encoding the (N−y)−1 data bits and the y flag bits into m second n-bit patterns in which corresponding first and second n-bit patterns combine to meet a first predetermined running digital sum threshold, producing, for y>1, a next N-bit code word by encoding the (N−y)−1 data bits and the y flag bits into m next n-bit patterns in which corresponding first and next n-bit patterns combine to meet a first predetermined running digital sum threshold, and so forth to generate 2 Also in accordance with one or more embodiments described herein, a system for encoding data into a code word that meets run length constraints and has a reduced running digital sum includes a first encoder that encodes (N−y)−1 data bits and y flag bits into a first N-bit code word with m first n bit patterns, a second encoder that encodes the (N−y)−1 data bits and the y flag bits into a second N-bit code word with m second n-bit patterns in which corresponding first and second n-bit patterns combine to meet a first predetermined running digital sum threshold, 2 The invention description below refers to the accompanying drawings, of which: Referring to There are particular n-bit patterns that cannot be used in the N-bit code word because of the run length constraints and the RDS threshold. For example, n-bit patterns with relatively high |RDS| values and any n-bit patterns that exceed the run length limits of k and j can be eliminated. Thus v n-bit patterns are eliminated, and the remaining n-bit patterns may be utilized for the encoding. The flag bits are included in the first n-bit segment to be encoded, and are set to a first predetermined state, for example, all zeros, for inclusion in the first code word. As discussed in more detail below, the flag bits are set during encoding and used for decoding. In the example, we will use a single flag for ease of explanation. However, multiple flags may be used, as is also discussed in more detail below. A second encoder In the example, the second encoder A selector With multiple flags, 2 Set forth below is an example in which N=480, y=1, m=40 and n=12. The 40 12-bit patterns form a 480-bit code word. The system encodes 479 user bits, which consist of 478 data bits and 1 flag bit, into the 480-bit code word and thus uses an N−1/N code. There are 4096 possible 12-bit patterns. Undesirable 12-bit patterns, that is, patterns that do not meet RLL constraints and/or an RDS threshold constraint must be eliminated. The constraints are: 1) The leading or trailing 9 bits of each 12-bit code word must not include 000000000 or 111111111, 2) The leading or trailing 9 bits of each 12-bit code word must not include 101010101 or 010101010, and 3) The |RDS| of each 12-bit pattern must be less than or equal to 8. There are 64 patterns that do not meet the conditions set forth above, and thus, 4032 12-bit patterns that meet the conditions. In accordance with the teachings of U.S. Pat. No. 6,839,004, which is incorporated herein by reference, the system encodes p bit segments into constrained segments that can be combined with 6-bit unconstrained segments to produce 12-bit words that can be mapped to the patterns that meet the three constraints. The code for the 6-bit segments is determined by selecting a value p such that 2 The encoding can produce 63*64=4032 different 12-bit segments, which can then be further encoded into or mapped one-to-one to the 4032 12-bit patterns that meet the run length and RDS constraints. The second encoder takes the 40 12-bit segments and modifies them by, in the example, combining each of them with a term or, as appropriate, one of a number of terms, determined to produce respective 12-bit companion patterns that satisfy the condition:
The encoding is now described in more detail. Referring to The segment encoder In general, the system generates m n Referring now to The second stage provides the 4-bit constrained segments through a multiplexer The 40 6-bit constrained segments are supplied to the segment encoder At the same time the 40 12-bit segments produced by the mapping encoder Referring now to A check processor The pattern masks are carefully selected such that all but a small number of masked words are the companions to the corresponding unmasked words. Accordingly, mapping is required for only the small number of words. Encoder A includes the first segment encoder The parameter R, which acts as the RDS threshold, may be user programmable, such that the decision between the first and second code word may be based more on the |RDS| value than the transition count or vice versa, depending on the environment in which the encoding system is to be used. As is understood by those skilled in the art, operations performed by the various processors and blocks described above with reference to The data modifier The decoding of code words in which multiple flags are used is performed in a similar manner, with the decoder using the modification and/or segment decoding steps that correspond to the states of the flags. Patent Citations
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