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Publication numberUS7687854 B2
Publication typeGrant
Application numberUS 10/876,729
Publication dateMar 30, 2010
Filing dateJun 28, 2004
Priority dateAug 19, 2003
Fee statusPaid
Also published asUS7919380, US20050040490, US20100144109
Publication number10876729, 876729, US 7687854 B2, US 7687854B2, US-B2-7687854, US7687854 B2, US7687854B2
InventorsNam Kyu Park
Original AssigneeMagnachip Semiconductor, Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Transistor in a semiconductor substrate having high-concentration source and drain region formed at the bottom of a trench adjacent to the gate electrode
US 7687854 B2
Abstract
The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Trenches are formed in a semiconductor substrate at gate edges. Low-concentration impurity regions are then formed at the sidewalls and the bottoms of the trenches. High-concentration impurity regions are formed at the bottoms of the trenches in a depth shallower than the low-concentration impurity regions. Source/drain consisting of the low-concentration impurity regions and the high-concentration impurity regions are thus formed. Therefore, the size of the transistor can be reduced while securing a stabilized operating characteristic even at high voltage. It is thus possible to improve reliability of the circuit and the degree of integration in the device.
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Claims(7)
1. A transistor in a semiconductor device, comprising:
a well formed by a first conductivity type impurity in an active region of a semiconductor substrate;
a low-concentration impurity region formed by a second conductivity type impurity on the active region;
a gate oxide film and a gate formed over a surface of the semiconductor substrate;
an isolation region formed in the semiconductor substrate;
a trench surrounded by the low-concentration impurity region;
dielectric film spacers formed on both sidewalls of the gate and the trench;
a high-concentration impurity region formed by the second conductivity type impurity at the bottom of the trench and the dielectric film spacers to form source/drain regions; and
a drift junction formed in a portion of a channel region in the well by a same dopant type of impurity as an impurity of the well,
wherein the high-concentration impurity region is formed to have a distance 1.0 μm to 2.0 μm, when the transistor stably operates at substantially 40 V, from a bottom surface of the gate oxide film in a vertical direction.
2. The transistor as claimed in claim 1, wherein the high-concentration impurity region is formed only at the trench in a self-aligned manner.
3. The transistor as claimed in claim 1, wherein the trench is formed between the gate and an adjacent isolation region.
4. The transistor as claimed in claim 1, further comprising:
an interlayer insulating film formed over the semiconductor substrate;
a contact plug formed on each a source/drain through the interlayer insulating film;
a metal wire formed on the interlayer insulating film including the contact plug.
5. The transistor as claimed in claim 1, wherein a height of a dielectric film spacer formed adjacent the gate is higher than a height of a dielectric film spacer formed adjacent the trench.
6. The transistor as claimed in claim 1, wherein a size (LVDMOS) of the transistor is formed to satisfy the following:
LVDMOS=2LDO+LGATE2, wherein LDO is a width for which the low-concentration impurity region and the gate are overlapped, and LGATE2 is a channel width.
7. The transistor as claimed in claim 1, wherein the trench has a width narrower than the low-concentration impurity region, and a depth of the trench is shallower than a depth of the low-concentration impurity region.
Description
BACKGROUND

1. Field of the Invention

The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, and more specifically, to a transistor in a semiconductor device having a VDMOS (Vertical Diffused MOS) structure suitable for a high-voltage operation, and method of manufacturing the same.

2. Discussion of Related Art

A transistor used in a high-voltage device is fabricated in a structure different from a common transistor. For example, a transistor is manufactured to have an EDMOS (Extended Drain MOS) or LDMOS (Lateral Diffused MOS) structure so that the transistor can operate stably at high voltage. Of them, a transistor of the LDMOS structure (hereinafter, referred to as “LDMOS transistor”) will be described.

FIG. 1 is a cross-sectional view for explaining the structure of a transistor in a semiconductor device in the related art.

Referring to FIG. 1, a LDMOS transistor includes a gate oxide film 104, a gate 105, dielectric film spacers 106 formed at the sidewalls of the gate 105, a source 107 and a drain 108. At this time, the source 107 has a low-concentration impurity region 107 a and a high-concentration impurity region 107 b, and the drain 108 has a low-concentration impurity region 108 a and a high-concentration impurity region 108 b. Unexplained reference numeral 102 indicates a well, 103 designates an isolation film and 109 indicates a well junction.

In the above, assuming that the size (LLDMOS) of the LDMOS transistor is from the edge of the high-concentration impurity region 107 b included in the source 107 to the edge of the high-concentration impurity region 108 b included in the drain 108, the size (LLDMOS) of the LDMOS transistor can be expressed into the following Equation 1.
L LDMOS=2L D+2L DO +L GATE1  Equation 1
where LD is a width from the edge of the high-concentration impurity region to the edge of the gate.

  • LDO is a width that the low-concentration impurity region and the gate are overlapped.
  • LGATE1 is a channel width.

In the above, in order for the LDMOS transistor to stably operate even at high voltage, the low-concentration impurity regions 107 a and 108 a have to be extended in the horizontal direction. Thus, the size of the transistor is increased. For example, in order for the LDMOS transistor to stably operate even at about 40V, it is required that LD be at least 1.5 μm and LGATE1 be at least 3 μm. At this time, assuming that LDO is 0.5 μm, the size of the LDMOS transistor becomes 7 μm.

If the channel width LGATE1 is reduced, the size of the LDMOS transistor can be reduced but the electrical properties of the transistor can be degraded due to a short channel effect.

For this reason, it is difficult to apply the conventional LDMOS transistor to a high-integration circuit. In particular, there is a problem that the conventional LDMOS transistor is difficult to implement SOC (System On Chip).

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a transistor in a semiconductor device and method of manufacturing the same, wherein trenches are formed in a semiconductor substrate at the edges of a gate, low-concentration impurity regions are formed at the sidewalls and the bottoms of the trenches, high-concentration impurity regions are formed at the bottoms of the trenches in a depth shallower than the low-concentration impurity regions, and source/drain consisting of the low-concentration impurity regions and the high-concentration impurity regions are thereby formed, thus reducing the size of the transistor while securing a stabilized operating characteristic even at high voltage and improving reliability of the circuit and the degree of integration in the device.

In order to accomplish the object, according to an aspect of the present invention, there is provided a transistor in a semiconductor device, comprising a gate oxide film formed at a given region of a semiconductor substrate, a gate formed on the gate oxide film, trenches formed in both side edges of the gate, and source/drain formed at the sidewalls and the bottoms of the trenches.

In the above, the transistor may further comprise dielectric film spacers formed at the sidewalls of the gate. The dielectric film spacers can be formed up to the sidewalls of the trenches.

The source/drain comprise low-concentration impurity regions formed at the sidewalls and the bottoms of the trenches, and high-concentration impurity regions formed at the bottoms of the trenches.

The transistor may further comprise a drift junction for controlling the threshold voltage, wherein the drift junction is formed in the semiconductor substrate under the gate.

According to a preferred embodiment of the present invention, there is provided a method of manufacturing a transistor in a semiconductor device, comprising the steps of providing a semiconductor substrate in which a well is formed in an active region and an isolation film is formed in an isolation region, forming low-concentration impurity regions in source/drain regions of the semiconductor substrate, forming trenches in the semiconductor substrate of the low-concentration impurity regions so that the trenches are adjacent to the isolation film, sequentially forming a gate oxide film and a gate on the semiconductor substrate between the trenches, and forming high-concentration impurity regions at the bottoms of the trenches to form source/drain having the low-concentration impurity regions and the high-concentration impurity regions.

It is preferred that the trenches are formed in a depth shallower than the low-concentration impurity regions and are formed in a width narrower below 5 μm than the width of the low-concentration impurity region.

The method may further comprise the step of forming a drift junction for controlling the threshold voltage in the semiconductor substrate between the low-concentration impurity regions before the gate oxide film is formed.

The method may further comprise the step of before the high-concentration impurity regions are formed, forming an insulating film on the entire surface and then performing a blanket etch process to form dielectric film spacers at the sidewalls of the gate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view for explaining the structure of a transistor in a semiconductor device in the related art;

FIG. 2 is a cross-sectional view for explaining the structure of a transistor in a semiconductor device according to an embodiment of the present invention; and

FIG. 3A to FIG. 3F are cross-sectional views for explaining a method of manufacturing a transistor in a semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Now the preferred embodiments according to the present invention will be described with reference to the accompanying drawings. Since preferred embodiments are provided for the purpose that the ordinary skilled in the art are able to understand the present invention, they may be modified in various manners and the scope of the present invention is not limited by the preferred embodiments described later.

Meanwhile, in case where it is described that one film is “on” the other film or a semiconductor substrate, the one film may directly contact the other film or the semiconductor substrate. Or, a third film may be intervened between the one film and the other film or the semiconductor substrate. Further, in the drawing, the thickness and size of each layer are exaggerated for convenience of explanation and clarity. Like reference numerals are used to identify the same or similar parts.

FIG. 2 is a cross-sectional view for explaining the structure of a transistor in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, the transistor in the semiconductor device according to an embodiment of the present invention includes a gate oxide film 207 and a gate 208 which are sequentially stacked at a given region, trenches 206 formed at both side edges of the gate 208, and source and drain 211 a and 211 b formed at the sidewalls and the bottoms of the trenches 206.

In the above, each of the source and drain 211 a and 211 b has a structure including a low-concentration impurity region 204 formed at the sidewall and the bottom of the trench 206, and a high-concentration impurity region 210 formed only at the bottom of the trench 206.

Meanwhile, dielectric film spacers 209 are further formed at the sidewalls of the gate 208. The dielectric film spacers 209 can be formed up to both sidewalls of the trenches 206.

Furthermore, in order to control the threshold voltage of the transistor, a drift junction 205 can be further formed in the semiconductor substrate 201 under the gate 208. By providing the drift junction 205 such as a threshold voltage ion implantation layer, a channel width of the transistor can become further narrow. It is thus possible to improve the degree of integration in the device.

The size of the VDMOS transistor formed thus according to an embodiment of the present invention will now be compared with that of the conventional LDMOS transistor.

In the same manner that the size of the LDMOS transistor is defined in FIG. 1, assuming that the size (LVDMOS) of the VDMOS transistor is from the edge of the high-concentration impurity region 210 included in the source 211 a to the edge of the high-concentration impurity region 210 included in the drain 211 b, the size (LVDMOS) of the VDMOS transistor can be expressed into the following Equation 2.
L VDMOS =2L DO +L GATE2  Equation 2
where LDO is a width that the low-concentration impurity region and the gate are overlapped.

  • LGATE2 is a channel width.

Referring to Equation 2, in the VDMOS transistor according to an embodiment of the present invention, the high-concentration impurity region 210 and the gate 208 are adjacent in the horizontal direction and are spaced only in the vertical direction. A distance (LD) between the edge of the high-concentration impurity region and the edge of the gate does not affect the size of the VDMOS transistor.

In the above, a difference between the size of the conventional LDMOS transistor and the size of the VDMOS transistor according to the present invention will be compared with reference to Equation 1 and Equation 2. The difference (Δ) can be expressed into the following Equation 3.
Δ=2L D+(L GATE1 −L GATE2)  Equation 3

Referring to Equation 3, in order for the VDMOS transistor to stably operate even at about 40V, it is required that LD be a minimum of 1.5 μm like in the prior art. Also, LGATE2 becomes 2 μm that is narrower than in the LDMOS transistor by means of the drift junction 205. The difference (Δ) between the size of the conventional LDMOS transistor and the size of the VDMOS transistor according to the present invention is 4 μm. That is, the size of the VDMOS transistor according to the present invention can be further reduced by about 4 μm compared to the size of the conventional LDMOS transistor.

A method of manufacturing the VDMOS transistor formed above will now be described.

FIG. 3A to FIG. 3F are cross-sectional views for explaining a method of manufacturing a transistor in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, a well 202 is formed at an active region of a semiconductor substrate 201.

In the above, the well 202 can be formed in a region where an N channel transistor is to be formed, in a triple well structure consisting of a triple N well into which boron (B) is implanted and a P well into which phosphorus (P) is implanted. The well 202 can be formed in a region where a P channel transistor is to be formed using an N well into which phosphorous is implanted. As above, after the impurity is implanted, an annealing process is implemented so that secondary drive-in is realized.

Thereafter, in the active region, low-concentration impurity regions 204 are formed in regions where source and drain will be formed. At this time, if an N channel transistor is formed, arsenic (As) can be implanted to form the low-concentration impurity regions 204. If a P channel transistor is formed, BF2 can be implanted to form the low-concentration impurity regions 204. After the impurity is implanted, an annealing process is performed so that secondary drive-in is realized in order to form a vertically diffused source/drain.

Meanwhile, it has been shown in the drawing that the low-concentration impurity regions 204 are formed in all the regions where the source and drain will be formed. The low-concentration impurity regions 204, however, can be formed only in a region where the drain will be formed.

Next, in order to control the threshold voltage of the transistor, a drift junction 205 is formed in a portion of the channel region between the low-concentration impurity regions 204. In case of the N channel transistor, BF2 can be implanted to form the drift junction 205. In case of the P channel transistor, arsenic (As) can be implanted to form the drift junction 205. After the impurity is implanted as such, an annealing process is performed so that the secondary drive-in is accomplished, thus forming the drift junction 205 of a depth to the extent that the transistor can stably operate even at high voltage.

Thereafter, trenches are formed in an isolation region by means of a STI (Shallow Trench Isolation) process. The trenches are then filled with an insulating material, forming isolation films 203.

Referring to FIG. 3B, some regions of the low-concentration impurity regions 204 are etched to form trenches 206. At this time, it is preferred that the trenches 206 are formed in a depth shallower than the low-concentration impurity regions 204 and are close to the isolation films 203.

In the above, the trenches 206 are formed in a width narrower than the low-concentration impurity regions 204. It is preferable that the width at non-etched portions of the low-concentration impurity regions 204 is determined to be suitable for the operating voltage. For example, the trenches 206 are formed in a width narrower about 0.5 μm than the low-concentration impurity regions 204. The degree that a gate to be formed in a subsequent process and the low-concentration impurity regions 204 are overlapped on the surface of the semiconductor substrate 201 is preferably controlled below 0.5 μm. Meanwhile, the depth of the trench 206 can be determined considering the operating voltage and distribution of an electric field. If the operating voltage is about 40V, it is preferred that the depth of the trench 206 is set to 1 μm to 2 μm.

By reference to FIG. 3C, a gate oxide film 207 and a gate 208 are sequentially formed on the active region of the semiconductor substrate 201 in which the trench 206 is not formed. At this time, a thickness of the gate oxide film 207 is determined depending on the operating voltage. Meanwhile, the gate 208 may be formed using polysilicon and is overlapped with the low-concentration impurity regions 204 within about 5 μm.

Referring to FIG. 3D, after an insulating film is formed on the entire surface, a dry etch process is performed to form dielectric film spacers 209. In this case, it is preferred that the insulating film is formed using HLD (High Pressure Low temperature Decomposition) oxide. Meanwhile, since the dielectric film spacers 209 are formed with the trenches 206 formed, the dielectric film spacers 209 are formed even at the sidewalls of the trenches 206.

Referring to FIG. 3E, an impurity ion implantation process is performed at a concentration higher than the impurity implanted in order to form the low-concentration impurity regions 204, thereby forming high-concentration impurity regions 210. At this time, if an N channel transistor is formed, arsenic (As) can be implanted to form the high-concentration impurity regions 210. If a P channel transistor is formed, BF2 can be implanted to form the high-concentration impurity regions 210. After the impurity is formed, an annealing process is performed so that the implanted impurity is activated.

Meanwhile, the impurity ion implantation process of the high concentration is performed with the gate 208 and the bottoms of the trenches 206 exposed. Thus, the high-concentration impurity regions 210 are formed only at the bottoms of the trenches 206 in a self-aligned manner. The impurity of the high concentration is also implanted into the gate 208.

Thereby, source and drain 211 a and 211 b consisting of the low-concentration impurity regions 204 formed at the sidewalls and the bottoms of the trenches 206 and the high-concentration impurity regions 210 formed only at the bottoms of the trenches 206 are formed.

Through the above process, the VDMOS transistor according to an embodiment of the present invention is manufactured.

By reference to FIG. 3F, an interlayer insulating film 212 is formed on the entire surface. A contact hole is then formed in the interlayer insulating film 212 by means of an etch process so that the junction of the semiconductor substrate 201 including the source/drain 211 a and 211 b is exposed. After the contact hole is filled with a conductive material to form contact plugs 213, a metal wire 214 of a given pattern is formed on the interlayer insulating film 212 including the contact plugs 213. At this time, the contact plugs can be formed using a conductive material such as polysilicon or tungsten.

The VDMOS transistor formed through the aforementioned method will now be examined. There is an effect that an electric field is distributed between the low-concentration impurity regions 204 formed in the vertical direction and the contact plugs 213 formed on the drain 211 b. If the low-concentration impurity regions 204 formed in the vertical direction do not exist, there will a problem that a voltage applied to the drain 211 b is concentrated on the edges of the high-concentration impurity regions 210 and the low-concentration impurity regions 204 on the horizontal line.

Furthermore, if the gate 208 is formed on the horizontal line not the VDMOS structure, an electric field is applied between the corners of the low-concentration impurity regions 204 and the edges of the gate 208. As a gate oxide film breakdown occurs at a very low voltage, it is not suitable for the object of a high voltage.

Furthermore, the vertically diffused drift junction 205 becomes a resisting body having distributed resistance due to a low doping concentration, thus help a high-voltage operation while serving to lower the voltage applied to the drain.

According to the present invention described above, trenches are formed in a semiconductor substrate of gate edges. Low-concentration impurity regions are formed at the sidewalls and the bottoms of the trenches. High-concentration impurity regions are formed at the bottoms of the trenches in a depth shallower than the low-concentration impurity regions. Source/drain consisting of the low-concentration impurity regions and the high-concentration impurity regions are thus formed. Therefore, the size of the transistor can be reduced while securing a stabilized operating characteristic even at high voltage. It is thus possible to improve reliability of the circuit and the degree of integration in the device.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4866492 *Sep 30, 1988Sep 12, 1989Polyfet Rf Devices, Inc.Vertical and lateral diffusion devices; low-resistance conductive layer connecting the source structure to a truncated source extersion underlying a dielectric gate and connecting to a channel region
US4963504 *Nov 24, 1989Oct 16, 1990Xerox CorporationMethod for fabricating double implanted LDD transistor self-aligned with gate
US5403763 *Feb 9, 1994Apr 4, 1995Semiconductor Energy Laboratory Co., Ltd.Method of manufacturing a vertical channel FET
US5484743 *Feb 27, 1995Jan 16, 1996United Microelectronics CorporationSelf-aligned anti-punchthrough implantation process
US5538909 *Jan 19, 1995Jul 23, 1996United Microelectronics CorporationMethod of making a shallow trench large-angle-tilt implanted drain device
US5693542 *Nov 9, 1995Dec 2, 1997Hyundai Electronics Industries Co., Ltd.Method for forming a transistor with a trench
US5798291 *Apr 1, 1997Aug 25, 1998Lg Semicon Co., Ltd.Method of making a semiconductor device with recessed source and drain
US5828103 *Dec 26, 1995Oct 27, 1998United Microelectronicws Corp.Recessed lightly doped drain (LDD) for higher performance MOSFET
US5834793 *Jul 23, 1996Nov 10, 1998Kabushiki Kaisha ToshibaSemiconductor devices
US5981343 *Oct 15, 1997Nov 9, 1999Sgs-Thomas Microelectronics, S.R.L.Single feature size mos technology power device
US5981998 *Oct 29, 1996Nov 9, 1999Sgs-Thomson Microelectronics S.R.L.Single feature size MOS technology power device
US6110786 *Apr 16, 1998Aug 29, 2000Advanced Micro Devices, Inc.Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof
US6198129 *Nov 4, 1999Mar 6, 2001Oki Electric Industry Co., Ltd.Vertical type insulated gate transistor
US6531347 *Feb 6, 2001Mar 11, 2003Advanced Micro Devices, Inc.Method of making recessed source drains to reduce fringing capacitance
US6656764 *May 15, 2002Dec 2, 2003Taiwan Semiconductor Manufacturing CompanyProcess for integration of a high dielectric constant gate insulator layer in a CMOS device
US6897570 *Jan 9, 2003May 24, 2005Renesas Technology, CorporationSemiconductor device and method of manufacturing same
US6906381 *Jun 8, 2001Jun 14, 2005Freescale Semiconductor, Inc.Lateral semiconductor device with low on-resistance and method of making the same
US20020045304 *Oct 3, 2001Apr 18, 2002Chien-Hsing LeeFabrication method and structure of flash memory device
US20060286757 *Jun 15, 2005Dec 21, 2006John PowerSemiconductor product and method for forming a semiconductor product
JPH025436A Title not available
JPH03156976A * Title not available
JPH06163572A * Title not available
Classifications
U.S. Classification257/344, 257/336, 257/408, 257/E29.267
International ClassificationH01L29/10, H01L21/335, H01L29/00, H01L21/336, H01L29/78
Cooperative ClassificationH01L29/7834, H01L29/1083, H01L29/66613
European ClassificationH01L29/66M6T6F11D, H01L29/10F2B2, H01L29/78F2
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