|Publication number||US7701008 B2|
|Application number||US 11/446,890|
|Publication date||Apr 20, 2010|
|Filing date||Jun 5, 2006|
|Priority date||Apr 29, 2003|
|Also published as||CN1309033C, CN1542930A, CN2726117Y, US7074656, US8053839, US8790970, US20040217433, US20060220133, US20060234431, US20100176424|
|Publication number||11446890, 446890, US 7701008 B2, US 7701008B2, US-B2-7701008, US7701008 B2, US7701008B2|
|Inventors||Yee-Chia Yeo, Ping-Wei Wang, Hao-Yu Chen, Fu-Liang Yang, Chenming Hu|
|Original Assignee||Taiwan Semiconductor Manufacturing Company, Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (93), Non-Patent Citations (27), Referenced by (11), Classifications (14), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of patent application Ser. No. 10/425,156, entitled “Doping of Semiconductor Fin Devices,” filed on Apr. 29, 2003, now U.S. Pat. No. 7,074,656 which application is incorporated herein by reference.
The present invention relates to semiconductor devices and more particularly to semiconductor devices with fin structures and methods for doping semiconductor fin devices.
The dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits is the metal-oxide-semiconductor field effect transistor (MOSFET) technology. Reduction in the size of MOSFETs has provided continued improvement in speed performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increasingly interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel.
Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-50 nm regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles become increasingly difficult to meet when conventional device structures based on bulk silicon (Si) substrates are employed. Innovations in front-end process technologies or the introduction of alternative device structures may be needed to sustain the historical pace of device scaling.
For device scaling well into the sub-30-nm regime, a promising approach to controlling short-channel effects is to use an alternative transistor structure with more than one gate, i.e., multiple-gates. An example of the alternative transistor structure is the multiple-gate transistor. Examples of the multiple-gate transistor include the double-gate transistor, triple-gate transistor, omega field-effect transistor (FET), and the surround-gate or wrap-around gate transistor. A multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET and realize the ultimate limit of silicon MOSFETs. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps suppress short channel effects, and prolongs the scalability of the MOS transistor.
The simplest example of a multiple-gate transistor is the double-gate transistor, as described in U.S. Pat. No. 6,413,802 ('802) issued to Hu, et al. and incorporated herein by reference. In the '802 patent, the transistor channel comprises a thin silicon fin defined using an etchant mask and formed on an insulator layer, e.g., silicon oxide. Gate oxidation is performed, followed by gate deposition and gate patterning to form a double-gate structure overlying the sides of the fin. Both the source-to-drain direction and the gate-to-gate direction are in the plane of the substrate surface.
The preferred embodiment of the present invention provides several methods for doping the semiconductor fin in a multiple-gate transistor to provide improved performance. In embodiments of the invention, the channel length is more uniformly doped than in certain prior art implementation thereby improving performance.
A first embodiment provides a method of doping semiconductor fins of multiple-gate transistors. A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (greater than 7″) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
A second embodiment provides a method to dope semiconductor fins with a different orientation. In this embodiment, a first mask covers the second semiconductor fin while the first semiconductor fin is doped by implanting dopant ions with a large implant angle. Similarly, a second mask covers the first semiconductor fin while the second semiconductor fin is doped by implanting the dopant ions with a large implant angle.
The present invention also includes structure embodiments. For example, semiconductor-on-insulator chip includes a plurality of multiple-gate transistors formed on an insulator layer. Each multiple-gate transistor includes a semiconductor fin having an orientation a gate electrode having a gate length of less than 30 nm. The orientation of each transistor of the plurality of multiple-gate transistors is the same. Other methods and structures are also taught.
A semiconductor-on-insulator chip comprising of a plurality of multiple-gate transistors formed on an insulator layer, each multiple-gate transistor comprising of a semiconductor fin having an orientation and a gate electrode having a gate length equal to the minimum feature size, said orientations of the plurality of multiple-gate transistors being the same.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
The preferred embodiment of the present invention relates to the field of semiconductor devices and more particularly to semiconductor devices with a fin structure. The present invention provides several methods for doping the semiconductor fin in a multiple-gate transistor.
Another example of the multiple-gate transistor is the triple-gate transistor 102. The cross-section of the triple-gate transistor structure 102 is illustrated in
The triple-gate transistor structure may be modified for improved gate control, as illustrated in
The omega-FET is therefore a field effect transistor with a gate 110 that almost wraps around the body 112. In fact, the longer the gate extension 130, i.e., the greater the extent of the encroachment E, the more the structure approaches or resembles the gate-all-around structure. A three-dimensional perspective of the triple-gate transistor with recessed insulator, or omega-FET, is schematically illustrated in
Another multiple-gate device that can utilize aspects of the present invention is the surround-gate of wrap-around gate transistor mentioned above. Examples of these deices are taught in the following references, each of which is incorporated herein by reference: J. P. Colinge, et al., silicon-on-insulator gate-all-around device,” International Electron Device Meeting, Dig. Technical Papers, pp. 595-598, December 1990; U.S. Pat. No. 6,391,782, B. Yu, Advanced Micro Devices, Inc., May 21, 2002, “Process for forming multiple active lines and gate-all-around MOSFET; E. Leobandung, et al., “Wire-Channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects,” J. Vacuum Science and Technology B, vol. 15, no. 6, pp. 2791-2794, 1997; and U.S. Pat. No. 6,451,656, B. Yu, et al., Advanced Micro Devices, Inc., Sep. 17, 2002, “CMOS inveter configured from double gate MOSFET and method of fabricating same.”
The multiple-gate transistor structures described, i.e., the double-gate transistor 100, the triple-gate transistor 102, and the omega-FET 104, have a common feature: the fin-like semiconductor active region 112. In doping the source and drain regions 126 and 128 of the semiconductor fin, prior art uses a conventional source and drain ion implantation process where ions are implanted at a small angle with respect to the normal of the wafer or the substrate. In conventional source and drain implantation, a small angle of 7 degrees or less is frequently used, as shown in
Using such an ion implantation condition results in most of the implanted dopants reaching the top surface 124 of the fin 112, giving a high-doped top surface region 132. Few dopants are effectively implanted into the sidewall surface 114, resulting in a lightly doped sidewall surface region 134. A long implantation time may be needed to introduce a significant amount of doping in the sidewall source/drain regions 126/128. In addition, since less dopants reach the bottom portion of the fin, the source and drain doping at the bottom portion of the fin will be lower, and may result in a larger channel length at the bottom portion of the fin than at the top portion of the fin.
Embodiments of the present invention can be implemented using any of a number of multiple gate transistors. Three examples of these transistors are described with respect to
Examples of double-gate transistors are provided in the following references, each of which is incorporated herein by reference. As will become clear from the teachings below, the structures disclosed in these references can be modified and/or utilize the methods of the present invention.
Multiple-gate transistors such as the double-gate transistor, the triple-gate transistor, the omega-FET, have a common feature: the semiconductor fin-like active region. Therefore, such devices are also known as semiconductor fin devices. The semiconductor fin has a predetermined fin height h and a predetermined fin width w. Another common feature of multiple-gate transistors is that the sidewall surfaces of the semiconductor fins are used for current conduction, i.e., a significant amount of source-to-drain current in the multiple-gate transistor is carried along the sidewall surfaces.
Essentially, the effective device width of the multiple-gate transistor is a function of the fin height h (see
According to this aspect of the invention, the implant angle α for the source and drain doping of the semiconductor fin device is large to optimize the device performance. Referring now to
In the preferred embodiment, the semiconductor fin 112 is formed from silicon, and the implanted ions are p-type dopant ions such as boron and/or indium or n-type dopant ions such as phosphorus, arsenic, and/or antimony. In the first implant step, as shown in
At the point of incidence at the top fin surface 124, the ions approach the top surface 124 at an angle α with respect to the normal of the top fin surface. The normal of the top fin surface is typically parallel to the normal of the wafer. At the point of incidence to the fin sidewall surface 114, the ions approach the sidewall surface 114 at an angle of (90-α) degrees with respect to the normal of the fin sidewall surface. The angles of α and (90-α) are measured in the plane perpendicular to the plane of the sidewall surface 114.
In the first implant step, the fin's first sidewall surface 114 received a dose of about (I/2).sin(α), the fin's top surface 124 received a dose of about (I/2).cos(α), and the fin's second sidewall surface 115 received essentially no dopants.
In the second implant step, the device 102 is rotated 180 degrees about its normal and the second half dose is implanted at an angle α with respect to the normal of the wafer in the z-x plane, as shown in
In the embodiment illustrated in
The preferred embodiment of this invention teaches that the implant angle should be large for the sidewall surfaces 114 and 115 to receive a substantial amount of doping. In fact, the implant angle is as large as 60 degrees for the top and sidewall surfaces of the fin 112 to have comparable doses, resulting in comparable doping concentrations.
Referring now to
According to the teaching of this invention, a large implant angle α has a number of advantages. First, a large angle implant can introduce more dopants more efficiently in the source and drain regions 126 and 128 on the sidewall surfaces of the transistor. As a result, the use of a small angle implant with long implantation time can be avoided. Second, a large angle implant will dope the top surfaces 124 and the sidewall surfaces 114 and 115 of the source and drain regions in the fin more equally. As a result, the channel length of the multiple-gate transistor is maintained the same whether at the top portion of the fin or at the bottom portion of the fin.
However, potential problems arise in the use of large angle implants, and solutions to these problems will be provided according to aspects of the present invention. Referring now to
The orientations of the gate electrodes 10 a and 10 b of the two transistors are also perpendicular to each other. It is understood that the two transistors may be in close proximity to each other, as illustrated in
The gate dielectric layer may be comprised of silicon oxide or silicon oxynitride. The gate dielectric layer may also comprise high permittivity dielectrics such as lanthalum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), or combinations thereof. High permittivity dielectrics typically have a relative permittivity of greater than 5. The gate electrode may be comprised of a conductive material. Examples of conductive materials are doped poly-crystalline silicon, doped poly-crystalline silicon-germanium, a metal, or a metal silicide. At this point, before the formation of the source and drain regions 126 and 128, the channel region 136 in the semiconductor fin 112 may be undoped or doped.
The subsequent fabrication process step may involve the formation of the source region 126 and drain region 128 by doping appropriate portions of the semiconductor fin 112. If a large angle implant with an angle α in the z-x plane is used to dope the first sidewall 114 a of the semiconductor fin of the first transistor 102 a, the channel region 136 b of the second transistor 102 b will also receive the source and drain dopants, causing degradation to the performance of the second transistor 102 b. The same problem occurs when using a large angle implant to dope the second sidewall 115 a of the first transistor 102 a.
In general, the large angle implant steps, while providing efficient doping of the source and drain regions of transistors with a first source-to-drain orientation, e.g., source-to-drain direction in y-direction, will also dope the channel region of the transistors with a second perpendicular source-to-drain orientation, e.g., source-to-drain direction in x-direction, with the same source/drain dopants. This is because a source and drain implant 140 with a large implant angle α such as 30 degrees has an implant angle similar to that of a halo implant and can therefore dope the channel region 136 b of the second transistor. Standard conventional halo implants, however, dope the channel region 136 with dopants of the opposite type to the source 126 and drain 128 dopants in order to control short channel effects. When the channel region 136 b of the second transistor 102 b is doped with the dopants intended for the source and drain regions 126 a and 128 a, the second transistor 102 b will have degraded short-channel behavior and may even fail due to an electrical short between the source and drain 126 b and 128 b.
According to aspects of this invention, a method is provided in which a large angle implant may be used to dope the source and drain regions 126 a and 128 a of the first transistor 102 a with a first source-to-drain orientation without doping the channel region 136 b of the second transistor 102 b with a second perpendicular source-to-drain orientation. Prior to the source and drain implant, a mask material 150 is deposited on the wafer to cover both the first and second transistors 102 a and 102 b. The mask material is patterned, e.g., by optical lithography, and the portion of the mask material 150 that covers the first transistor 102 a is removed to form a first mask 150, as shown in
The doping of the source and drain regions 126 a and 128 a may be performed in two implant steps, as described above, in which a half-dose angled implant is performed to dope the first sidewall 114 a and top surface 124 a of the fin 112 a of the first transistor 102 a followed by another half-dose angled implant to dope the second sidewall 115 a and top surfaces 124 a. Following the doping of the source and drain regions 126 a and 128 a, the first mask 150 may be removed.
Next, a second mask 152 is formed to expose the second transistor 102 b while covering the first transistor 102 a. An ion implantation including at least two steps is performed to dope the source and drain regions 126 a and 128 a of the second transistor 102 b. The channel region 136 a of the first transistor 102 a is shielded from this ion implantation process by the second mask 152. The implant angle of the ion implantation process to dope the source and drain regions 126 b and 128 b of the second transistor 102 b is oriented at an angle β in the z-y plane. The angle β is in the z-y plane which is perpendicular to the plane of the sidewall 114 b of the semiconductor fin 112 b of the second transistor. In
The second mask 152 may then be removed. A high temperature annealing step may be performed to activate the implanted dopants in the semiconductor fins 112 a and 112 b. The annealing step may be a spike anneal process in which the wafer temperature is rapidly increased to a peak temperature of 1050 degrees Celsius followed by a rapid cooling of the wafer temperature, or any other annealing techniques such as a rapid thermal anneal (RTA) commonly known and used in the art.
In the above-mentioned method embodiment, it is seen that the doping of source and drain regions 126 and 128 in transistors of the same type, e.g., n-type or n-channel, involves an additional mask patterning step. The introduction of an additional mask is sometimes costly and could be commercially prohibitive. Therefore, a further improvement over the above-mentioned embodiment is to align all multiple-gate transistors of the same type with a predetermined range of gate lengths in the same direction to permit the use of a large angle implant without the introduction of an additional mask. This is described in another embodiment of the present invention.
According to this embodiment, all multiple-gate transistors of the same conductivity type and with gate lengths less than or equal to a predetermined gate length are oriented in the same direction. In this context, all of transistors refers to all of the functional or operational transistors that are designed to operate with optimum characteristics. For example, this does not include dummy transistors or other transistors that do not operate in the circuits of the chip. The predetermined gate length is determined based on susceptibility to short-channel effects. Transistors with shorter gate lengths are more susceptible to short-channel effects. The predetermined gate length may be 30 nm, for example. In another example, the predetermined gate length may be the minimum gate length.
Since the large angle implant for doping the source and drain regions 126 and 128 of transistors of a first source-to-drain orientation degrade short-channel effects of transistors with other source-to-drain orientations, transistors susceptible to degradation of short-channel effects should all have the same source-to-drain direction. This means, for example, that all n-type multiple-gate transistors with gate lengths less than 30 nm have the source-to-drain direction oriented in the x-direction. This is illustrated in
It is understood, however, that transistor 102 c and transistor 102 d may have different electrical characteristics or vulnerability to short-channel effects depending on the ion implantation conditions used to dope their source and drain regions 126 and 128. The x-direction can be, for example, a crystallographic direction such as the  direction. In this case, the sidewall surfaces of the n-channel multiple-gate transistor are (100) surfaces. N-channel multiple-gate transistors with (100) sidewall surfaces are expected to have the best electron mobility. In another example, all p-type multiple-gate transistors with gate lengths less than 30 nm may have the source-to-drain direction oriented in the  crystallographic direction. In this case, the sidewall surfaces of the p-channel multiple-gate transistor are (110) surfaces. P-channel multiple-gate transistors with (110) sidewall surfaces is expected to have the best hole mobility.
In another method embodiment, the semiconductor fins 112 may be doped by solid-source diffusion instead of ion implantation as described in the other method embodiments. In the solid-source diffusion technique, a dopant-containing material (the solid source) is deposited on the semiconductor fin to be doped. An elevated temperature treatment is then performed to allow the dopants in the dopant-containing material or solid-source to diffuse into the semiconductor fins. Examples of dopant-containing materials include boro-silicate glass (BSG), phospho-silicate glass (PSG), doped germanium, etc. The discussion related to
While several embodiments of the invention, together with modifications thereof, have been described in detail herein and illustrated in the accompanying drawings, it will be evident that various modifications are possible without departing from the scope of the present invention. The examples given are intended to be illustrative rather than exclusive. The drawings may not necessarily be to scale and features may be shown in a schematic form.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4933298||Dec 19, 1988||Jun 12, 1990||Fujitsu Limited||Method of making high speed semiconductor device having a silicon-on-insulator structure|
|US4946799||Nov 9, 1989||Aug 7, 1990||Texas Instruments, Incorporated||Process for making high performance silicon-on-insulator transistor with body node to source node connection|
|US5115289||Aug 5, 1991||May 19, 1992||Hitachi, Ltd.||Semiconductor device and semiconductor memory device|
|US5317175||Jan 29, 1992||May 31, 1994||Nissan Motor Co., Ltd.||CMOS device with perpendicular channel current directions|
|US5317178||Jul 22, 1993||May 31, 1994||Industrial Technology Research Institute||Offset dual gate thin film field effect transistor|
|US5464783||Feb 2, 1995||Nov 7, 1995||At&T Corp.||Oxynitride-dioxide composite gate dielectric process for MOS manufacture|
|US5607865||Jan 27, 1995||Mar 4, 1997||Goldstar Electron Co., Ltd.||Structure and fabrication method for a thin film transistor|
|US5801397||May 30, 1995||Sep 1, 1998||Sgs-Thomson Microelectronics, Inc.||Device having a self-aligned gate electrode wrapped around the channel|
|US5814895||Dec 19, 1996||Sep 29, 1998||Sony Corporation||Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate|
|US5998852||May 15, 1998||Dec 7, 1999||International Business Machines Corporation||Geometrical control of device corner threshold|
|US6114725||Jun 9, 1998||Sep 5, 2000||International Business Machines Corporation||Structure for folded architecture pillar memory cell|
|US6157061||Aug 27, 1998||Dec 5, 2000||Nec Corporation||Nonvolatile semiconductor memory device and method of manufacturing the same|
|US6222234||Apr 8, 1999||Apr 24, 2001||Nec Corporation||Semiconductor device having partially and fully depleted SOI elements on a common substrate|
|US6252284||Dec 9, 1999||Jun 26, 2001||International Business Machines Corporation||Planarized silicon fin device|
|US6300182||Dec 11, 2000||Oct 9, 2001||Advanced Micro Devices, Inc.||Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage|
|US6342410||Jul 10, 2000||Jan 29, 2002||Advanced Micro Devices, Inc.||Fabrication of a field effect transistor with three sided gate structure on semiconductor on insulator|
|US6344392||Nov 16, 1998||Feb 5, 2002||Vanguard International Semiconductor Corporation||Methods of manufacture of crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor|
|US6380024||Feb 7, 2000||Apr 30, 2002||Taiwan Semiconductor Manufacturing Company||Method of fabricating an SRAM cell featuring dual silicide gates and four buried contact regions|
|US6387739||Aug 7, 1998||May 14, 2002||International Business Machines Corporation||Method and improved SOI body contact structure for transistors|
|US6391695||Aug 7, 2000||May 21, 2002||Advanced Micro Devices, Inc.||Double-gate transistor formed in a thermal process|
|US6391782||Jun 20, 2000||May 21, 2002||Advanced Micro Devices, Inc.||Process for forming multiple active lines and gate-all-around MOSFET|
|US6391796||Sep 7, 1999||May 21, 2002||Shin-Etsu Handotai Co., Ltd.||Method for heat-treating silicon wafer and silicon wafer|
|US6411725||Jun 20, 2000||Jun 25, 2002||Digimarc Corporation||Watermark enabled video objects|
|US6413802||Oct 23, 2000||Jul 2, 2002||The Regents Of The University Of California||Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture|
|US6432829||Mar 8, 2001||Aug 13, 2002||International Business Machines Corporation||Process for making planarized silicon fin device|
|US6451656||Feb 28, 2001||Sep 17, 2002||Advanced Micro Devices, Inc.||CMOS inverter configured from double gate MOSFET and method of fabricating same|
|US6475869 *||Feb 26, 2001||Nov 5, 2002||Advanced Micro Devices, Inc.||Method of forming a double gate transistor having an epitaxial silicon/germanium channel region|
|US6475890||Feb 12, 2001||Nov 5, 2002||Advanced Micro Devices, Inc.||Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology|
|US6476437||Jun 18, 2001||Nov 5, 2002||Vanguard International Semiconductor Corp.||Crown or stack capacitor with a monolithic fin structure|
|US6492212||Oct 5, 2001||Dec 10, 2002||International Business Machines Corporation||Variable threshold voltage double gated transistors and method of fabrication|
|US6514808||Nov 30, 2001||Feb 4, 2003||Motorola, Inc.||Transistor having a high K dielectric and short gate length and method therefor|
|US6521949||May 3, 2001||Feb 18, 2003||International Business Machines Corporation||SOI transistor with polysilicon seed|
|US6525403||Sep 24, 2001||Feb 25, 2003||Kabushiki Kaisha Toshiba||Semiconductor device having MIS field effect transistors or three-dimensional structure|
|US6534807||Aug 13, 2001||Mar 18, 2003||International Business Machines Corporation||Local interconnect junction on insulator (JOI) structure|
|US6562491||Oct 15, 2001||May 13, 2003||Advanced Micro Devices, Inc.||Preparation of composite high-K dielectrics|
|US6573549||Jun 21, 2002||Jun 3, 2003||Texas Instruments Incorporated||Dynamic threshold voltage 6T SRAM cell|
|US6596599||Jul 16, 2001||Jul 22, 2003||Taiwan Semiconductor Manufacturing Company||Gate stack for high performance sub-micron CMOS devices|
|US6605514||Sep 9, 2002||Aug 12, 2003||Advanced Micro Devices, Inc.||Planar finFET patterning using amorphous carbon|
|US6610576||Dec 13, 2001||Aug 26, 2003||International Business Machines Corporation||Method for forming asymmetric dual gate transistor|
|US6611029||Nov 8, 2002||Aug 26, 2003||Advanced Micro Devices, Inc.||Double gate semiconductor device having separate gates|
|US6617210||May 31, 2002||Sep 9, 2003||Intel Corporation||Method for making a semiconductor device having a high-k gate dielectric|
|US6635909||Mar 19, 2002||Oct 21, 2003||International Business Machines Corporation||Strained fin FETs structure and method|
|US6642090||Jun 3, 2002||Nov 4, 2003||International Business Machines Corporation||Fin FET devices from bulk semiconductor and method for forming|
|US6657252||Mar 19, 2002||Dec 2, 2003||International Business Machines Corporation||FinFET CMOS with NVRAM capability|
|US6686231||Dec 6, 2002||Feb 3, 2004||Advanced Micro Devices, Inc.||Damascene gate process with sacrificial oxide in semiconductor devices|
|US6706571||Oct 22, 2002||Mar 16, 2004||Advanced Micro Devices, Inc.||Method for forming multiple structures in a semiconductor device|
|US6720231||Jan 28, 2002||Apr 13, 2004||International Business Machines Corporation||Fin-type resistors|
|US6720619||Dec 13, 2002||Apr 13, 2004||Taiwan Semiconductor Manufacturing Company, Ltd.||Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices|
|US6762448||Apr 3, 2003||Jul 13, 2004||Advanced Micro Devices, Inc.||FinFET device with multiple fin structures|
|US6768158||Sep 4, 2002||Jul 27, 2004||Korea Advanced Institute Of Science And Technology||Flash memory element and manufacturing method thereof|
|US6787854 *||Mar 12, 2003||Sep 7, 2004||Advanced Micro Devices, Inc.||Method for forming a fin in a finFET device|
|US6821834||Dec 4, 2002||Nov 23, 2004||Yoshiyuki Ando||Ion implantation methods and transistor cell layout for fin type transistors|
|US6833588||Oct 22, 2002||Dec 21, 2004||Advanced Micro Devices, Inc.||Semiconductor device having a U-shaped gate structure|
|US6844238||Mar 26, 2003||Jan 18, 2005||Taiwan Semiconductor Manufacturing Co., Ltd||Multiple-gate transistors with improved gate control|
|US6855606||Feb 20, 2003||Feb 15, 2005||Taiwan Semiconductor Manufacturing Company, Ltd.||Semiconductor nano-rod devices|
|US6855990||Nov 26, 2002||Feb 15, 2005||Taiwan Semiconductor Manufacturing Co., Ltd||Strained-channel multiple-gate transistor|
|US6858478 *||Feb 14, 2003||Feb 22, 2005||Intel Corporation||Tri-gate devices and methods of fabrication|
|US6864519||Nov 26, 2002||Mar 8, 2005||Taiwan Semiconductor Manufacturing Co., Ltd.||CMOS SRAM cell configured using multiple-gate transistors|
|US6885055 *||Feb 4, 2003||Apr 26, 2005||Lee Jong-Ho||Double-gate FinFET device and fabricating method thereof|
|US6992354||Jun 25, 2003||Jan 31, 2006||International Business Machines Corporation||FinFET having suppressed parasitic device characteristics|
|US7005330||Jun 27, 2003||Feb 28, 2006||Taiwan Semiconductor Manufacturing Company, Ltd.||Structure and method for forming the gate electrode in a multiple-gate transistor|
|US7105894||Feb 27, 2003||Sep 12, 2006||Taiwan Semiconductor Manufacturing Co., Ltd.||Contacts to semiconductor fin devices|
|US7148526 *||Jan 23, 2003||Dec 12, 2006||Advanced Micro Devices, Inc.||Germanium MOSFET devices and methods for making same|
|US7214991||Dec 6, 2002||May 8, 2007||Taiwan Semiconductor Manufacturing Co., Ltd.||CMOS inverters configured using multiple-gate transistors|
|US7265417 *||Jun 16, 2004||Sep 4, 2007||International Business Machines Corporation||Method of fabricating semiconductor side wall fin|
|US7276763||Dec 15, 2005||Oct 2, 2007||Taiwan Semiconductor Manufacturing Company, Ltd.||Structure and method for forming the gate electrode in a multiple-gate transistor|
|US7358121 *||Aug 23, 2002||Apr 15, 2008||Intel Corporation||Tri-gate devices and methods of fabrication|
|US20020011612||Jul 30, 2001||Jan 31, 2002||Kabushiki Kaisha Toshiba||Semiconductor device and method for manufacturing the same|
|US20030011080||Jul 11, 2001||Jan 16, 2003||International Business Machines Corporation||Method of fabricating sio2 spacers and annealing caps|
|US20030042528||Aug 30, 2001||Mar 6, 2003||Leonard Forbes||Sram cells with repressed floating gate memory, low tunnel barrier interpoly insulators|
|US20030042531||Sep 4, 2002||Mar 6, 2003||Lee Jong Ho||Flash memory element and manufacturing method thereof|
|US20030057486||Sep 27, 2001||Mar 27, 2003||International Business Machines Corporation||Fin field effect transistor with self-aligned gate|
|US20030067017||Sep 13, 2002||Apr 10, 2003||Meikei Ieong||Variable threshold voltage double gated transistors and method of fabrication|
|US20030102497||Dec 4, 2001||Jun 5, 2003||International Business Machines Corporation||Multiple-plane finFET CMOS|
|US20030111678||Jun 28, 2002||Jun 19, 2003||Luigi Colombo||CVD deposition of M-SION gate dielectrics|
|US20030113970||Dec 14, 2001||Jun 19, 2003||Fried David M.||Implanted asymmetric doped polysilicon gate FinFET|
|US20030178670||Mar 19, 2002||Sep 25, 2003||International Business Machines Corporation||Finfet CMOS with NVRAM capability|
|US20030178677||Mar 19, 2002||Sep 25, 2003||International Business Machines Corporation||Strained fin fets structure and method|
|US20040007715||Jul 9, 2002||Jan 15, 2004||Webb Douglas A.||Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys|
|US20040031979||Jun 6, 2003||Feb 19, 2004||Amberwave Systems Corporation||Strained-semiconductor-on-insulator device structures|
|US20040036126||Aug 23, 2002||Feb 26, 2004||Chau Robert S.||Tri-gate devices and methods of fabrication|
|US20040038464||Aug 21, 2003||Feb 26, 2004||Fried David M.||Multiple-plane FinFET CMOS|
|US20040061178||Dec 31, 2002||Apr 1, 2004||Advanced Micro Devices Inc.||Finfet having improved carrier mobility and method of its formation|
|US20040075122||Oct 22, 2002||Apr 22, 2004||Ming-Ren Lin||Double and triple gate MOSFET devices and methods for making same|
|US20040087094||Oct 30, 2002||May 6, 2004||Advanced Micro Devices, Inc.||Semiconductor component and method of manufacture|
|US20040108523||Dec 6, 2002||Jun 10, 2004||Hao-Yu Chen||Multiple-gate transistor structure and method for fabricating|
|US20040119100 *||Dec 19, 2002||Jun 24, 2004||International Business Machines Corporation||Dense dual-plane devices|
|US20040145000||Jan 23, 2003||Jul 29, 2004||An Judy Xilin||Tri-gate and gate around MOSFET devices and methods for making same|
|US20050121706||Jan 7, 2005||Jun 9, 2005||Hao-Yu Chen||Semiconductor nano-rod devices|
|US20050275010||Apr 12, 2005||Dec 15, 2005||Hung-Wei Chen||Semiconductor nano-wire devices and methods of fabrication|
|US20060234431||Jun 5, 2006||Oct 19, 2006||Yee-Chia Yeo||Doping of semiconductor fin devices|
|FR2617642A1||Title not available|
|JPH0215875A||Title not available|
|1||Auth, Christopher P., et al., "Scaling Theory for Cylindrical, Fully-Depleted, Surrounding-Gate MOSFETs," IEEE Electron Device Letters, vol. 18, No. 2 (Feb. 1997) pp. 74-76.|
|2||Celik, Muhsin, et al., "A 45nm Gate Length High Performance SOI Transistor for 100nm CMOS Technology Applications," Symposium on VLSI Technology Digest of Technical Papers (2002) pp. 166-167.|
|3||Chau, R., et al., "Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and trl-gate," Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (2002) pp. 68-69.|
|4||Chau, Robert, et al., "A 50nm Depleted-Substrate CMOS Transistor (DST)," IEDM (2001) pp. 621-624.|
|5||Chen, W., et al., "Suppression of the SOI Floating-body Effects by Linked-body Device Structure," Symposium on VLSI Technology Digest of Technical Papers (1996) pp. 92-93.|
|6||Colinge, J.P., et al., Silicon-on-Insulator "Gate-All-Around Device," International Electron Devices Meeting (Apr. 1990) pp. 595-598.|
|7||Colinge, J.P., et al., Silicon-on-Insulator "Gate—All-Around Device," International Electron Devices Meeting (Apr. 1990) pp. 595-598.|
|8||Fung, Samuel K.H., et al., "Gate Length Scaling Accelerated to 30nm regime using Ultra-thin Film PD-SOI Technology," IEDM (2001) pp. 629-632.|
|9||Geppert, Linda, "The Amazing Vanishing Transistor Act," IEEE Spectrum (Oct. 2002) pp. 28-33.|
|10||Huang, X., et al., "Sub-50 nm P-Channel FinFET," IEEE Transactions on Electron Devices, vol. 48, No. 5 (May 2001) pp. 880-886.|
|11||Je, Minkyu, et al., "Quantized Conductance of a Gate-all-Around Silicon Quantum Wire Transistor," Microprocesses and Nanotechnology Conference (1998) pp. 150-151.|
|12||Kranti, Abhinav, et al., "Design Guidelines of Vertical Surrounding Gate (VSG) MOSFETs for Future ULSI Circuit Applications," IEEE (2001) pp. 161-165.|
|13||Leobandung, E., et al., "Wire-Channel and Wrap-Around-Gate Metal Oxide-Semiconductor Field-Effect Transistors with a Significant Reduction of Short Channel Effects," Journal of Vacuum Science and Technology B, vol. 15, No. 6 (Nov. 1997) pp. 2791-2794.|
|14||Nemati, Farid, et al., "A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories," IEDM (1999) pp. 283-286.|
|15||Nitayama. Akihiro, et al., "Multi-Pillar Surrounding Gate Transistor (M-SGT) for Compact and High-Speed Circuits," IEEE Transactions on Electron Devices, vol. 38, No. 3 (Mar. 1991) pp. 579-583.|
|16||Oh, Sang-Hyun, et al., "Analytic Description of Short-Channel Effects in Fully-Depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs," IEEE Electron Device Letters, vol. 21, No. 9 (Sep. 2000) pp. 445-447.|
|17||Sato, Nobuhiko, et al., "Hydrogen Annealed Silicon-On-Insulator," Appl. Physics Letter, vol. 65, No. 15 (Oct. 10, 1994) pp. 1924-1926.|
|18||Shahidi, G.G., "SOI Technology for the GHz Era," IBM J. Res. & Dev., vol. 46, No. 2/3 (Mar./May 2002) pp. 121-131.|
|19||Solymar, L., et al., "Electrical Properties of Materials," Oxford University Press, 1998, Sixth Edition, pp. 152.|
|20||Tang, Stephen H., et al., "FinFET-A Quasi-Planar Double-Gate MOSFET," IEEE International Solid-State Circuits Conference (2001) pp. 118-119 & 437.|
|21||Tang, Stephen H., et al., "FinFET—A Quasi-Planar Double-Gate MOSFET," IEEE International Solid-State Circuits Conference (2001) pp. 118-119 & 437.|
|22||Wolf, S., "Silicon Processing for the VLSI Era"; vol. 2-Chapter 6, CMOS Process Integration, p. 369, Lattice Press, Sunset Beach, CA.|
|23||Wong, H.S.P., "Beyond the Conventional Transistor," IBM Journal of Research and Development, vol. 46, No. 2/3 (Mar./May 2002) pp. 133-167.|
|24||Yamagata, K., et al., "Selective Growth of Si Crystals from the Agglomerated Si Seeds Over Amorphous Substrates," Appl. Phys, Lett., vol. 61, No. 21 (Nov. 23, 1992) pp, 2557-2559.|
|25||Yang, et al, "25nm CMOS Omega FETs," International Electron Devices Meeting, Digest of Technical Papers, 2002, pp. 255-258, IEEE.|
|26||Yang, et al., "23nm CMOS Omega FETs," International Electron Devices Meeting, Digest of Technical Papers (Dec. 2002) pp. 109-110.|
|27||Yang, et al., "35nm CMOS FinFETs," 2002 Symposium on VLSI Technology Digest of Technical Papers (Jun. 2002) pp. 109-110. cited by other.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
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|US8906807||Oct 10, 2012||Dec 9, 2014||International Business Machines Corporation||Single fin cut employing angled processing methods|
|US9276087||Apr 28, 2014||Mar 1, 2016||Samsung Electronics Co., Ltd.||Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin|
|US9431522||Jan 21, 2016||Aug 30, 2016||Samsung Electronics Co., Ltd.||Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin|
|US9653593||Jan 18, 2013||May 16, 2017||Taiwan Semiconductor Manufacturing Company, Ltd.||Method of fabricating FinFET device and structure thereof|
|US20060234431 *||Jun 5, 2006||Oct 19, 2006||Yee-Chia Yeo||Doping of semiconductor fin devices|
|US20110129978 *||Dec 1, 2009||Jun 2, 2011||Kangguo Cheng||Method and structure for forming finfets with multiple doping regions on a same chip|
|WO2013048513A1 *||Sep 30, 2011||Apr 4, 2013||Intel Corporation||Non-planar transitor fin fabrication|
|U.S. Classification||257/347, 257/345, 257/E29.117, 257/335|
|International Classification||H01L21/336, H01L21/265, H01L29/786, H01L29/76|
|Cooperative Classification||H01L21/26586, H01L29/66803, H01L29/785|
|European Classification||H01L29/66M6T6F16F2, H01L29/78S, H01L21/265F|
|Jun 29, 2010||CC||Certificate of correction|
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