|Publication number||US7701256 B2|
|Application number||US 11/901,304|
|Publication date||Apr 20, 2010|
|Filing date||Sep 17, 2007|
|Priority date||Sep 29, 2006|
|Also published as||DE602007013425D1, EP2064812A2, EP2064812B1, US20080079474, WO2008042188A2, WO2008042188A3|
|Publication number||11901304, 901304, US 7701256 B2, US 7701256B2, US-B2-7701256, US7701256 B2, US7701256B2|
|Inventors||Christopher Peter Hurrell, Colin Gerard Lyden|
|Original Assignee||Analog Devices, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (2), Classifications (20), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a signal conditioning circuit which is suitable for use in a successive approximation converter, the circuit operating to condition a signal for supply to a comparator latch used within the successive approximation converter.
In a successive approximation routine, SAR, converter a comparator is used to determine the difference between a trial value and the analog value being converted. It is known in prior art successive approximation converters for the comparator to be formed from a number of voltage amplifier stages followed by a regenerative latch. The latch is a real component and hence suffers from both thermal noise and an input offset. The purpose of the amplifier stages is to reduce the effect of thermal noise and the offset by amplifying the voltage difference prior to it being provided to the latch. The amplifiers also have the effect of reducing “kickback” from the latch that can cause voltage spikes at the comparator inputs and which then have to be given time to settle out.
The outputs “on” and “op” are connected to either a subsequent amplifier stage or to the comparator latch. The outputs therefore have to drive both the inherent capacitance of the following stage, such as the gate capacitance of a subsequent field effect transistor, and also have to drive the parasitic capacitances associated with the load and devices connected to the output nodes. The combination of the resistors 16 and 18 and the parasitic capacitance CP creates a pole, giving the circuit an overall low-pass frequency response.
It is also known to replace the load resistors 16 and 18 by active loads as shown in
It should be noted that making the gain larger has the effect of reducing the bandwidth of the amplifier (because the product of gain and bandwidth is generally a constant). In one respect this is desirable as it reduces a noise bandwidth of the circuit, however it also increases a settling time. As a result although the influence of noise would be reduced, the converter bit trials would have to run more slowly to allow the circuit to settle to full accuracy. As a result, amplifier stages have typically been made with gains of between 10 and 20.
According to a first aspect of the present invention there is provided a signal conditioning circuit for a latching comparator, the circuit comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.
According to a second aspect of the present invention there is provided a successive approximation converter including a signal conditioning circuit comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.
According to a third aspect of the present invention there is provided a comparator, comprising a clocked latch preceded by at least one integrator.
The present invention will further be described, by way of non-limiting example, with reference to the accompanying drawings in which:
When progressing from one bit trial to another, the parasitic capacitances CP at the output “on” and “op” of the signal conditioning circuit may need to transition from the value appropriate for the last bit trial to the value appropriate for the current bit trial. This may require a full scale change in the voltage stored across the parasitic capacitances CP. Given that the charge and discharge current in the prior art arrangements of
Given that the provision of the shorting switch solves the settling problem, the inventors realised that it was also possible to increase the gain of the stage without incurring undesirable effects. In fact, the inventors realised that the comparator or latch preamplifier could be replaced by an integrator. If the circuit is acting as an integrator, then for a small differential DC input between the gates of the transistors Q1 and Q2 then the output voltage difference between “on” and “op” would rise linearly with respect to time and, if there were no head room constraints on the supply rails, would continue rising indefinitely. This contrasts with the operation of an amplifier where the output voltage would ramp up following a classic “RC” time constant characteristic to an ultimate value represented by A×VDIFF, where A represents the amplifier gain and VDIFF represents the voltage difference between the input voltages supplied to the gates of Q1 and Q2.
By making the transconductance of Q3, Q4, Q5 and Q6 the same then the theoretical gain of the circuit would, if the drain-source impedance is ignored, exhibit infinite DC gain and would approximate the integrator functionality.
The circuit of
A second part of the auto-zeroing circuit occurs around the active load. As in the embodiment of
If the transconductance of Q7 is similar to that of Q1 then the gain of the circuit falls to unity when Q7 is conducting in this diode connected manner, and this can be achieved by using a further transistor Q9 to provide a low impedance path between the drain and the gate of Q7 during the auto-zero phase. A capacitor 60 is provided to sample and store the gate voltage of Q7, depending on whether the further transistor Q9 is in a conducting state (sample) or non-conducting (store). A corresponding arrangement involving transistors Q8, Q10 and a further capacitor 62 are formed in the other half of the circuit.
In order to understand the operation of the circuit, suppose that transistors 51 and 52 are placed in a high impedance state and that transistors 53 and 54 are switched to a low impedance state such that the same voltage is applied to the gates of Q1 and Q2. If the circuit was perfectly matched then the voltages at “on” and “op” would be identical. However suppose that there is a slight offset between Q1 and Q2, and that this offset is represented by VOFF. When Q9 and Q10 are non-conducting, then the load for Q1 and Q2 is formed solely by transistors Q3, Q4, Q5 and Q6 and hence the gain of the stage is large and theoretically approaching infinity. For convenience, it is easier to assume that the gain is finite but large. Therefore suppose that the gain of the circuit is 1000. Therefore the output offset voltage VOUTOFF would be 1000VOFF. However, suppose now that transistors Q9 and Q10 are operated as switches thereby causing the transistors Q7 and Q8 to become the predominant load for transistors Q1 and Q2 thereby reducing the gain of the circuit to close to unity. If we assume for convenience that the gain is reduced to unity then the output offset VOUTOFF becomes reduced to that of the input offset VOFF. The capacitors 60 and 62 charge to the gate voltages of transistors Q7 and Q8 in order to achieve this condition. Suppose now that transistors Q9 and Q10 are switched into a non-conducting state. The output voltage offset immediately subsequent to switching of transistors Q9 and Q10 off is identical to that which occurred immediately prior to switching the transistors off, but the gain of the circuit increased from around unity to around 1000 times. It can therefore be seen that the input referenced offset has effectively been reduced by a factor of 1000 as transistors Q7 and Q8 become driven by a constant gate voltage and therefore effectively form an infinite impedance load similar to that formed by the combination of transistors Q3 to Q6 in the circuit described with respect to
It should be noted that for any of the circuit arrangements described herein, cascode devices may also be used to further increase the effective gain of the stage and also to decrease parasitic capacitance on the output node. These cascode devices may be placed between the output nodes and the input devices Q1 and Q2, or the output nodes and the load devices Q3, Q4, Q5, Q6, Q7 and Q8. Similarly cascode devices could be inserted into the arrangement shown in
As noted before, the reason why the stages act as integrators is that there is always an unwanted parasitic capacitance at the output of the integrator. In preferred embodiments of the invention no instantiated capacitor is used and use is made of the inherent parasitic capacitance of the circuit. In fact it is desirable to make the parasitic capacitance at the output of the integrator as small as possible in order to maximise the effective gain or rate of integration of the stage.
The auto-zero arrangement in
The converter includes a digital to analog converter 70 for generating a trial value. The digital to analog converter 70 may be implemented using several technologies, however switched capacitor arrays are particularly well suited as they can also be used to sample the input signal. The switched capacitor array may be implemented in a dual ended fashion, as is well known to the person skilled in the art. In the example shown in
The signal conditioning circuit can be regarded as being internal to the strobed or clocked comparator. The comparator could be implemented merely as a clocked latch receiving its output from the integrating signal conditioning circuit.
In use, and with reference to
In a SAR cycle some of the bit trials may benefit from an extended integration period 104′ as shown in
|Cited Patent||Filing date||Publication date||Applicant||Title|
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8487659||Apr 22, 2011||Jul 16, 2013||Analog Devices, Inc.||Comparator with adaptive timing|
|US20120194252 *||Jan 31, 2011||Aug 2, 2012||Hynix Semiconductor Inc.||Method of shifting auto-zero voltage in analog comparators|
|U.S. Classification||327/52, 327/336, 327/345, 327/54|
|International Classification||H03F3/45, G01R19/00, G11C7/00|
|Cooperative Classification||H03F3/45188, H03F2203/45642, H03F2200/264, H03F2203/45082, H03F3/45659, H03F2203/45396, H03M1/124, H03F2200/78, H03M1/46, H03F2203/45424|
|European Classification||H03F3/45S3B1A4, H03F3/45S1B1A, H03M1/12S|
|Sep 17, 2007||AS||Assignment|
Owner name: ANALOG DEVICES, INC., MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HURRELL, CHRISTOPHER PETER;LYDEN, COLIN GERARD;REEL/FRAME:019878/0911;SIGNING DATES FROM 20070903 TO 20070906
Owner name: ANALOG DEVICES, INC.,MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HURRELL, CHRISTOPHER PETER;LYDEN, COLIN GERARD;SIGNING DATES FROM 20070903 TO 20070906;REEL/FRAME:019878/0911
|Sep 18, 2013||FPAY||Fee payment|
Year of fee payment: 4