US 7704804 B2
A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.
1. A method comprising the steps of:
providing a substrate including a plurality of fuse structures formed thereupon;
forming a dielectric layer over the fuse structures;
forming a conductor layer over an interconnect structure and a disposable conductive hard etch stop shape over each of the fuse structures wherein the etch stop controls the intermediate dielectric layer above each ones of the fuse structures; and
forming a material-free region between adjacent ones of said fuse structure.
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9. A method comprising the steps of:
providing a substrate including a plurality of fuse structures formed in a first dielectric layer;
forming at least a second dielectric layer over said plurality of fuse structures;
forming a conductor layer on said second dielectric layer;
patterning the conductor layer to simultaneously form an interconnect structure, and a conductive hard etch stop shape over each ones of the fuse structures in order accurately position an intermediate passivation layer above the fuse structures;
forming an opening in said at least second dielectric layer between adjacent ones of said fuse structures to create a void wherein the void prevents propagation of cracks between said adjacent fuse structures during a fuse blow operation, and
removing the hard etch stop shape prior to a fuse blow operation.
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forming a first silicon nitride layer;
forming a silicon oxide layer on said first silicon nitride layer; and
forming a second silicon nitride layer on said silicon oxide layer.
15. The method of
forming a photoresist layer on said at least second dielectric layer;
exposing and developing said photoresist layer; and
etching exposed portions of said at least second dielectric layer to form said opening.
16. The method of
forming a photoresist layer on said conductor layer;
exposing and developing said photoresist layer; and
removing an exposed portion of said conductor layer, wherein a remaining portion of the conductor layer forms said first interconnect structure and the hard edge stop.
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This application is related to a commonly assigned non-provisional application Ser. No. 11/277,398 filed on Mar. 24, 2006 which was based on a provisional application Ser. No. 60/594,395, “Crack Stop Void Formed in a Low-k Dielectric Layer Between Adjacent Fuses”, filed Apr. 4, 2005, and incorporated in its entirety herein by reference.
This invention relates generally to integrated circuits and, more particularly, to protection of fuses formed in a low-k dielectric layer from damage when employing a laser beam in a fuse blow operation. The crack stop void is formed simultaneously with the formation of an interconnect structure along with a portion of the conductor layer over the fuse.
Semiconductor integrated circuits (IC) and their manufacturing techniques are well known in the art. In typical integrated circuits, a large number of semiconductor devices are fabricated on a silicon substrate. To achieve the desired functionality, a plurality of conductors or interconnects are typically employed for coupling selected devices together. In some integrated circuits, some of the conductive links may be coupled to fuses which may be selectively programmed (i.e. blown) after fabrication using lasers. By way of example, in a logic integrated circuit, fuses may be employed during manufacturing to protect from destruction some of the gate stacks of the transistors from inadvertent built-up of electrostatic charge. Once the fabrication of the IC is substantially complete, the fuses may be blown or cut to permit the logic circuit to function as if the protective current paths never existed. More commonly, fuses may be employed for repairing defects found in the logic circuit by appropriate replacement of defective elements with redundancy replacement elements present within or without the chip.
Fuses may be selectively blown or programmed with a laser beam. Once blown, the fuse changes from a highly conductive state to a highly resistive state (i.e. non-conductive) which inhibits current from flowing through it and represents an open circuit to the path taken by the current. Typically, a fuse is formed of a metallic material and the laser beam imparts enough energy into the fuse to melt the metal. The fuse is formed in a dielectric material such as silicon oxide and a silicon oxide dielectric layer formed over the fuse. Energy delivered from the laser is transmitted through the surrounding silicon oxide dielectric layers. Since silicon oxide is a relatively “rigid” material, it is possible to blow the fuse with minimal damage to the surrounding dielectric layers using conventional fuse structure with sufficient distance between fuses. Thus, the risk of incorrectly programming one fuse when programming another nearby fuse is relatively low.
A trend in the fabrication of integrated circuits is the use of “low-k” dielectric material in an inter-level dielectric layer to reduce parasitic capacitance between interconnects (e.g. wires and vias) resulting in an increase in the speed of devices. Fuses are typically formed in the same inter-level dielectric layer as the interconnects. The use of low-k dielectrics in the back-end-of-line (BEOL) levels can result in a reduction in the material strength of the inter-level dielectric layer. For example, having layers of silicon oxide dielectric (e.g. a rigid material) and low-k dielectric (e.g. a non-rigid material) formed upon each other have resulted in separation of the different material layers when placed under a physical stress. The separation of the inter-level dielectric layers can result in yield or reliability issues due to, for example, exposure of interconnects to air (e.g. corrosion of metal interconnects). Since fuses are formed in the same inter-level dielectric layer as interconnects, fuses are also susceptible to damage.
Thus, fuses are typically formed in silicon oxide layers above the low-k dielectric layers. It is desirable to create a reliable and predictable fuse structure which could be used for low-k or silicon oxide dielectric materials.
It is an aspect of the present invention to provide a method of forming fuses in a low-k or silicon oxide dielectric layer that are spaced apart with minimal distances in a repeatable in semiconductor manufacturing process.
It is another aspect of the present invention to provide a method of forming fuses in a low-k dielectric layer having high reliability and high yield.
The above and other aspects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in an aspect, a method thereof comprising the steps of providing a substrate including a plurality of fuse structures formed thereupon; and simultaneously forming a material-free region between adjacent ones of the fuse structures while removing a portion of a conductor layer to form an interconnect structure.
In another aspect, the present invention is directed to a method thereof comprising the steps of providing a substrate including a plurality of fuse structures formed in a first dielectric layer; forming at least a second dielectric layer over the plurality of fuse structures; forming an opening in the at least second dielectric layer between adjacent ones of the fuse structures; forming a conductor layer on the second dielectric layer filling the opening; and patterning the conductor layer to simultaneously form a first interconnect structure and a void in the opening, wherein the void prevents propagation of cracks between the adjacent fuse structures during a fuse blow operation. A problem with previous trench crack stop methodology particularly when copper is used in the last metal level fuses depends on its ultimate reliability upon a well controlled set of critical parameters which define the overall process window. The solution is to produce a fuse dielectric over-passivation thickness that does not vary from fuse to fuse, chip to chip, wafer to wafer, and lot to lot because of the nonuniformity of the RIE process and thickness of the dielectric material that must be etched.
In the present invention, the fuse crack stop is created using a pattern-conformal aluminum fuse over-plate created at the top most aluminum pad (TD) or pad/wiring (LB) layer, the edges of which serve as the mask edges in the definition of the interfuse crack stop. In this case the interfuse crack stop is created by a vertical etch occurring after the TD or LB layers are completely formed. The over plate aluminum acts to mask the over-fuse passivation during all processing subsequent to the aluminum deposition (including the vertical dielectric RIE process to open the pad via and create the interfuse crack stop. Thus the over-fuse passivation is fixed at the as-deposited thickness, at all fuse locations, resulting in a very consistent and uniform fuse passivation coverage thickness across all parts
The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
The present invention may be used when reliable and repeatable fuse structures having controllable passivation are required, such as, silicon oxide have passivation layers at minimal fuse pitch, or fuse passivation over low-k material, or multi-layers of low-k material surround the fuse. This invention is particularly suited in situations where laser fuse integration is necessary in multiple layers of low-k materials are used in which there is a reduction in adhesion of materials. The reduction in material adhesion can lead to excessive delaminating, cracking or cratering (hereinafter referred to as “damage”) of the materials which can cause reliability and/or yield degradation by incorrectly programming a nearby fuse. One solution is to space the fuses further apart from each other but this will increase the layout footprint (i.e. area) of the fuse bank for a given design. Another solution is to form a void between adjacent fuses as described in, for example, commonly assigned U.S. patent application Ser. No. 11/277,398, however, when a final passivation layer (e.g. dielectric) is required over a last wiring level then portions of the passivation layer form in the void and diminish the effectiveness of the void as a damage barrier since passivation material in the void provides a pathway for damage to propagate through the passivation-filled damage barrier. A solution to allow for the removal of passivation material from the void would be to increase the size of the void but this will consume much of the area between adjacent fuses thus limiting future fuse pitch reduction.
According to an embodiment of the invention shown in
In conventional integrated circuit fuse designs, fuses placed in a row inside a fuse bank cannot be reliably used when fuse pitches (i.e. distance between adjacent fuses) fall below approximately 3 micrometers (um). This is because lasers that are typically used for blowing fuses have a wavelength of the order of about 1 to about 1.3 um. As a result, the smallest spot that can be focused is greater than about 2 to 2.6 um. This, coupled with the uncertainty associated with the positioning of the substrate relative to the laser spot renders the blowing of fuses an unreliable operation. For fuse pitches less than 3 um, the probability of damaging a neighboring fuse increases as the pitch decreases. The introduction of a crack stop filled with material (e.g. metal) between fuses will also not work at these tight pitches since the crack stop itself will be ablated by the laser causing damage to fuses or circuit elements next to it. In the invention described herein, since the crack stop void is made by removing material, damage to the crack stop void due to the laser beam is virtually eliminated. This makes it possible to space fuses even down to a pitch of about 2.2 um without damaging neighboring fuses during fuse blow. Moreover, the crack stop void still performs the function of stopping cracks from damaging neighboring fuses. Thus, spacing of fuses consistent with conventional silicon oxide fuse integration is achieved without an increase in foot print.
In laser fuse integration where copper is the last metal level, fuses ultimately depend on the reliability of a well-controlled set of critical parameters which define the overall process window. The most important process window variables include the specific laser parameters and the fuse structure consistency from part to part, the latter of which is primarily dependent upon over-fuse dielectric passivation thickness. However, that process inherently produces fuse dielectric over-passivation thickness variation from fuse-to-fuse, chip-to-chip, wafer-to-wafer, and lot-to-lot depending on the nonuniformity of the RIE process and the thickness of the dielectric material that must be etched.
In the present invention, the fuse crack stop void is created using a pattern-conformal aluminum fuse over-plate created at TD or LB layer, the edges of which serve as the mask edges in the definition of the interfuse crack stop void. In this case the interfuse crack stop void is created by a vertical etch occurring after the TD and LV levels are formed. The over plate aluminum acts to mask the over-fuse passivation during all processing subsequent to the aluminum deposition (including the vertical dielectric RIE process to open the pad via and create the interfuse crack stop void. Thus the over-fuse passivation is fixed at the as-deposited thickness, at all fuse locations, resulting in a very consistent and uniform fuse passivation coverage thickness across all parts.
Referring now to
Dielectric layers 60, 65 and 70 used for final passivation layer 45 are formed on dielectric layer 45 as shown in
As shown in
The pad level conductor shapes 102 above the layers 60, 65, and 70 that overlie the fuse 50 should be removed after the C4 is formed by wet etching, such as a HCl based etching material, prior to laser activating a fuse blow as shown in
Since the formation of crack stop void 150 and the formation of the passivation layer over the fuse are accomplished simultaneously with the formation of conductive transfer pad 105, additional processing steps dedicated only to the formation of crack stop void 150 are not required. Thus, reductions in fabrication costs and time are achieved.
While there has been shown and described what is considered to be preferred embodiments of the invention, it will, of course, be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention. It is therefore intended that the invention be not limited to the exact forms described and illustrated, but should be constructed to cover all modifications that may fall within the scope of the appended claims.