|Publication number||US7719254 B2|
|Application number||US 11/836,730|
|Publication date||May 18, 2010|
|Filing date||Aug 9, 2007|
|Priority date||Aug 10, 2006|
|Also published as||DE102006037554B3, US20080036445|
|Publication number||11836730, 836730, US 7719254 B2, US 7719254B2, US-B2-7719254, US7719254 B2, US7719254B2|
|Inventors||Thorsten Meyer, Mathias Hans-Ulrich Alexander Von Borcke, Markus Winkler|
|Original Assignee||Infineon Technologies Ag|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Classifications (15), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to German Patent Application No. 10 2006 037 554.8, which was filed Aug. 10, 2006, and is incorporated herein by reference.
The invention relates to a method for setting a reference potential of a current sensor, and to an arrangement for determining the reference potential of a power semiconductor device.
In power electronics, efforts have increasingly been made for a relatively long time to protect the integrated circuits used against overloading and to initiate suitable measures in the case of electrical or thermal overload. For this purpose, the current flow through a corresponding circuit, in particular a power semiconductor device, and/or the temperature thereof is usually detected and compared with predetermined limit values.
Thus, for realizing self-protecting MOS power semiconductor devices, it is known to provide a current sensor and a temperature sensor on the chip. In an embodiment which is likewise known and often put into practice, the current sensor is embodied as a small DMOS transistor that supplies a current proportional to the load current in the power switching device if the voltage values applied to it are the same as those applied to a load DMOS transistor. This small transistor, which is also referred to as a sense DMOS, has an area which is smaller than that of the load DMOS by a factor of 1,000 to 100,000. A current flows through it which is smaller, ideally by the geometrical ratio of the active areas, than the current flowing through the load DMOS and is therefore a measure of the latter current.
In the form of realization of a common-drain technology, the same drain potential and the same gate potential are present at both transistors. The source potential is tapped off suitably at the load DMOS, and the source potential of the sense DMOS is set to the same potential value. The current that flows in this state is then measured. The current serves as an indicator of the load current presently flowing through the load DMOS.
Conventionally, the source potential at the load DMOS is tapped off in various ways.
Thus, it is known to provide a metal tapping at a measuring point at the chip edge.
Advantages and expediencies of the invention emerge, moreover, from the dependent claims and also the following description of preferred exemplary embodiments and embodiment aspects with reference to the figures, in which:
In one embodiment, a method for setting a reference potential of a current sensor in a power semiconductor device is disclosed. On the basis of a specific geometry and a typical two-dimensional potential distribution of the power semiconductor device, a plurality of tapping points are predetermined on the area of the power semiconductor device. On the basis of the specific geometry of the power semiconductor device, a line course between said tapping points and a measuring point for measuring a potential average value is determined and realized. Respective potential values are detected at the tapping points and fed to the measuring point. The potential average value is determined at the measuring point. The potential of the current sensor is set to the potential average value thus determined.
The invention offers the advantage of providing an improved method for setting the reference potential of a current sensor, and also a correspondingly improved measuring arrangement, which ultimately ensure a better function of the current sensor of a power semiconductor device.
In the method according to the invention for setting a reference potential of a current sensor in a power semiconductor device, firstly, on the basis of the specific geometry and a typical two-dimensional potential distribution of the power semiconductor device, a plurality of tapping points are predetermined as measuring points on the area of the power semiconductor device. It is furthermore provided that on the basis of the specific geometry of the power semiconductor device, a processing algorithm for potential values measured at the tapping points for determining a potential average value is predetermined and stored. On this basis, finally, the respective potential values are measured using the tapping points, and, finally, the potential of the current sensor is set by means of the actual potential average value determined with sufficient accuracy in this way.
Specifically referring to a MOS power semiconductor device (a DMOS), according to the invention the source potential is tapped off at a plurality of locations of the active area of the load DMOS and the measured source potential values are averaged over a suitable combination of length and number of lines leading to the tapping points, in a predetermined manner suitable for the specific arrangement. By means of a correspondingly optimized measuring method and an arrangement of this type, it is possible to determine a source potential average value which corresponds to a good approximation to the source potential actually present on average at the load DMOS. The invention can be applied in a similar manner also to an IGBT or similar power semiconductor devices.
One embodiment of the method proposed is for the tapping points to be obtained as the result of a simulation calculation for the specific geometry of the power semiconductor device. In the case of such a simulation calculation, alongside the specific geometry and source potential distribution of the load DMOS—in the sense of boundary conditions—it should be taken into consideration that as the number of tapping points increases, the area taken up for the measuring arrangement increases, but on the other hand the accuracy (insensitivity to process fluctuations, operating point, temperature and bonding accuracy) also increases.
A first embodiment of the tapping point arrangement in the case of a load DMOS with a one-dimensional potential gradient is the linear arrangement in the direction of the potential gradient. In the case of a source potential distribution which has a fall gradient in two directions, a two-dimensional arrangement of the tapping points is preferred which may in particular have more or less the form of a matrix arrangement. In such a matrix arrangement, however, it is not necessary either for all the matrix points to be provided with measuring taps or for these to have identical spacings.
In further embodiments of the invention it is provided that at least one portion of the tapping points is positioned on oxide-insulated poly-Si lines of the power semiconductor device (for instance in trenches). As an alternative or else in combination therewith it may be provided that at least one portion of the tapping points is positioned on metal interconnects and/or doping channels having sufficient conductivity of the MOS power semiconductor device. In any case the measuring arrangement and the method are configured in such a way that at least one tapping point, in particular a plurality of tapping points, is or are determined within the area of the power semiconductor device.
Furthermore, one embodiment of the method according to the invention is for the length of conductive tracks, in particular of the poly-Si lines, metal interconnects or doping channels, from a source bonding pad as far as the respective tapping points to be included in the processing algorithm. In this respect, the method proposed includes a processing algorithm that is based on the knowledge of the person skilled in the art with regard to known design algorithms.
A non-active area of the DMOS is in each case demarcated by a dash-dotted line and hatched. Each of the figures also schematically shows at least one bonding wire with an associated pinch section which makes contact with the front-side metallization (not illustrated) for the source terminal of the DMOS.
Here as in the rest of the figures, the tapping point is to be conceived of as a vertical conductive contact-connection of the front-side metallization to the poly-Si line buried into a trench (or in some figures also directly to a metal interconnect section).
The conductive connection between the tapping point 45.1 and the associated bonding pad 43 is produced here via a relatively long poly-Si conductor structure 46.1, which, owing to the long length L1 is preferably formed from a parallel connection of a plurality of poly-Si lines (provided in the component structure) in trenches with a parallel connection resistance R1. By contrast, the conductive connection of the second tapping point 45.2 to the measuring point 43 is formed over by far the greatest part of the length by a metal interconnect 46.2 b having a practically negligible resistivity, and only a short final section having the length L2 is formed as a poly-Si line 46.2 a with the resistance R2. Owing to its shortness, this section can be formed perfectly well by an individual poly-Si line of the already present component structure.
A third tapping point 55.3 is added, which is positioned in the central region of the active area 51 and is connected to the measuring point 53 via a combination of a section of the metal interconnect 56.2 b and a poly-Si line 56.3 a. The latter has a length L2 and a resistance R2, which, in view of the length lying between the values L1 of the line 56.1 and L3 of the line 56.2 a, should expediently lie between the resistance values of those lines. Here, too, a parallel connection of a plurality of poly-Si lines of the component structure is therefore expediently suitable.
The embodiments shown in
Specifically referring to the arrangement of
It is at the discretion of the developer to choose a linear or matrix-type arrangement in order to harmonize the requirements for sufficient measurement accuracy and low realization outlay. If a sufficiently good result can be obtained with a linear arrangement, this arrangement can also be chosen for a configuration with a two-dimensional fall gradient owing to the advantage of saving space, and, on the other hand, a matrix arrangement may also be preferred for a configuration with approximately one-dimensional fall gradients (as in
In this case, four tapping points 65.1 to 65.4 are distributed over the active area 61 and are conductively connected to the first bonding pad 63 in each case via a section of a metal interconnect 66 b and a poly-Si line section 66.1 a, 66.2 a, 66.3 a and 66.4 a, respectively, that branches off from the interconnect 66 b. By analogy with the explanations further above, it should be taken into account here, too, that the tapping points 65.3, 65.4 with relatively long poly-Si line linking, for obtaining an expediently weighted source potential average value, have poly-Si line sections having a lower “length-specific” resistance (here meant as total resistance relative to a unit length of a poly-Si interconnect or a plurality of interconnects connected in parallel) than the tapping points 65.1, 65.2, which are connected to the metal interconnect 66 b only via very short poly-Si lines.
The further arrangement according to the invention in accordance with
These tapping points 75.1 to 75.9 too, as in the previous embodiment, are connected to the first bonding pad 73 for measuring tapping of the source potential in each case via a section of a metal interconnect 76 b and poly-Si line sections 76.1 a to 76.9 a, respectively. The basic explanations further above apply to the choice of the respective suitable resistance value of the poly-Si line sections and hence the optional formation thereof from a plurality of parallel trench lines sections of the component structure. Thus, in an expedient manner, the lines sections 46.1 a to 46.3 a could in each case be formed from an individual poly-Si line in a trench, the line sections 76.4 a to 76.6 a could be formed by parallel connection of the poly-Si lines in three trenches, and the line sections 46.7 a to 46.9 a could be formed by parallel connection of the poly-Si lines in five trenches.
Finally, the embodiment shown in
As can be discerned in the figure, a total of nine tapping points 85.1 to 85.9 are distributed largely uniformly over the active area 81 of the load DMOS 80, said tapping points all being conductively connected to a first bonding pad 83 for measuring tapping of the source potential. While the tapping points 85.1 to 85.3, which can be seen vertically one below another in the left-hand region of the figure, are connected to the first bonding pad 83 in each case exclusively via a poly-Si line 86.1 to 86.3, the line connection of the remaining tapping points 85.4 to 85.9 comprises in each case a section of a metal interconnect 86 b and poly-Si lines 86.4 a to 86.9 a, respectively. The considerations mentioned further above with regard to the dimensioning and partial configuration by parallel connection of the poly-Si lines in a plurality of trenches running parallel hold true for these interconnect sections.
The embodiment of the invention is not restricted to the above-described exemplary embodiments and highlighted aspects, but rather is likewise possible in a multiplicity of modifications that lie within the scope of expert action.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5815027||Jun 7, 1996||Sep 29, 1998||Siemens Aktiengesellschaft||Circuit configuration for detecting a load current of a power semiconductor component with a source-side load|
|US5828308 *||Aug 5, 1997||Oct 27, 1998||Nec Corporation||Current sensing circuit formed in narrow area and having sensing electrode on major surface of semiconductor substrate|
|US6150714 *||Sep 18, 1998||Nov 21, 2000||Texas Instruments Incorporated||Current sense element incorporated into integrated circuit package lead frame|
|US7085977 *||Oct 25, 2001||Aug 1, 2006||Texas Instruments Incorporated||Method and system for detecting an outlying resistance in a plurality of resistive elements|
|US7277264 *||Mar 18, 2005||Oct 2, 2007||Rohm Co., Ltd.||Semiconductor integrated circuit having current detection functionality and power supply unit equipped with the same|
|DE19520735A1||Jun 7, 1995||Dec 12, 1996||Siemens Ag||Schaltungsanordnung zum Erfassen des Laststroms eines Leistungs-Halbleiterbauelementes mit sourceseitiger Last|
|U.S. Classification||324/72, 361/93.1, 438/14|
|International Classification||G01R29/00, G01R35/00|
|Cooperative Classification||H01L2924/14, H01L2224/0603, H01L2224/05554, H01L2224/05552, H01L2224/04042, H01L2924/13055, G01R19/0092, H01L24/05, H01L2224/4847|
|Oct 22, 2007||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MEYER, THORSTEN;BORCKE, MATHIAS HANS-ULRICH ALEXANDER VON;WINKLER, MARKUS;REEL/FRAME:019990/0964;SIGNING DATES FROM 20070905 TO 20070911
Owner name: INFINEON TECHNOLOGIES AG,GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MEYER, THORSTEN;BORCKE, MATHIAS HANS-ULRICH ALEXANDER VON;WINKLER, MARKUS;SIGNING DATES FROM 20070905 TO 20070911;REEL/FRAME:019990/0964
|Nov 15, 2013||FPAY||Fee payment|
Year of fee payment: 4