|Publication number||US7720110 B2|
|Application number||US 11/610,320|
|Publication date||May 18, 2010|
|Filing date||Dec 13, 2006|
|Priority date||Oct 10, 2000|
|Also published as||CN1193548C, CN1347231A, EP1198085A1, EP1198085B1, US7184449, US20020041607, US20070116062|
|Publication number||11610320, 610320, US 7720110 B2, US 7720110B2, US-B2-7720110, US7720110 B2, US7720110B2|
|Original Assignee||Sony Deutschland Gmbh|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (18), Referenced by (4), Classifications (12), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a Continuation of U.S. patent application Ser. No. 09/972,208, filed Oct. 5, 2001, and claims priority to European Patent Application No. 00 122 026.8, filed Oct. 10, 2000.
1. Field of the Invention
The present invention relates to a method to perform a cycle synchronization between interconnected sub-networks and a cycle synchronizator adapted to perform said method.
2. Discussion of the Background
It is known to interconnect sub-networks, e.g. with long delay bi-directional connections to extend a network to a wider area. In particular, this technique is used to interconnect several IEEE 1394 serial buses to extend an IEEE 1394 network, e.g. through a whole house. The basic topology of such a connection is shown in
Independent IEEE 1394 buses must be synchronized to have the same cycle rate. In particular, the IEEE 1394 standard mandates that for opened isochronous channels an isochronous packet is sent in every isochronous cycle. To ensure that isochronous transfers between the interconnected IEEE 1394 buses work, it must be ensured that all buses have the same frequency of isochronous cycles.
Therefore, it is the object underlying the present invention to provide a method to perform a cycle synchronization between interconnected sub-networks and a cycle synchronizator adapted to perform said method.
The method according to the present invention is defined in independent claim 1 and the cycle synchronizator according to present invention is defined in independent claim 12. Preferred embodiments thereof are respectively defined in the dependent subclaims.
The method to perform a cycle synchronization between interconnected sub-networks according to the present invention is characterized in that a reference node connected to one of the sub-networks transmits a respective cycle time information to cycle masters of all other sub-networks at recurring time instants, and the cycle masters of all other sub-networks adjust their cycle time accordingly.
Therewith, the present invention offers a method to synchronize several interconnected sub-networks which is independent of the connection between the sub-networks, since with the transmission of cycle time information of a reference node no relying on a clock frequency used for the transmission through the connection through sub-networks is necessary. After reception of the cycle time information each cycle master of the other sub-networks can adjust their cycle time accordingly so that in turn the cycle frequency in an IEEE 1394 serial bus connected to a respective cycle gets adjusted. Therefore, in a network with N sub-networks N−1 cycle masters are required to adjust their cycle time and the remaining sub-network has to comprise the reference node transmitting its time information to the N−1 cycle masters of the other sub-networks. Preferably, the reference node and the cycle masters are arranged within a respective interface of the sub-network which is connected to the interconnection of all sub-networks.
According to the present invention an adjustment of the cycle time within a cycle master might be performed by the following steps: Determining a first time interval in-between two receptions of cycle time information from the reference node with an own clock, determining a second time interval in-between corresponding transmission of cycle time information from the reference node on basis of the received cycle time information, comparing the first and second time intervals and adjusting the own cycle time according to the comparison result. Therefore, a large scale integration is possible.
Further, the comparison of the first and the second time intervals according to the present invention might consider a preceding adjustment of the own cycle time, the adjustment of the own cycle time within a cycle master might be performed in a step-wise manner and/or the adjustment of the own cycle time within a cycle master might be performed by adjusting a local number of clocks within one cycle.
In particular, in the latter case the adjustment of the own cycle time within a cycle master is performed by setting the local number of clocks equal to an ideal number of clocks of one cycle in case the first time interval and the second time interval are identical, smaller than an ideal number of clocks of one cycle in case the first time interval is smaller than the second time interval and larger than an ideal number of clocks in case the first time interval is larger than the second time interval. In particular, these features enable a very easy and therefore reliable method to perform the cycle synchronization between interconnected sub-networks according to the present invention which is independent from the transmission method used in-between the sub-networks.
The stepwidth of setting the local number of clocks smaller or larger than the ideal number of clocks might be determined according to the difference of the first and second time intervals. In this case it is possible to determine how fast the sychronization should be achieved and/or to consider smaller and larger deviations of the cycle timers within the cycle masters.
According to the present invention preferably the cycle time information transmitted by the reference node is a content of its cycle time register. In this case the adjustment of the own cycle time within a cycle master is preferably performed by adjusting the average difference between a time interval of two transmissions of cycle time information of the reference node which is determined by subtracting two succeeding received contents of the cycle time register of the reference node and a time interval of two samplings of the own cycle timer which is determined by subtracting two succeeding sampled contents of the own cycle time register plus a corrective difference to be zero. Of course, also other than two succeeding transmissions could be used, but in this case the hardware design to realize a cycle synchronizator according to the present invention leads to an increased cost. Further preferably, the corrective difference corresponds to the preceding adjustment.
Further preferably, according to the present invention the recurring time instants are determined to a regular time interval with a small variation.
The cycle synchronizator according to the present invention is therefore characterized by a clock offset estimation means to determine a timing error of an own cycle timer, and a cycle adjustment loop receiving the timing error determined by said clock offset estimation means to adjust the own cycle timer to reduce its timing error. Preferably, a de-jitter filter is arranged in-between the clock offset estimation means and the cycle adjustment loop to filter said determined timing error.
Therefore, in case the present invention is applied to a distributed IEEE 1394 network, i.e. several IEEE 1394 serial buses which are regarded as sub-networks are interconnected, e.g. by a long delay, bi-directional connection provides advantages in that the cycle synchronization is based on free-running oscillators of the cycle masters and standard IEEE 1394 physical interfaces can be used, since the cycle synchronization is based on a timing error of the own cycle timer which can be determined on basis of the transmission of cycle time information of a reference node in the network. Additionally, the reference node does not need to be a cycle master, i.e. the reference node can be predetermined.
Further features and advantages of the present invention will be apparent from the following detailed description of an exemplary embodiment thereof taken in conjunction with the accompanying drawings, in which
The following preferred embodiment of the present invention is adapted to the IEEE 1394 standard. However, as mentioned above, the present invention is not restricted thereto.
Every IEEE 1394 node maintains cycle time information in a node. For example,
To allow for significant jitter to occur both on the transmitter and on the receiver side according to the present invention an optional filtering can be performed which limits the cycle length adjustment range to +/−1 clock and/or which uses a de-jitter filter.
After transmission, the receiving node samples its own local cycle timer at the instant when it receives the remote cycle time information. In the standard IEEE 1394 node, one cycle has a duration of 3072 clocks of a 24,576 MHz oscillator. According to the preferred embodiment of the present invention shown and described in the following, a cycle timer is used where the duration of the cycle can be adjusted to 3071, 3072 or 3073 clocks. However, a variable duration might also be implemented. The information of the remote and local cycle time registers is used to adjust the local number of clocks per cycle.
According to the preferred embodiment of the present invention a special phase locked loop as shown in
The cycle synchronizator shown in
In particular, the clock offset estimation means 1 receives the remote time which is supplied directly as minuent to a first adder 9 and via a first delay element 11 as subtrahend to the first adder 9. The first delay element 11 holds the preceding sample of the remote time, i.e. shows a FIFO-behaviour with a storage capacity of one sample. Therefore, the first adder 9 outputs a remote time delta, i.e. the time difference of the time in-between two samples of the time register of the reference node. This remote time delta is input as minuent to a second adder 5. Further, the clock offset estimation means 1 comprises the local cycle timer 3 of the cycle master. The local time output therefrom is input as minuent to a third adder 10 and via a second delay element 12 also as subtrahent to the third adder 10. The second delay element 12 shows the same delay T as the first delay element 11. Therefore, the third adder 10 outputs a local time delta corresponding in time to the remote time delta output by the first adder 9. This local time delta is input as subtrahent to the second adder 5 which outputs the timing error in clocks to the de-jitter filter 4 which inputs the filtered timing error in clocks to the cycle adjustment loop 2. Further, the local time delta output from the third adder 10 is input to a controller 7 which determines the number clock skips/inserts necessary on basis of an arithmetic operation subtracting the duration of a cycle in clocks for this period of time from that of an ideal cycle and multiplying the resulting difference by the quotient of the number of clocks between the previous sampling instant and this sampling instant with the duration of a cycle in clocks for this period of time.
The cycle adjustment loop 2 comprises a fourth adder receiving the timing error in clocks from de-jitter filter 4 as a first summand and the number of clock skips/inserts determined by the controller 7 as second summand to build their sum. This sum is supplied to an integrator 13 which outputs its integration result to a quantizer 6. The quantizer 6 determines whether the next cycle of the cycle timer 3 within the clock offset estimation means 1 should comprise 3071, 3072 or 3073 clocks. In case the integration result of the integrator 13 is smaller than −80 then the next cycle should comprise 3071 clocks, in case the integration result is bigger than 80 then the next cycle should comprise 3073 clocks and in case the output result of the integrator 13 equals to 80 the cycle should comprise 3072 clocks. This comparison introduces an hysteresis into the loop so that there are usually only differences of one clock in succeeding cycles, i.e. that there is usually no jump from 3071 to 3073, but either between 3072 and 3073 or between 3071 and 3072 clocks per cycle. Therefore, also another value than 80 cycles which equal to 10 ms might be used. The number of clocks output by the quantizer 6 is input to a third delay element 14 which also has the same delay T as the first delay element 11. The cycle duration output by the third delay element 14 is supplied to the controller 7 which determines the number of clock skips/inserts and to the cycle timer 13.
As mentioned above, the delay T of the first to third delay elements 11, 12, 14 are not fixed but depend on the reception of a transmitted remote time. Also, the delay T within the delay elements does not indicate a fixed or preset time, but that the sample and hold operation performed by the delay element is performed by all three delay elements simultaneously.
The phase locked loop for a cycle synchronization according to the preferred embodiment of the present invention shown in
Since without jitter or disturbances the delay of the transmission path between reference and cycle synchronizator is constant, the method according to the present invention uses exactly the time interval for the local and remote measurement. Since the respective oscillators used for the respective measurement might differ slightly with respect to their oscillation frequency, i.e. according to the IEEE 1394 standard +/−100 ppm are allowed, these measurements of local and remote time intervals do not give exactly the same number of clocks. The cycle synchronizator according to the present invention extracts the number of cycles n_cycles that have elapsed in the respective time interval and depending on the current cycle duration, the corrective number of clocks is set to be either +n_cycles, 0, or −n_cycles. Corrective values of −1, 0+1 per 3072 clocks as explained above is equivalent to an adjustment range of +/−166/3072=+/−325 ppm. Also larger corrective values might be used which—on the other hand—lead to higher local jitter and are therefore not preferred. Therefore, in the long run, the remote and local number of cycles are equalized.
As shown in
Since the IEEE 1394 serial bus is a self-configuring bus, it is necessary that the network reference node is automatically determined after each network reconfiguration, e.g. after the addition or removal of nodes.
In the first step 401, a first time interval (Δt1, Δt1′) is determined in-between two receptions of cycle time information from the reference node 30 with an own clock, in step 403 a second time interval (Δt2, Δt2′) is determined in-between two corresponding transmissions of cycle time information from the reference node 30 based on the received cycle time information, in step 405 the first time interval is compared to the second time interval, and in step 407 the own cycle length is adjusted according to the comparison result.
Therefore, according to the present invention the oscillator is not adjusted, but the number of clocks within one cycle. Therefore, a free-running oscillator can be used instead of a voltage controlled oscillator. This feature enables the integration of the cycle synchronization according to the present invention on a single chip. Further, as mentioned above, the present invention performs the cycle synchronization independently of the connecting channel in-between the different sub-networks, i.e. IEEE 1394 serial buses which basically need only slight modifications in that the cycle synchronizator according to the present invention has to be included into a respective cycle master of a sub-network. Further, the connection network needs no master clock, since one of the sub-networks serves as reference.
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|U.S. Classification||370/516, 370/503|
|International Classification||G06F1/14, H04L7/00, H04J3/06, H04L12/46|
|Cooperative Classification||H04J3/0655, H04L12/40078, G06F1/14, H04L12/4035|
|European Classification||G06F1/14, H04J3/06C1|