|Publication number||US7723781 B2|
|Application number||US 12/108,333|
|Publication date||May 25, 2010|
|Filing date||Apr 23, 2008|
|Priority date||Mar 15, 2004|
|Also published as||US7381595, US20050218406, US20080224205|
|Publication number||108333, 12108333, US 7723781 B2, US 7723781B2, US-B2-7723781, US7723781 B2, US7723781B2|
|Inventors||Pooran Chandra Joshi, Apostolos T. Voutsas, John W. Hartzell|
|Original Assignee||Sharp Laboratories Of America, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Referenced by (2), Classifications (23), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a Divisional of a pending patent application entitled, HIGH-DENSITY PLASMA OXIDATION FOR ENHANCED GATE OXIDE PERFORMANCE, invented by Pooran Joshi et al., Ser. No. 11/139,726, filed May 26, 2005, now U.S. Pat. No. 7,381,595 which is a Continuation-in-Part of the following applications:
HIGH-DENSITY PLASMA PROCESS FOR SILICON THIN-FILMS, invented by Pooran Joshi, Ser. No. 10/871,939, filed Jun. 17, 2004, now U.S. Pat. No. 7,186,663;
METHODS FOR FABRICATING OXIDE THIN-FILMS, invented by Joshi et al., Ser. No. 10/801,374, filed Mar. 15, 2004, now U.S. Pat. No. 7,087,537; and,
VERTICAL THIN-FILM TRANSISTOR, invented by Schuele et al., Ser. No. 10/831,424, filed Apr. 23, 2004, now U.S. Pat. No. 6,995,053. These applications, and their parent applications, are incorporated herein by reference.
1. Field of the Invention
This invention generally relates to the fabrication of integrated circuit (IC) devices, and more particularly, to a gate oxide and a method for forming the same using high-density plasma oxidation.
2. Description of the Related Art
The quality of polysilicon thin-films and the interface between silicon and silicon dioxide (Si/SiO2) layers are critical to the performance of thin-film transistors, MOS capacitors, and various ICs. The quality of the SiO2/Si interface is dependent upon the quality of the SiOx (where x is less than, or equal to 2) transition layer at the interface and the defects in the poly-Si layer. The general approach is to improve the quality of the SiOx transition layer at the Si/SiO2 interface. Defects in the poly-Si can also be passivated and the stoichiometry improved by oxidation and hydrogenation processes.
Although lower temperatures are generally desirable for any device fabrication process, they are especially critical in LCD manufacture, where large-scale devices are formed on a transparent glass, quartz, or plastic substrate. These transparent substrates can be damaged when exposed to temperatures exceeding 650 degrees C. To address this temperature issue, low-temperature Si oxidation processes have been developed. These processes use a high-density plasma source such as an inductively coupled plasma (ICP) source, and are able to form Si oxide with a quality comparable to 1200 degree C. thermal oxidation methods.
Various semiconductor devices require the deposition of SiO2, or other oxide thin-films, on structures that are planar or non-planar. For planar surfaces there is usually no problem in depositing uniform SiO2 thin-films over large areas in the fabrication of stable and reliable devices. However, for a device with vertical steps in the structure, such as shallow-trench isolation (STI), vertical thin-film transistors (V-TFTs), graded steps, or curved surfaces, it is important to deposit SiO2 films with sufficient step-coverage to maintain film integrity, device performance, and yield. Thermal oxide has proven to be the most suitable oxide from the step-coverage point of view. However, the low growth rates and high processing temperatures exceeding 800° C. make thermal oxidation unsuitable for low-temperature devices.
Plasma-enhanced chemical vapor deposition (PECVD) processes are suitable for the low temperature processing of the SiO2 thin-films. The electrical quality and the step-coverage of the PECVD deposited oxide thin-film is strongly dependent upon the processing conditions. It is possible to improve the step-coverage of the deposited oxide by decreasing the process temperature or varying the process chemistries and plasma process variables. However, any such attempt to improve the step-coverage results in a corresponding decrease in the oxide quality.
Low-temperature Si oxide deposition processes are also used to fabricate stepped structures, such as an interlevel interconnect via. Although step-coverage is improved by lowering the process temperatures, the quality of the resultant Si oxide is poor. Thus, good Si oxide step-coverage can conventionally be obtained in non-critical areas of an IC structure, such as a field oxide region for example. However, vertical thin-film transistors (V-TFTs) for example, requiring both a high quality Si gate oxide film and good step-coverage, have been difficult to fabricate.
Generally, a fixed oxide charge is a positive charge that remains after annealing out interface trap charges, and is caused as a result of a structural defect. These fixed oxide charges occur primarily within 2 nanometers of a Si/SiO2 interface. The charge density is dependent upon oxidation and hydrogenation processes. It is known that these fixed oxide charges can be minimized through the use of high oxidation temperatures. Fixed oxide charges in a gate oxide layer can act to degrade the threshold voltage of a transistor.
Oxide trapped charges can be formed at the interface between a silicon layer and a metal or Si substrate, or can be introduced throughout the oxide layer as a result of ion implantation. Mobile ionic charges can also be formed at the silicon oxide interface as a result of ionized alkali metals, sodium, or potassium. A gate insulator with any of the above-mentioned oxide charge types can degrade the threshold voltage, breakdown voltage, and current gain of a transistor.
It would be advantageous if a process could be developed to enhance Si/SiO2 interfaces at a significantly lower thermal budget and temperature.
It would be advantageous if a low-temperature process could be developed that permitted the fabrication of step-covered Si oxide gate insulators.
It would be advantageous if the above-mentioned low-temperature process could reduce the oxide charge concentration in a gate insulator.
The present invention describes a high-density plasma oxidation process to improve the bulk and interfacial quality of Si oxide thin-films deposited on planar, stepped, graded, or curved surfaces. High-density plasma generated oxide radicals promote efficient oxidation of the oxide thin-films at significantly lower thermal budgets than the thermal or conventional plasma oxidation processes. In this manner, good oxide step-coverage is achieved simultaneously with good oxide quality and reliability.
More specifically, the present invention describes a low temperature (<400° C.) high-density plasma oxidation process to improve the oxidation state of oxide thin-films. The oxidation state, and oxygen vacancies or defects are the major source of poor electrical performance of oxide or sub-oxide thin-films. The conventional approach to improve the oxidation state of oxide thin-films is to expose them to an oxygen atmosphere at elevated temperatures. However as mentioned above, the thermal oxidation process is not suitable for low temperature devices due to high temperatures and large thermal budgets. Likewise, conventional PECVD processes can be used to improve the oxidation state of deposited oxides. However, the conventional capacitively coupled plasma-based processes have high thermal budgets due to low plasma concentration and energy. Structural damage can occur as a result of attempting to enhance the reaction kinetics by increasing the plasma power, which results in a corresponding increase in the sheath potential.
The present invention plasma oxidation process further addresses the issue of step-coverage for V-TFT devices, which require high step-coverage oxide processes to obtain uniform deposition on the top and side faces, which are perpendicular to each other. The step-coverage of conventional PECVD processes depends on the nature of precursor, process temperatures, and the plasma processing conditions. In general, any conventional attempt to improve the step-coverage results in a degradation of the electrical performance. The present invention post-deposition high-density plasma oxidation process enhances the bulk and interfacial quality of the oxide thin-film, even though the film has been deposited at low temperatures to achieve high step-coverage on graded or abrupt transition surfaces.
Accordingly, a method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions.
When the silicon oxide thin-film gate insulator is deposited overlying the gate, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained (comparing the gate top surface to gate sidewalls). These results can be obtained for Si oxide thin-film thicknesses of less than 50 nanometers (nm). For example, the Si oxide thin-film can be deposited using a PECVD process with tetraethylorthosilicate (TEOS) precursors.
Another benefit of the high-density plasma oxidation process is a decrease in the concentration of oxide charge in the gate insulation layer. Given a Si oxide thin-film with a thickness in the range of about 10 to 50 nm, an oxide charge concentration of less than 5×1011 per square centimeter (cm−2) can be obtained.
Additional details of the above-described method, a method for forming Si oxide thin-films on substrates with abrupt transitions, and V-TFT devices are presented below.
A gate 106, having vertical sidewalls 108 and a top surface 110, overlies the substrate insulation layer 104. A silicon oxide thin-film gate insulator 112 overlies the gate top surface 110 and sidewalls 108. The gate insulator 112 has a step-coverage of greater than 65%. Step-coverage is defined as the ratio of a vertical aspect thickness 113 a, to a planar (horizontal) thickness 113 b. As shown, the oxide thickness 113 a over the sidewalls 108 is being compared to the oxide thickness 113 b over the gate top surface 110. Poor step-coverage results in a relatively thin layer of oxide overlying corner and abrupt transition regions. If used as a gate oxide, these “thin” regions are prone breakdown. Thus, step-coverage is an important consideration in the fabrication of V-TFTs, or any active device using an oxide-covered abrupt transition surfaces.
A first source/drain region 114 overlies the gate top surface 110. A second source/drain (S/D) region 116 overlies the substrate insulation layer 104, adjacent a first gate sidewall 108 a. A channel region 118 overlies the first gate sidewall 108 a, interposed between the first S/D region 114 and the second source/drain region 116.
Note, although the sidewalls 108 have been described as vertical with respect the horizontal surface of the substrate 102, in other aspects not shown, the sidewalls can be graded or curved. That is, the sidewalls 108 need not be perpendicular to the substrate surface. Although not specifically shown in the figure, additional layers of insulator may be used to separate gate top surface 110 from the first S/D region 114.
A gate 206, having vertical sidewalls 208 and a top surface 210, overlies the substrate insulation layer 204. A silicon oxide thin-film gate insulator 212 overlies the gate top surface 210 and sidewalls 208.
A first source/drain region 214 overlies the gate top surface 210. A second source/drain (S/D) region 216 overlies the substrate insulation layer 204, adjacent a first gate sidewall 208 a. A channel region 218 overlies the first gate sidewall 208 a, interposed between the first S/D region 214 and the second source/drain region 216.
The silicon oxide thin-film gate insulator 212 has a thickness 220 in the range of about 10 to 50 nm and an oxide charge concentration of less than 5×1011 per square centimeter (cm−2). As used herein, oxide charge concentration refers to the combination of oxide fixed charges, oxide trapped charges, and mobile (ionic) charges. Since perfect step-coverage is difficult to achieve, the thickness 220 is being defined with respect to oxide 212 overlying the gate top surface 210, which is potentially thicker than the Si oxide overlying the sidewalls 208.
The invention describes a novel high-density plasma oxidation process, employing an inductively coupled plasma source, for the post-deposition oxidation of oxide thin-films at process temperatures lower than 400° C. The high-density plasma process is effective in the efficient generation of oxygen radicals to effectively improve the oxidation state of an oxide film, enhancing its electrical performance.
High-Density Plasma System
The HD plasma oxidation processes are effective in minimizing impurities incorporated in the films during deposition at low processing temperatures, as well as impurity-related bonds in the films. This is possible because plasma density and energy levels are higher for the HD-PECVD process than those for conventional PECVD processes.
High-Density Plasma Oxidation Process
The high-density plasma oxidation process described in this invention has been successfully used for the low temperature oxidation of Si films. Further, a high-density plasma growth process, with high SiO2 growth rates at temperatures lower than 400° C., can be used where conventional thermal growth is impractical. The plasma-grown SiO2 thin-films (grown at 350° C.) have a high quality, comparable to thermal oxides grown at temperatures of higher than 800° C.
Step-Coverage and Oxide Quality Improvement
The electrical parameter that is most sensitive to the deposition temperature is the flat band voltage. A higher flat band voltage reflects more fixed oxide charges in the film, and high oxide charges in the interface degrade TFT performance. A lower flat band voltage is desired to make high performance TFT devices. The high-density plasma oxidation process brings the flat band voltage to the levels obtained using a high temperature deposition process (400° C.).
The flat band voltage of a 50 nm thick SiO2 film (TEOS oxide) is below −2V after a plasma oxidation treatment. The flat band voltage of SiO2 (TEOS oxide) samples at thicknesses of less than 30 nm is below −1V after high-density plasma oxidation. Generally, flat band voltage depends on the type of oxide material and the metal/oxide work function difference.
Generally, any kind of oxide deposition at a temperature of 400° C., or greater, produces an oxide of acceptable quality. However, for TEOS oxide the film properties change very rapidly with temperature and the typical processing temperature is 400° C., or lower. The quality of a TEOS oxide deposited at a temperature of 350° C. is still sufficiently good for some applications, but not as a gate oxide. However, the properties of TEOS oxide degrade rapidly at temperatures below 350° C.
For TEOS oxide films, an improvement in the flat band voltage and the bias temperature stress reliability can be obtained by practicing the present invention high-density plasma oxidation process. For oxide thin-films in general, the high-density plasma oxidation process yields improvement can be detected in the dielectric constant, flat band voltage, interface trap charges, leakage current, and breakdown field strength.
Alternately considered, the high-density plasma oxidation process decreases the concentration of oxide charges in the bulk of the dielectric film and at its top and bottom interfaces. The flat band voltage is dependent upon the effect of oxide charges. The flat band voltage value depends on the configuration (type of metal, type of Si), while the fixed charge concentration value does not depend on the configuration. So the fixed oxide charge concentration is a normalized parameter while flat band voltage is not. The oxide charges are typically confined to the Si/SiO2 interface but can also be located in the oxide film and the top metal/oxide interface. The term “oxide charges” has been used rather than “fixed oxide charges” as the contribution of all oxide charges is considered.
High-Density Plasma Oxidation of Oxides
The high-density plasma oxidation process described in this invention can be used for post-deposition oxygen plasma treatment of any oxide to improve its bulk and interfacial properties. The oxygen vacancies and defects are the major factors dictating the oxide quality and reliability for electronic devices. The high-density plasma oxidation process offers significantly lower thermal budgets for oxidation compared to standard oxidation approaches.
Top Electrode Power
13.56-300 MHz, up to 10 W/cm2,
Bottom Electrode Power
50 KHz-13.56 MHz, up to 3 W/cm2
O2/Inert Gas, O2: 0-20%
High-density plasma oxidation processes for post-deposition oxidation treatment of oxide thin-films.
Generally, the present invention has been presented in the context of improving the quality of an oxide film, deposited at a low temperature, overlying a surface with an abrupt transition. However, the invention is also applicable to oxide grown on so-called planar surfaces. As the gate oxide thickness decreases below 50 nm, step-coverage becomes an issue even for the “planar” devices, as there are also steps in planar device surfaces. If deposition temperatures are reduced to improve the TEOS oxide step-coverage, then the principle of combining low temperature TEOS oxide+HDP (high-density plasma) oxidation becomes applicable to planar devices.
Step 1002 forms a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer. Step 1004 deposits a silicon oxide thin-film gate insulator overlying the gate. In some circumstances, Step 1004 deposits the silicon oxide at a temperature of less than 400 degrees C. Step 1006 plasma oxidizes the gate insulator at a temperature of less than 400° C., using a high-density plasma source. Step 1008 forms a first source/drain region overlying the gate top surface. Step 1010 forms a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall. Step 1012 forms a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions.
In one aspect, depositing the silicon oxide thin-film gate insulator overlying the gate in Step 1004 includes forming a Si oxide layer having a step-coverage of greater than 65%, comparing the gate top surface to gate sidewalls. In another aspect, Step 1004 deposits a layer of Si oxide over the gate top surface having a thickness of less than 50 nm. In one other aspect, Step 1004 uses a plasma-enhanced chemical vapor deposition (PECVD) process with tetraethylorthosilicate (TEOS) precursors to deposit the Si oxide.
In one aspect, plasma oxidizing the gate insulator in Step 1006 includes using an inductively coupled plasma (ICP) source with the following substeps (not shown), see Table 1 above. Step 1006 a supplies power to a top electrode at a frequency in the range of 13.56 to 300 MHz, and a power density of up to 10 W/cm2. Step 1006 b supplies power to a bottom electrode at a frequency in the range of 50 kilohertz to 13.56 MHz, and a power density of up to 3 W/cm2. Step 1006 c uses an atmosphere pressure in the range of 1 to 500 mTorr. Step 1006 d supplies an oxygen gas.
In one aspect, supplying an oxygen gas in Step 1006 d includes: mixing O2 and an insert gas in a ratio in the range of 0 to 20%; and, using an inert gas such as He, Ar, or Kr. Then, the method further comprises Step 1006 e, which oxidizes for a duration in the range of 1 to 60 minutes. Alternately, Step 1006 d includes supplying oxygen gas from a source such as N2O, O2, or O3.
In one aspect of the method, Step 1007 decreases the concentration of oxide charge in the gate insulation layer. For example, if Step 1004 deposits a layer of Si oxide over the gate top surface having a thickness in the range of about 10 to 50 nm, then Step forms an oxide charge concentration of less than 5×1011 cm−2.
In a different aspect, Step 1005 a introduces an oxygen species using an ion source, simultaneous with the plasma oxidation of Step 1006. That is, plasma oxidizing the gate insulator at a temperature of less than 400° C. in Step 1006 includes plasma oxidizing the gate insulator at least partially in response to the oxygen species. In one aspect, Step 1005 a controls the energy of the oxygen species impinging on the gate insulator in response to the low frequency bias applied to the bottom electrode (Step 1006 b).
In another aspect, Step 1005 b irradiates the gate insulator with an energy source such as a light source or a laser beam, simultaneous with the plasma oxidation of Step 1006. That is, plasma oxidizing the gate insulator at a temperature of less than 400° C. in Step 1006 includes plasma oxidizing the gate insulator at least partially in response to the energy source of Step 1005 b.
In one aspect, depositing the Si oxide thin-film gate insulator in Step 1004 includes depositing a layer of Si oxide over the substrate surface having a thickness of less than 50 nm. In another aspect, the Si oxide is deposited using a PECVD process with TEOS precursors.
In one aspect, plasma oxidizing the silicon oxide thin-film in Step 1006 includes using an ICP source as follows: supplying power to a top electrode at a frequency in the range of 13.56 to 300 MHz, and a power density of up to 10 W/cm2; supplying power to a bottom electrode at a frequency in the range of 50 kilohertz to 13.56 MHz, and a power density of up to 3 W/cm2; using an atmosphere pressure in the range of 1 to 500 mTorr; and, supplying an oxygen gas.
The oxygen gas can be O2 mixed with an insert gas in a ratio in the range of 0 to 20%. The inert gas can be He, Ar, or Kr. Then, the plasma oxidation process further comprises oxidizing for a duration in the range of 1 to 60 minutes. Alternately, the oxygen gas can be N2O, O2, or O3.
In a different aspect, Step 1105 a introduces an oxygen species using an ion source, simultaneous with the plasma oxidation of Step 1106. That is, plasma oxidizing the Si oxide thin-film at a temperature of less than 400° C. in Step 1106 includes plasma oxidizing the Si oxide at least partially in response to the oxygen species. In one aspect, Step 1105 a controls the energy of the oxygen species impinging on the Si oxide thin-film in response to the low frequency bias applied to the bottom electrode.
In another aspect, Step 1105 b irradiates the Si oxide thin-film with an energy source such as a light source or a laser beam, simultaneous with the plasma oxidation of Step 1106. That is, plasma oxidizing the Si oxide thin-film in Step 1106 includes plasma oxidizing the Si oxide film at least partially in response to the energy source of Step 1105 b.
A high-density plasma oxidation method has been presented along with some oxide-covered structures that benefit from this process. Some details of specific materials and fabrication steps have been used to illustrate the invention. However, the invention is not limited to merely these examples. Other variations and embodiments of the invention will occur to those skilled in the art.
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|U.S. Classification||257/329, 257/E27.057, 257/E27.056|
|International Classification||H01L21/84, H01L21/336, H01L29/78, H01L29/786|
|Cooperative Classification||C23C16/24, C23C16/509, H01L21/31612, C23C16/45523, H01L21/049, H01L29/66666, H01L29/6675, H01L29/78642|
|European Classification||H01L29/66M6T6F15A, H01L29/66M6T6F12, C23C16/509, C23C16/24, C23C16/455F, H01L21/316B2B, H01L21/04H10B, H01L29/786C|
|Jun 8, 2010||AS||Assignment|
Owner name: SHARP KABUSHIKI KAISHA,JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHARP LABORATORIES OF AMERICA INC.;REEL/FRAME:024492/0628
Effective date: 20100608
|Nov 12, 2013||FPAY||Fee payment|
Year of fee payment: 4