US 7725800 B2 Abstract Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.
Claims(8) 1. A data storage apparatus that decodes encoded data to perform error correction, wherein the data storage apparatus comprises:
means for generating syndrome values for error events in an input sequence using a first error correction code;
means for generating reliability information by selecting a most likely error event for each span of a symbol in the input sequence having a minimum error metric value among the error events that have a first syndrome value, and by selecting a most likely error event for each span of the symbol in the input sequence having a minimum error metric value among the error events that have a second syndrome value;
means for applying a second error correction code to provide corrected syndrome values using the reliability information; and
means for selecting a most likely symbol corresponding to an error event having a smallest error metric value among the error events having syndrome values consistent with the corrected syndrome values.
2. The data storage apparatus defined in
means for generating error metric values each indicating a probability that a set of error values in the input sequence is caused by one of a set of error events.
3. The data storage apparatus defined in
4. The data storage apparatus defined in
5. The data storage apparatus defined in
means for performing error correction on the most likely symbol using a Reed-Solomon decoding technique.
6. The data storage apparatus defined in
7. The data storage apparatus defined in
means for grouping at least a subset of the most likely error events into potentially valid sets of the most likely error events such that each of the potentially valid sets of the most likely error events has one error event for each span of a symbol and each of the potentially valid sets of the most likely error events has syndrome values that form a codeword of the second error correction code; and
means for selecting one of the potentially valid sets of the most likely error events that has a minimum total error metric value among the potentially valid sets of the most likely error events.
8. The data storage apparatus defined in
means for generating most likely symbols by applying the most likely error events to symbols in the input sequence,
wherein the means for selecting a most likely symbol corresponding to an error event having a smallest error metric value among the error events having syndrome values consistent with the corrected syndrome values further comprises means for selecting the most likely symbol from among the most likely symbols such that the most likely symbol corresponds to an error event having a smallest error metric value among the error events having syndrome values consistent with the corrected syndrome values.
Description The present invention relates to techniques for performing error correction decoding in data recording systems, and more particularly, to techniques for performing error correction using decoders that process soft information. When a data sequence is read from a magnetic hard disk using a hard disk drive, the data sequence can be estimated by running the signal samples at the output of the channel through a trellis sequence detector. The trellis sequence detector computes a most likely input sequence associated with the signal samples. The most likely input sequence is the sequence through a trellis that is closest to the signal samples in Euclidean space. A trellis diagram represents a time sequence of sample values and the possible recorded input sequences that could have produced the sample sequence. A Viterbi detector is a trellis sequence detector that finds the most likely trellis path among all possible trellis paths in a trellis diagram based on a metric value associated with each trellis path. When a long parity code is used, it becomes very complex to implement a Viterbi detector so as to enforce the parity code constraints along the trellis, because the number of trellis states of the Viterbi detector increases exponentially with the number of parity bits in the parity code. A parity post processor (PPP) is a signal processing module added to a conventional Viterbi detector to enforce a parity code constraint and/or to re-compute more accurate trellis path metric values based on a longer target polynomial than the one used by the Viterbi detector. Among all the trellis paths that the PPP evaluates, the PPP picks the trellis path that also satisfies the parity constraint and makes corrections to the Viterbi output accordingly. Synthetic waveform block Two paths through the trellis that differ in a single bit, differ in multiple sample values. Filter The output of Viterbi detector Block This error event can only occur if the detected data contains a string of five alternating bit values 10101 or 01010. Therefore, a sliding window of five bits is examined, and the error event is declared valid with positive sign if the detected data in the window is 10101 and valid with negative sign if it is 01010. When an error event occurs near the edge of a codeword, bits in an adjacent codeword must be examined in order to qualify the error event. Error event pattern matching block Error event pattern matching block Error event pattern matching block Error event pattern matching block Most likely error event generator block Error correction is then applied to the preliminary detected binary sequence to correct the error based on the most likely error event selected in block Hard-decision decoding takes binary bits as input, assumes all bits are equally likely to be in error, and decodes by flipping as few bits as possible to produce a valid codeword. Hard decoding uses special algebraic properties of the code to decode efficiently, even for very powerful codes. One type of two-stage decoder uses a hard-decoded tensor product code, where the second component code of the tensor product code is a hard-decoded BCH code. Reed Solomon ECC decoding is another example of hard-decision decoding. Because hard decision decoding assumes all bits are equally likely to be in error, it does not consider that some bits are more reliable than others. Error correction can also be performed by soft-decision decoding. Soft-decision decoding receives input analog data (e.g., an equalized read-back signal or bit reliability information) and preferentially flips unreliable bits. Soft-decision decoding out-performs hard-decision decoding, because it is able to exploit the fact that some bits are more reliable than others. However, it can be difficult to decode powerful codes efficiently using soft decoding. Also, existing soft-decoded parity codes span multiple Reed-Solomon (RS) symbols. Therefore, it would be desirable to provide error correction decoding techniques with greater performance and reliability. The present invention includes systems and methods for error correction decoding. Two levels of error correction decoding are performed using a first level decoder and a second level decoder. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon (RS) symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected. The present invention represents a substantial improvement over many prior art techniques, because it allows soft decoding of the outer component code. Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures. In many data storage or communications systems, two separate codes are combined to form a composite code. The most common method of combining two component codes is simple concatenation. In simple concatenation, the composite codeword consists of a sequence of smaller blocks. Each of the smaller blocks is a codeword of an inner component code. The sequence of blocks is a codeword of an outer component code. Simple concatenation combines two component codes to form a composite code that has stronger error correcting capabilities than either component code. However, the composite code incurs the parity overhead of both component codes. Encoding proceeds by first encoding the data blocks using the outer component code by adding outer parity blocks. Then, every block is encoded using the inner component code by adding inner parity bits within each block. Decoding proceeds by first decoding each block using the inner component code decoder. The inner component code decoder corrects all errors in blocks with only a few bits in error. The resulting sequence of blocks is then decoded using the outer component code decoder. The outer component code decoder corrects blocks that were decoded incorrectly by the inner component code decoder. Another method for combining two component codes known in the prior art is generalized concatenation. As with simple concatenation, the composite codeword consists of a sequence of smaller blocks. The blocks are not codewords of the inner component code. The degree to which each block deviates from the parity rules of the inner component code is called the syndrome for that block. The outer component code does not operate over the sequence of blocks as such, but rather the sequence of syndromes is a codeword of the outer component code. Encoding proceeds by computing the inner component code syndrome for blocks corresponding to data elements of the outer component code. The outer component code encoder then computes the syndromes required for the remaining blocks in order for the complete sequence of syndromes to form a valid codeword of the outer component code. These remaining blocks correspond to parity elements of the outer component code. For the remaining blocks, parity bits are added to force the syndrome to the required value. Decoding proceeds by first computing the inner block syndrome for each block. The sequence of syndromes is then decoded using the outer component code decoder. Each block is then decoded again using the inner component code decoder and the corresponding syndrome value given by the outer component code decoder. According to an embodiment of the present invention, a decoder receives data encoded by combining three component codes to form a composite code. First, two codes are combined by generalized concatenation to form a first composite code. The first composite code is then used as the inner code in simple concatenation with an outermost error correction code to form a second composite code. For example, a simple parity code can be concatenated with a BCH code to form a composite tensor product parity code that is then concatenated with a Reed-Solomon outermost error correction code. It should be understood that the principles of the present invention can decode data that has been encoded using composite codes formed by combining different component codes in a similar fashion. According to the present invention, soft decoding is performed to correct errors in a data stream. The parity post processor (PPP) of In the system of The tensor symbols are encoded by a tensor product parity code. Although tensor product parity codes are used to illustrate the present invention, it should be understood that the principles of the present invention can be applied to any composite code. Tensor product parity codes are merely one type of composite codes. Error event pattern matching block The PPP also includes soft information generator Most likely error event generator In block Block Block The end result is a set of soft information generated by block The soft information is also referred to as reliability information. The soft information is used to select the most likely value for each tensor symbol, as will now be described in further detail with respect to Soft information generator According to an embodiment of the present invention, the preliminary binary detected sequence is a series of symbols generated by an encoder that encodes data using a composite code. As described above, a composite code is a combination of an inner component code and an outer component code. First level decoder The soft information is transmitted to a second level decoder A tensor product parity code (TPPC) is constructed by combining two smaller error correcting codes. The parity check matrix of a TPPC is derived by taking the tensor product of the parity check matrices for the two smaller codes. For example, a TPPC code can be the tensor product of a short parity code and a low density parity check (LDPC) code. The two smaller codes are referred to as a first parity code and a second parity code. The tensor symbols can be, for example, Reed-Solomon (RS) symbols, RS symbol combinations, or RS symbol splits. RS symbol combinations are combinations of RS symbols or combinations of RS symbols with extra bits. RS symbol splits are parts of split RS symbols. Block The syndrome values for the correct error event must form a codeword of the outer component code. Second level decoder Second level decoder The second level decoder block The error events output by block The total error metric value for a potentially valid set of error events can be computed by combining the error metrics of each error event in the set. If the error metric values are logarithms of probabilities, the total error metric value for a potentially valid set of independent error events can be computed by adding together the error metrics for each error event in the set. Second level decoder The most likely tensor symbol for each error event output by block Multiplexer The most likely tensor symbol is then transmitted to Reed-Solomon (RS) decoder Error signal generator Parity post processor The soft information is transmitted to tensor parity error correction block A second parity post processor (PPP) PPP Blocks The advantage of the The foregoing description of the exemplary embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. A latitude of modification, various changes, and substitutions are intended in the present invention. In some instances, features of the invention can be employed without a corresponding use of other features as set forth. Many modifications and variations are possible in light of the above teachings, without departing from the scope of the invention. It is intended that the scope of the invention be limited not with this detailed description, but rather by the claims appended hereto. Patent Citations
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