US 7730118 B2 Abstract An arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, including a multiplier, addition circuitry, a result register, and accumulator circuitry. The multiplier arranged to receive first and second operands and operable to generate multiplication terms. The addition circuitry for receiving multiplication terms from the multiplier and operable to combine them to generate a multiplication result. The result register for receiving the multiplication result from the adder. The accumulator circuitry connected to receive a value stored in the result register and an accumulate control signal which determines whether the arithmetic unit implements a multiply or a multiply-accumulate instruction.
Claims(22) 1. An arithmetic unit comprising:
a multiply-accumulate circuit having first and second operand inputs and an accumulator input;
an first addition circuit to receive multiply-accumulate terms from the multiply-accumulate circuit and to generate a multiply-accumulate result;
a result register to receive the multiply-accumulate result from the first addition circuit; and
an accumulator circuit to receive an accumulate signal and a current contents the result register,
wherein the accumulator circuit is coupled to the accumulator input of the multiply-accumulate circuit and the accumulator input receives the current multiply-accumulate result from the result register when the accumulate signal is asserted and does not receive the current multiply-accumulate result of the result register when the accumulate signal is not asserted.
2. The arithmetic unit of
a multiply circuit to receive the first and second operand inputs; and
a second addition circuit to receive the accumulator input and multiplication terms from the multiply circuit and to generate the multiply-accumulate terms.
3. The arithmetic unit of
the first and second operand inputs comprise first and second numbers of bits, respectively;
the multiply circuit generates a number of multiplication terms equal to a sum of the first and second numbers of bits; and
the second addition circuit comprises a number of full adders equal to the number of multiplication terms.
4. The arithmetic unit of
5. The arithmetic unit of
6. The arithmetic unit of
7. The arithmetic unit of
8. A processor comprising:
an instruction memory;
a fetch-decode block to fetch instructions from the instruction memory; and
an execution stage to execute multiply and multiply-accumulate instructions received from the fetch-decode block, wherein the execution stage includes an arithmetic unit comprising:
a multiply-accumulate circuit having first and second operand inputs and an accumulator input;
a first addition circuit to receive multiply-accumulate terms from the multiplier circuit and to generate a multiply-accumulate result;
a result register to receive the multiply-accumulate result from the first addition circuit; and
an accumulator circuit to receive an accumulate signal and the multiply-accumulate result from the result register,
wherein the accumulator circuit is coupled to the accumulator input and the accumulator input of the multiply-accumulate circuit receives the multiply-accumulate result from the result register when the accumulate signal is asserted.
9. The processor of
a multiply circuit to receive the first and second operand inputs; and
a second addition circuit to receive the accumulator input and multiplication terms from the multiply circuit and to generate the multiply-accumulate terms.
10. The processor of
the first and second operand inputs comprise first and second numbers of bits, respectively;
the multiply circuit generates a number of multiplication terms equal to a sum of the first and second numbers of bits; and
the second addition circuit comprises a number of full adders equal to the number of multiplication terms.
11. The processor of
12. The processor of
13. The processor of
14. The processor of
15. The processor of
16. A method of operating an arithmetic unit having first and second operand inputs, an accumulate signal input and a result register, and method comprising:
providing an accumulator input, wherein the accumulator input is equal to a current multiply-accumulate result of the result register when the accumulate signal input is asserted and does not equal the current multiply-accumulate result of the result register when the accumulator signal input is not asserted;
performing a multiply-accumulate operation on the first and second operand inputs and the accumulator input to generate multiply-accumulate terms;
adding the multiply-accumulate terms to generate a multiply-accumulate result; and
loading the multiply-accumulate result into the result register.
17. The method of
inputting zero values to the first and second operand inputs;
asserting the accumulate signal input; and
storing the current multiply-accumulate result of the result register as the accumulated result after performing the steps of performing a multiply-accumulate operation, adding the multiply-accumulate terms, and loading the multiply-accumulate result into the result register.
18. The method of
inputting the specified accumulator value to the first operand input and a value of one to the second operand input;
setting the accumulate signal input to an unasserted value; and
performing the steps of performing a multiply-accumulate operation, adding the multiply-accumulate terms, and loading the multiply-accumulate result into the result register.
19. The method of
multiplying the first and second operands to generate a number of multiplication terms equal to a sum of the first and second numbers of bits; and
adding the multiplication terms and the accumulator input with a number of full adders equal to the number of multiplication terms to generate the multiply-accumulate result.
20. The method of
multiplying the first and second operands with a Booth recoding circuit; and
adding the multiplication terms and the accumulator input with a Wallace tree circuit to generate the multiply-accumulate result.
21. The method of
the accumulator input is equal to a current multiply-accumulate result of the second result register when the accumulate signal input is asserted;
the first result register is loaded in response to a first clock signal; and
the second result register is loaded in response to a second clock signal,
wherein the second clock signal is active only when the arithmetic unit is performing a multiply-accumulate operation.
22. A method of implementing a multiply instruction in a processor, the method comprising:
executing a first instruction to retrieve an accumulator result from a result register of an arithmetic unit in the processor;
executing a multiply instruction to supply a first operand and a second operand to the arithmetic unit, the arithmetic unit configured to generate a multiplication result;
transferring the multiplication result to a destination register of the processor; and
executing a second instruction to load an accumulator value into the arithmetic unit.
Description The present invention relates to a multiply-accumulate unit for selectively implementing multiply and multiply-accumulate operations. Multiply-accumulate (MAC) operations are required in processor cores. Multiply-accumulate is an important and expensive operation. It is frequently used in digital signal processing and video/graphics applications. As a result, any improvement in the delay for performing this operation has a significant impact on various aspects of processor performance. The cost of providing the third register Reg There exists units which can implement MUL and MAC instructions, for example as described in the following. United States Publication No. US2003/0172101 describes a multiply-accumulate unit (MAC) for use in a processor based system. The MAC includes control logic that allows it to implement multiply or multiply-accumulate instructions. XP 001221317 (“A High Performance and Low-Power 32-bit Multiply-Accumulate Unit With Single-Instruction-Multiple-Data (SIMD) Feature”) describes a multiply-accumulate unit (MAC) that is capable of implementing multiply and multiply-accumulate instructions. U.S. Pat. No. 5,436,860 describes a multiply-accumulate unit that wherein the multiply-accumulate circuitry is reused to provide barrel shifter functionality. To address the above-discussed deficiencies of the prior art, it is an aim of the invention to provide a MUL-MAC unit with lower power and lower chip overhead than has been available until now. According to an aspect of the present invention there is provided an arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, comprising: a multiplier arranged to receive first and second operands and operable to generate multiplication terms; addition circuitry for receiving multiplication terms from the multiplier and operable to combine them to generate a multiplication result; an output register for receiving the multiplication result from the adder; and accumulator circuitry connected to receive a value stored in the result register and an accumulate control signal which determines whether the arithmetic unit implements a multiply or a multiply-accumulate instruction; said result register being arranged to hold the result of a multiply instruction for retrieval when a multiply instruction is implemented and to be overwritten with an accumulator result when a multiply-accumulate instruction is implemented. A further aspect of the invention provides a processor including such an arithmetic unit and an execution unit arranged to execute a first instruction to retrieve an accumulator result from the result register and a second instruction to load an accumulator value into the arithmetic unit. Another aspect of the invention provides a method of operating an arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, the method comprising: supplying first and second operands to a multiplier operable to generate multiplication terms; supplying the multiplication terms to addition circuitry operable to generate a multiplication result; storing the multiplication result in a result register of the arithmetic unit; supplying a value stored in the result register to accumulator circuitry; and selectively operating an accumulate control signal supplied to the accumulator circuitry to determine whether the arithmetic unit implements a multiply or a multiply-accumulate instruction; wherein when a multiply instruction is implemented the result of a multiply instruction is retrieved from the result register and when a multiply-accumulate instruction is implemented, the value in the result register is overwritten with an accumulator result. A further aspect of the invention provides a method of implementing a multiply instruction in a processor, the method comprising: executing a first instruction to retrieve an accumulator result from a result register of an arithmetic unit in the processor; executing a multiply instruction which causes first and second operands to be supplied to the arithmetic unit which is operable to generate a multiplication result; transferring the multiplication result from the result register to a destination register of the processor; and executing a further instruction to load an accumulator value into the arithmetic unit in readiness for a subsequent multiply-accumulate instruction. The advantage of the inventive claim is the use of a single register for holding results, and also as an accumulator for a MAC instruction. Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “processor” may mean any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular apparatus or controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such definitions words and phrases. For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings, in which like reference numerals represent like parts, and in which: In the multiply-accumulate unit of The accumulator gates The provision of a local accumulator function has the effect that the result of previous multiply or multiply-accumulate instructions can be added into future multiply-accumulate instructions, providing the required accumulation. If a MUL operation is to be implemented, the clock CLK The second result register Reg R This design represents an improvement over the design of The removal of the second result register in the embodiment of Conversely, an accumulator value can be set in the result register Reg R prior to a MAC operation by executing the instruction:
Using these two instructions means that the multiply-accumulate unit can switch between operating as a multiplier and a multiply-accumulate unit. When the multiply-accumulate unit result needs to be removed so that the unit can operate as a multiplier, the first of the above-referenced instructions is implemented. When the unit ceases to be used as a multiplier and needs to be used again as a multiply-accumulate unit, the initial accumulator value can be set using the second of the above-referenced instructions. The design of A still further improvement can be made which will now be described with reference to One example of a multiplier configuration which will allow this optimisation is illustrated in The fourth level of the Wallace tree comprises two 3 bit adders It can be seen from the above that each column of the Wallace tree has two spare inputs, one, By introducing the value to the accumulator directly into the Wallace tree construction, no full adders are needed to achieve the multiply-accumulate operation. The first and second instructions for removing the accumulated value and resetting the accumulated value as described above in relation to the embodiment of The above-described embodiments of Patent Citations
Non-Patent Citations
Classifications
Rotate |