Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS7732331 B2
Publication typeGrant
Application numberUS 10/998,229
Publication dateJun 8, 2010
Filing dateNov 26, 2004
Priority dateDec 6, 2000
Fee statusPaid
Also published asUS6936535, US20020187631, US20050101132, WO2002067319A2, WO2002067319A3, WO2002067319A8
Publication number10998229, 998229, US 7732331 B2, US 7732331B2, US-B2-7732331, US7732331 B2, US7732331B2
InventorsKi-Bum Kim, Pekka J. Soininen, Ivo Raaijmakers
Original AssigneeAsm International N.V.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Copper interconnect structure having stuffed diffusion barrier
US 7732331 B2
Abstract
The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.
Images(12)
Previous page
Next page
Claims(44)
1. A process for copper metallization comprising:
depositing a diffusion barrier comprising grain boundaries over a semiconductor substrate;
after depositing the diffusion barrier, separately providing a compounding material and incorporating the compounding material into the diffusion barrier;
depositing a layer of a reactive metal formed to a thickness of about 0.1-2.0 nm over the diffusion baffler;
stuffing the grain boundaries of the diffusion baffler with a compound of the reactive metal from the layer of the reactive metal and the compounding material; and
depositing a layer of copper over the diffusion barrier.
2. The process of claim 1, wherein the diffusion baffler comprises a metal nitride.
3. The process of claim 2, wherein the diffusion baffler comprises a metal nitride selected from the group consisting of titanium nitride, tungsten nitride and tantalum nitride.
4. The process of claim 3, wherein the diffusion baffler comprises titanium nitride.
5. The process of claim 2, wherein the reactive metal is selected from the group consisting of Al, Si, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mg, Y and La.
6. The process of claim 5, wherein the reactive metal is Al.
7. The process of claim 2, wherein the reactive metal is selected from the group consisting of metals of group IIIB of the periodic table, metals of group VIB of the periodic table, metals of group VB of the periodic table, and metals of Group VIB of the periodic table.
8. The process of claim 2, wherein incorporating a compounding material comprises incorporating nitrogen into the diffusion baffler prior to depositing the layer of reactive metal.
9. The process of claim 2, wherein incorporating a compounding material comprises incorporating oxygen into the diffusion barrier prior to depositing the layer of reactive metal.
10. The process of claim 9, wherein incorporating oxygen into the diffusion barrier comprises annealing the substrate in the presence of oxygen.
11. The process of claim 9, wherein incorporating oxygen into the diffusion barrier comprises treating the diffusion barrier with excited oxygen species.
12. The process of claim 2, further comprising depositing a second metal nitride layer between depositing the layer of reactive metal and depositing the layer of copper.
13. The process of claim 9, wherein forming a different metal compound comprises forming metal oxide by annealing after deposition of the reactive metal layer.
14. The process of claim 2, wherein forming a different metal compound comprises forming metal oxide by annealing in the presence of oxygen.
15. The process of claim 14, wherein forming a different metal compound comprises forming metal oxide by annealing in the presence of oxygen after deposition of the second metal nitride layer and before depositing the copper layer.
16. The process of claim 2, wherein the layer of reactive metal is deposited to a thickness of about 2 nm.
17. The process of claim 2, wherein the metal nitride is deposited to a thickness of about 5 to 10 nm.
18. The process of claim 2, wherein the metal nitride layer is deposited by atomic layer deposition (ALD).
19. The process of claim 2, wherein the reactive metal layer is deposited by a process selected from the group consisting of chemical vapor deposition (CVD) and atomic layer deposition (ALD).
20. The process of claim 2, wherein the reactive metal layer is deposited by plasma enhanced atomic layer deposition (PEALD).
21. A process for copper metallization comprising:
depositing a metal nitride diffusion barrier comprising grain boundaries over a semiconductor substrate;
after depositing the diffusion barrier, separately providing a compounding material and incorporating the compounding material into the diffusion barrier;
depositing a layer of a reactive metal formed to a thickness of about 0.1-2.0 nm over the diffusion barrier;
moving the reactive metal from the layer of the reactive metal through the grain boundaries of the diffusion barrier to stuff the grain boundaries with a compound of the reactive metal and the compounding material; and
depositing a layer of copper over the diffusion barrier.
22. The process of claim 21, wherein the metal nitride is selected from the group consisting of titanium nitride, tungsten nitride and tantalum nitride.
23. The process of claim 21, wherein the compounding material is selected from the group consisting of oxygen and nitrogen.
24. The process of claim 21, wherein incorporating a compounding material into the diffusion barrier comprises exposing the metal nitride diffusion barrier to air.
25. The process of claim 21, wherein incorporating a compounding material into the diffusion barrier comprises annealing the metal nitride diffusion barrier in the presence of oxygen.
26. The process of claim 21, wherein incorporating a compounding material into the diffusion barrier comprises treating the metal nitride diffusion barrier with activated oxygen.
27. The process of claim 21, wherein moving the reactive metal through the grain boundaries comprises annealing.
28. The process of claim 21, wherein the reactive metal is aluminum.
29. The process of claim 28, wherein the compounding material is oxygen.
30. The process of claim 29, wherein the grain boundaries are stuffed with aluminum oxide.
31. A process for copper metallization comprising:
depositing a metal nitride layer on a semiconductor substrate;
depositing a layer of a reactive metal over the metal nitride layer, the reactive metal being different from any metal in the metal nitride layer and wherein the reactive metal is selected from the group consisting of Al, Si, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mg, Y and La;
depositing a second metal nitride layer directly over and contacting the reactive metal layer; and
forming a metal compound in the grain boundaries of the metal nitride layers, the metal compound formed from the reactive metal.
32. The process of claim 31, additionally comprising depositing a layer of copper directly over the second metal nitride layer.
33. The process of claim 31, wherein the first metal nitride layer is titanium nitride.
34. The process of claim 31, wherein the second metal nitride layer is titanium nitride.
35. The process of claim 31, wherein the reactive metal layer is aluminum.
36. The process of claim 31, wherein the reactive metal layer is silicon.
37. The process of claim 31, wherein a layer of titanium is deposited over the reactive metal layer prior to depositing the second metal nitride layer.
38. The process of claim 31, additionally comprising depositing a second metal layer over the reactive metal prior to depositing the second metal nitride layer.
39. A process of forming a barrier layer during semiconductor metallization comprising:
depositing a layer of titanium nitride in a damascene trench by atomic layer deposition (ALD);
depositing a layer of aluminum on the layer of titanium nitride; and
depositing a second layer of titanium nitride directly on and contacting the layer of aluminum.
40. The process of claim 39, wherein the layer of aluminum is deposited by MOCVD.
41. The process of claim 40, wherein the layer of aluminum is deposited from dimethylethylamine alane (DMEAA).
42. The process of claim 39, wherein the layer of aluminum is deposited by plasma enhanced atomic layer deposition (PEALD).
43. The process of claim 39, wherein the second layer of titanium nitride is deposited by atomic layer deposition (ALD).
44. The process of claim 39, additionally comprising annealing in the presence of oxygen following deposition of the second layer of titanium nitride.
Description
REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. patent application Ser. No. 10/007,304, filed Dec. 5, 2001 now U.S. Pat. No. 6,936,535 and claims priority under 35 U.S.C. §119 to Korean Patent Application Number 10-2000-0074025, filed Dec. 6, 2000.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to methods of fabricating a semiconductor device and, more particularly, to methods of forming interconnect structures in a semiconductor device fabrication process.

2. Description of the Related Art

A process of fabricating a semiconductor integrated circuit is roughly divided into the process of forming devices on a silicon substrate and the process of electrically connecting the devices. The latter is called an interconnection process or metallization, and is a key for improving yield rate and reliability in the fabrication of semiconductor devices as the devices become more highly integrated.

A metal widely used as an interconnection material is aluminum (Al). However, as the integration of devices is improved, the interconnection line width is reduced, while its total length is increased, such that the signal transfer delay time, represented by the RC time constant, is lengthened. Furthermore, the reduction in interconnection line width results in cutting in the interconnection line due to electromigration or stress migration. Accordingly, in order to fabricate a reliable device with a fast operation speed, copper (Cu) is used instead of aluminum (Al) for forming the interconnection lines since it has lower resistance compared with that of Al and stronger resistance against electromigration and stress migration.

However, Cu lacks excellent properties that Al has other than the low resistance and high melting point. For example, Cu cannot form a dense protective layer such as Al2O3, has bad adhesive strength to SiO2 and is difficult to dry-etch. In addition, its diffusion coefficient in silicon is approximately 106 times larger than that of Al, and it is known that Cu diffused into the silicon forms a deep level between band gaps. Furthermore, copper's diffusion coefficient in SiO2 is known to be large, which decreases the ability of SiO2 to insulate between Cu lines. As a result of copper's large diffusion coefficient in silicon and SiO2, the reliability of the semiconductor device is reduced. Accordingly, to ensure the reliability of the device, a diffusion barrier capable of preventing Cu from rapidly diffusing into the silicon or SiO2 is required.

Ta or TaN thin films deposited by a sputtering process are currently being used as the diffusion barrier for Cu, instead of the TiN films generally used in the conventional Al interconnection line fabricating process. However, when the diffusion barrier is deposited in a contact or trench structure using sputtering, step coverage deteriorates as the device size becomes smaller. This problem suggests that it would be beneficial to form the diffusion barrier through a more conformal process, such as chemical vapor deposition (CVD).

However, the development of new processes for forming a reliable diffusion barrier for Cu requires a considerably long period of time and this may delay commercialization of a semiconductor device employing a Cu interconnect structure.

The present invention solves the above problems. It is an object of the present invention to provide methods for fabricating a semiconductor device employing a diffusion barrier whose grain boundary is stuffed with metal oxide, not a metal element constructing the diffusion barrier. This may advance commercialization of a semiconductor device with a Cu interconnect structure.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, a process for copper metallization is provided. A diffusion barrier comprising grain boundaries is deposited over a semiconductor substrate and a layer of reactive metal is deposited over the diffusion barrier. A different metal compound, such as an oxide or nitride of the reactive metal, is formed in the grain boundaries of the diffusion barrier. Copper is then deposited over the diffusion barrier.

In one embodiment the diffusion barrier is a metal nitride, preferably selected from the group consisting of titanium nitride, tungsten nitride and tantalum nitride. More preferably the diffusion barrier is titanium nitride. In a further embodiment the reactive metal is Al. In another embodiment the different metal compound is formed in the grain boundaries by annealing after deposition of the reactive metal layer.

In another aspect, the present invention provides a process for copper metallization in which a metal nitride layer is deposited on a semiconductor substrate, a layer of reactive metal is deposited over the metal nitride layer, a second metal nitride layer is deposited over the reactive metal layer, and a metal compound is formed from the reactive metal in the grain boundaries of the metal nitride layers. In a preferred embodiment, the metal nitride layers are titanium nitride and the reactive metal is aluminum.

In a further aspect, the present invention provides a diffusion barrier for a copper interconnect comprising a layer of metal nitride covered by a layer of reactive metal. The grain boundaries of the metal nitride layer are stuffed with a different metal compound.

In one embodiment the metal nitride layer is titanium nitride, the reactive metal is aluminum, and the grain boundaries are stuffed with aluminum oxide. In another embodiment the reactive metal is silicon and the grain boundaries of the metal nitride are stuffed with silicon oxide. In yet another embodiment the diffusion barrier additionally comprises a second metal nitride layer over the layer of reactive metal.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects and advantages of the invention can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIGS. 1 to 6 are cross-sectional views showing a method of forming a Cu interconnect structure according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view of a Cu interconnect structure according to another embodiment of the present invention.

FIG. 8 is a graph showing the sheet resistances of samples based on the thickness of the Al thin film and the annealing temperature in experimental Cu interconnect structures, comparing a conventional structure with structures formed according to one embodiment of the present invention.

FIGS. 9A to 9D are SEM photographs showing etch pits on a silicon surface exposed after etching Cu, Al and TiN layers in experimental Cu interconnect structures, comparing a conventional structure with structures formed according to one embodiment of the present invention.

FIG. 10 illustrates a process for the growth of TiN/Al/TiN by ALD.

FIG. 11 shows a process for the growth of TiN/Al/Ti/TiN by ALD.

FIG. 12 illustrates a process for the growth of TiN by atomic layer deposition (ALD) using plasma.

FIG. 13 illustrates a process for the growth of TiN by plasma enhanced ALD (PEALD) using nitrogen radicals.

FIG. 14 shows a process for the growth of elemental aluminum using hydrogen radicals.

FIG. 15 is a process for the ALD growth of elemental titanium with hydrogen radicals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present disclosure teaches processes for forming a diffusion barrier in the context of copper metallization, as well as diffusion barriers formed by these processes. However, the skilled artisan will appreciate that the present processes and structures have applications in other contexts.

The present invention will now be described in connection with preferred embodiments with reference to the accompanying drawings.

A diffusion barrier is a material that is inserted between two substances in order to prevent the substances from being mixing with each other due to diffusion. In a semiconductor device fabrication process, the diffusion barrier is used not only to prevent the diffusion between a substrate and interconnection material but also to block the interconnection material from diffusing into a dielectric film.

Diffusion barriers can be roughly classified into passive barriers, non-barriers, single crystal barriers, sacrificial barriers and stuffed barriers. If the diffusion barrier remains thermodynamically stable between the interconnection material and substrate, it is a passive barrier or non-barrier. The distinction between the two is based on diffusion through the grain boundary of the diffusion barrier. That is, the diffusion barrier is a passive barrier when it there is little diffusion through the grain boundary. On the other hand, a diffusion barrier is a non-barrier, which does not serve as a diffusion barrier, when material diffuses easily through the grain boundary.

Diffusion barriers are sacrificial barriers if they are thermodynamically unstable such that there is a reaction with either the interconnection material or the substrate. Thus, the sacrificial barrier itself reacts with the interconnection material or substrate material to prevent the diffusion of the material. The sacrificial barrier is consumed according to the reaction so that it loses its function as the diffusion barrier when it has been completely consumed. When a diffusion barrier cannot fulfill its function it is called “diffusion barrier failure”. Thus, sacrificial diffusion barrier failure will occur after a lapse of a predetermined time, however it performs its function until then.

Diffusion barrier failure in Cu interconnects is often the result of one of the following three causes:

    • 1) Diffusion of Cu or substrate atoms through defects in the diffusion barrier, such as dislocations or vacancies;
    • 2) Diffusion of Cu or substrate atoms through the grain boundary of a polycrystalline diffusion barrier; and
    • 3) Chemical reaction of the diffusion barrier with the Cu or substrate material.

Failure of a thermodynamically stable diffusion barrier mainly depends on number 2 above, namely, the diffusion of Cu or substrate atoms through the grain boundary of a polycrystalline diffusion barrier. This is because the diffusion of the Cu or substrate atoms through the grain boundary occurs much more readily than diffusion through the grain. Accordingly, it is very important to prevent the diffusion through the grain boundary.

There are several approaches to preventing diffusion through the grain boundary. First, forming the diffusion barrier using a single crystal or amorphous crystal having no grain boundary may avoid grain boundary diffusion. The second approach is to block existing grain boundaries. Blocking the grain boundaries in a polycrystalline thin film is called ‘stuffing’ and results in a ‘stuffed barrier.’

A method of “stuffing” the diffusion barrier that has been studied uses nitrogen stuffing and oxygen stuffing. Precipitates of nitrides or oxides have been formed at the grain boundaries of diffusion barriers by the reaction of nitrogen or oxygen with metal elements present in the diffusion barriers. These precipitates stuff the grain boundaries of the diffusion barriers. In the case of TiN diffusion barriers, commonly used in aluminum metallization, one method to improve the barrier properties is to stuff the grain boundaries with extra oxygen by annealing a TiN thin film deposited by PVD or CVD in a N2 or O2 ambient. For example, diffused oxygen in the grain boundaries of the TiN reacts to form titanium oxide that is thought to stuff the grain boundaries.

The stuffing effect with nitrogen or oxygen works efficiently with Al but is not effective with Cu. Specifically, most of the oxygen introduced into TiN films with the help of annealing diffuses through the grain boundaries of the TiN to oxidize the surface of the TiN grains. The oxygen in the titanium oxide reacts easily with Al that has diffused through the grain boundaries to form Al2O3. However, in the case of Cu, the enthalpy of formation of copper oxide is smaller than that of Ti oxide. Thus, Cu atoms that diffuse through the grain boundary do not take oxygen from the titanium oxide and do not form copper oxide. The following Table 1 shows the enthalpy of formation of titanium oxide, aluminum oxide and copper oxide.

TABLE 1
Enthalpy of formation at 298 K
Type Phase (kJ/mol)
Ti—O TiO −519.7
Ti2O3 −1521.6
Ti3O5 −2457.2
TiO2 −944.0
Al—O Al2O3 −1675.7
Cu—O CuO −168.6
Cu2O −157.3

As described above, a TiN thin film into which oxygen has been incorporated through annealing can serve as an excellent stuffed diffusion barrier for Al but is barely effective for Cu. Furthermore, because Cu is does not react strongly with nitrogen, it is difficult to improve the property of the diffusion barrier by incorporating impurities.

Again, because the enthalpy of formation for copper oxide is smaller than that of Ti oxide, Cu cannot form oxide at the grain boundary of the TiN. The following table 2 shows the tendency of oxide formation enthalpy for various metals.

TABLE 2
Ca V Nb Mo Hf Ta W Al Mg Ti Zr Cr Zn Be
Enthalpy of oxide CaO: V2O5: Nb2O5: MoO3: HfO2: Ta2O5: WO3: Al2O3: MgO: TiO2: ZrO2: Cr2O3: ZnO: BeO:
formation [kJ/mol] −635 −1550 −1550 −745 −1144 −2045 −842 −1656 −601 −944 −1097 −1139 −350 −608

As shown in the table 2, metals such as Al, Zr, Cr, V, Nb, Hf and Ta that have an enthalpy of oxide formation larger than that of Ti oxide can form oxides by reacting with oxygen atoms bound to Ti as they diffuse along the TiN grain boundaries. Consequently, these metals can be used to stuff the grain boundary.

A TiN thin film can serve as an effective diffusion barrier in Al interconnection lines because oxygen contained in the TiN thin film can combine with the Al to form an oxide that stuffs the grain boundaries. Thus, a metal whose enthalpy of oxide formation is lower than that of the metal element of the diffusion barrier can be used to “stuff” the grain boundary of the diffusion barrier with the oxide of the metal, thereby forming a diffusion barrier that is effective for Cu interconnection lines. Accordingly, in one embodiment of the present invention a compounding material such as oxygen is incorporated into the diffusion barrier in an amount sufficient for stuffing the grain boundary. In one arrangement, the oxygen is preferably incorporated into the diffusion barrier before the stuffing step. Annealing is preferably carried out to move the material through the grain boundary and to thereby form an oxide at the grain boundary.

In one aspect of the invention, a reactive metal element having a strong inclination to form an oxide is deposited or formed on the diffusion barrier in the form of a thin film, such as by using a gas containing the metal element or a solution including its ions. The diffusion barrier thus contains a small amount of the metal element therein. In the case of the deposition of the metal element, the metal thin film is formed in minimum thickness such that the diffusion of the metal element into the Cu layer is restricted, while the resistance of the Cu layer is not affected.

FIGS. 1 to 6 show an embodiment of a method of fabricating a semiconductor device according to the present invention. FIG. 1 illustrates a part of the semiconductor device, including a substrate 10 and a dielectric film 20 formed thereon. A plurality of elements may be formed on the semiconductor substrate 10, such as MOS transistors, bipolar junction transistors and resistors, for example. These elements have been formed previously through fabrication processes executed before the illustrated step. The semiconductor device shown may employ a multilevel-interconnection structure. In this case, the substrate 10 can include the semiconductor elements and a metal layer that electrically connects the elements. A dielectric film 20 may be, for example, SiO2, Si3N4, or a doped glass film. It is preferably formed through CVD or PECVD processes, depending on its composition. In a preferred embodiment, the dielectric film 20 is preferably formed of SiO2 deposited by CVD.

Next, as shown in FIG. 2, a via or trench 22 is formed in the dielectric film. The via or trench 22 may be formed using reactive ion etching and a mask that defines the boundary of the via or trench 22. In case of a contact hole through which a metal line comes into contact with an element formed on the substrate or a lower metal line, the via penetrates the dielectric film 20 to reach the substrate 10. In a field region other than a contact hole, however, it does not reach the substrate 10 and instead forms a trench 22 in which a metal line is to be formed. FIGS. 1 to 6 show the trench 22 formed at the field region. The skilled artisan will recognize this as a stage in damascene metallization.

Referring to FIG. 3, a TiN thin film 32 is deposited by CVD on the dielectric film 20 having the trench 22 formed therein. The TiN thin film 32 is preferably formed to a thickness of approximately 100 Å. Thereafter, a process for incorporating a compounding material, such as oxygen or nitrogen, into the grain boundaries of the TiN thin film 32 is executed. Preferably, oxygen is incorporated into the grain boundary. This may be accomplished by exposing the TiN thin film 32 to the air, by annealing the TiN film in a furnace or by treating the TiN thin film with activated oxygen from an O2-plasma.

Referring to FIG. 4, an Al thin film 34 serving as an intermediate metal layer is deposited on the TiN film 32, such as by CVD. In a preferred embodiment, the Al thin film 34 is formed to a thickness of about 0.1-2.0 nm. The double layer 30 of the TiN thin film 32 and Al thin film 34 serves as a new diffusion barrier after an annealing process.

Referring to FIG. 5, a Cu layer 40 is deposited on the double layer 30 to fill the trench 22. The Cu layer 40 is preferably formed through PVD, electroplating or MOCVD. After the completion of the deposition of the Cu layer, the surface of the semiconductor device is planarized as shown in FIG. 6. In a preferred embodiment, the planarization is carried out in such a manner that the TiN thin film 32, Al thin film 34 and Cu layer 40 are nonselectively removed through chemical mechanical polishing (CMP). Note that CMP could be selective against a CMP shield over the insulating layer 20. In another alternative embodiment, the planarization may be performed by a nonselective plasma etching process. Upon completion of the planarization, a Cu interconnect 50 is exposed and the diffusion barrier 30, comprising the TiN thin film 32 and Al thin film 34, is present between the dielectric film 20 and the Cu interconnect 50. In the aforementioned process, an annealing process is performed at least once following deposition of the Al film.

FIGS. 8 and 9 illustrate experimental examples of Cu interconnect structures realized according to one embodiment of the present invention. In the examples shown, a TiN layer was deposited to the thickness of about 200 Å by pyrolytic deposition using the single precursor of TDMAT on an 8-inch silicon wafer. The wafer was cut into samples with a size of 1 inch2 and Al and Cu were continuously deposited thereon using DC magnetron sputtering. Annealing was carried out at a pressure of below 5×106 Torr in a vacuum ambient. The annealing was carried out for one hour at temperatures from about 500-700° C., with the temperature being increased in steps of about 50° C. The sheet resistance of each of the annealed samples was measured by using a four-point probe. FIG. 8 shows the measured result of the sheet resistance based on various thicknesses of the Al thin film and different annealing temperatures. As shown in FIG. 8, the samples having the Al thin film deposited thereon at a thickness of 10 nm or greater effectively block diffusion of Cu, compared to sample A, having only Cu deposited thereon.

The Cu layer, Al film and TiN film were removed using a chemical solution in order to estimate the diffusion barrier failure temperature, and then the silicon surface was Secco-etched. FIGS. 9A to 9D are SEM (Scanning Electron Microscopy) photographs of etch pits on the silicon surface exposed by the etching. FIGS. 9A to 9D correspond to the four samples (A, B, C and D) of FIG. 8, respectively, which were all annealed at 650° C. As shown in FIGS. 9A to 9D, the size and density of the etch pits are sharply reduced as the Al film thickness increases.

As a result of the estimation of the failure temperature, diffusion barrier failure occurred in the sample having only the Cu layer deposited thereon, without the Al film, after annealing for one hour at 500° C. under vacuum. Diffusion barrier failure did not occur in the samples with an Al film of 10 nm or greater thickness or more deposited thereon, even after annealing for one hour at 700° C. in the same ambient. From this result, it is understood that the CVD-TiN thin film deposited contains greater than 20 atomic % oxygen because its fine structure is porous enough that Al in contact with the TiN film diffuses into the TiN grain boundaries during the annealing to form Al oxide at the grain boundaries, thereby blocking Cu diffusion.

Although a specific embodiment has been illustrated and described above, it will be obvious to those skilled in the art that various modifications may be made. For example, although the Al thin film is formed as the intermediate metal layer on the single-level TiN diffusion barrier 32 in the above-described embodiment, the TiN diffusion barrier can be formed in a multilevel structure. In the case of a multilevel TiN diffusion barrier, the Al film is formed between the layers of the multilevel TiN diffusion barrier. FIG. 7 shows the case where the TiN diffusion barrier is formed of two layers. Referring to FIG. 7, a first TiN thin film 32-1 is deposited on the dielectric film 20, preferably using CVD, and then the process for stuffing the grain boundary thereof with oxygen is carried out. Thereafter, Al is deposited on the first TiN thin film 32-1. As described above, the intermediate Al metal layer is preferably deposited in the form of thin film on the first TiN film 32-1, or an adhesion layer is formed on the TiN film using a gas containing Al or a solution having Al ions.

Subsequently, a second TiN thin film 32-2 is deposited on the intermediate metal layer using CVD, thereby forming a multilevel TiN diffusion barrier. The Cu layer 40 is deposited on the second TiN film 32-2 through the aforementioned process. After the deposition of the second TiN thin film 32-2, annealing is preferably carried out for the deposited structure at least once. With the structure shown in FIG. 7, Al diffuses into the first and second TiN thin films 32-1, 32-2 during the annealing and combines with O2 existing in the films to form Al oxide at the grain boundaries of the first and second TiN thin films 32-1, 32-2, thereby effectively blocking the diffusion of Cu. In addition, a further intermediate metal layer can be formed on the second TiN thin film 32-2 to block the diffusion of Cu more effectively.

Although Al is used for the intermediate metal layer in the above illustrated embodiment of the invention, Zr, Cr, V, Nb, Hf or Ta, which have a stronger inclination to formation oxide than Ti, can also be used as a material for forming the intermediate metal layer as shown in Table 2. In other words, the intermediate metal layer is formed of a metal element that forms an oxide thereof more easily than the metal element of which the diffusion barrier is comprised.

Furthermore, the intermediate metal layer can be formed through a method other than CVD, such as PVD, electroplating, electrodeless plating, wet chemical contamination and atomic layer deposition (ALD).

Although the diffusion barrier is formed of TiN in the aforementioned embodiment, TaN or WN can be also used for the diffusion barrier and deposited using CVD. In addition, the above-described embodiment relates to the fabrication of a Cu interconnect structure located on the dielectric film. However, in the actual semiconductor device fabrication process, a contact hole for connecting the metal line for interconnection to an element formed on the substrate or a lower metal line can be formed. In the structure having this contact hole, the diffusion barrier is deposited on the substrate or lower metal line located under the contact hole, the intermediate metal layer is formed on the diffusion barrier and the Cu layer is deposited on the intermediate metal layer. In a further variation of this embodiment of the invention, the Cu layer is not deposited in the contact hole, ohmic contact is made using only the intermediate metal layer, and the Cu interconnect structure is employed only in the field area.

As described above, a novel diffusion barrier combines a layer comprising a diffusion barrier layer used in the conventional Al interconnect structure, for example, a TiN film, with an intermediate metal ultra thin film, preferably comprised of a metal selected from the group consisting of Al, Zr, Cr, V Nb, Hf and Ta. By forming the diffusion barrier for the copper line in an easier way, the commercialization of copper as the line material can be advanced.

In another embodiment, a diffusion barrier comprising grain boundaries is deposited on a semiconductor substrate. Preferably the diffusion barrier comprises a metal nitride, such as titanium nitride, tungsten nitride or tantalum nitride. More preferably the diffusion barrier is titanium nitride. A thin layer of a reactive metal is deposited on the diffusion barrier layer. The reactive metal reacts with a compounding material, particularly nitrogen or oxygen, to form a different metal compound that expands within and stuffs the grain boundaries of the metal nitride layer. Preferably the reactive metal reacts with oxygen to form a metal oxide during an annealing process. The oxygen may have been incorporated in the metal nitride layer prior to deposition of the reactive metal layer. Alternatively the oxygen may be supplied during the annealing.

In a further embodiment, a diffusion barrier comprising grain boundaries is deposited on a semiconductor substrate. Preferably the diffusion barrier comprises a metal nitride, such as titanium nitride, tungsten nitride or tantalum nitride. More preferably the diffusion barrier is titanium nitride. A thin layer of a reactive metal is deposited on the diffusion barrier layer. A second layer of metal nitride is then deposited on top of the reactive metal layer, to form a laminate structure.

FIG. 10 illustrates a process for depositing a TiN/Al/TiN structure. A 5 nm layer of TiN is grown 170 by ALD on a semiconductor substrate. Next, a 2 nm aluminum layer is grown 172 by ALD on the TiN layer. Finally a 5 nm layer of TiN is grown 174 by ALD on the aluminum layer.

In yet a further embodiment an additional metal layer is deposited. Thus, a diffusion barrier comprising grain boundaries is deposited on a semiconductor substrate. The diffusion barrier is preferably a metal nitride, such as TiN. A first reactive metal layer, such as an aluminum layer, is deposited thereon. Next, a second metal layer is deposited on the first reactive metal layer. A second diffusion barrier, such as a metal nitride layer, is then deposited on the second metal layer. According to one embodiment the second metal layer is a titanium metal layer that covers the surface of the first reactive metal and protects it against the nitrogen source chemical that is used for the growth of a second diffusion barrier layer, such as a metal nitride layer. A process for producing structures according to this embodiment is diagramed in FIG. 11.

As shown in FIG. 11, a 5-nm layer of TiN is grown 190 by, e.g., ALD on a substrate surface. Next, a 2-nm aluminum layer is grown 192 by, e.g., ALD on the TiN surface. Then a 1-nm layer of Ti is grown 194 by, e.g., ALD on the aluminum surface. The Ti layer protects the aluminum layer against the nitrogen source chemical that is used to grow the second metal nitride layer. Finally, a 4-nm layer of TiN is grown 196 by, e.g., ALD on the titanium surface. Because ALD often utilizes highly reactive source chemicals, in the beginning of the TiN layer growth 196, the nitrogen source chemical might react with the titanium metal (deposited at step 194) and convert the titanium metal into titanium nitride. In that case the resulting thin film structure would be TiN/Al/TiN, instead of TiN/Al/Ti/TiN.

In each of the embodiments described above, the diffusion barrier comprising grain boundaries may be treated with oxygen or nitrogen, for compounding with the reactive metal in the grain boundaries, prior to deposition of the reactive metal layer. Such treatment may comprise, for example, exposure to oxygen in the atmosphere, an oxygen anneal process or treatment with O2 plasma. As a result, oxygen or nitrogen is incorporated in the grain boundaries of the diffusion barrier. The compounding material may be present in an unreacted form, such as free oxygen or nitrogen, and/or may have previously reacted with the metal of the diffusion barrier at the grain boundaries forming, e.g., TiO2. At any point following deposition of the reactive metal layer, an anneal step is carried out such that the reactive metal reacts with the oxygen or nitrogen present in the grain boundaries of the metal nitride layer to form an oxide or nitride stuffing the grain boundaries. This metal oxide or nitride incorporates the reactive metal, which is different from the metal in the metal nitride.

Alternatively, an anneal process is carried out in the presence of oxygen after deposition of the reactive metal layer. In the case of the laminate embodiments, the oxygen anneal may be carried out immediately following deposition of the first reactive metal layer, or after the deposition of a subsequent reactive metal and/or further metal nitride layer. The reactive metal layer reacts with oxygen during the oxygen anneal to form a metal oxide that stuffs the grain boundaries of the diffusion barrier.

The term “reactive metal” or “elemental metal” as used herein, broadly refers to any element that can react with oxygen to form an oxide or nitrogen to form a nitride and stuff the grain boundaries of a diffusion barrier layer, particularly a metal nitride layer. Reactive metals include, but are not limited to, aluminum, silicon, titanium, metals in groups IVB, VB and VIB of the periodic table, such as Zr, Hf, V, Nb, Ta, Cr, Mo and W, germanium, magnesium, yttrium, lanthanum, and metals in Group III of the periodic table, including the lanthanide series (e.g., Sc, Ce, pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu).

Metal nitride layers, for example TiN layers, may be formed by any method known in the art, including PVD, CVD, ALD and PEALD. Preferably, damascene trenches and/or contact vias are lined with metal nitride by ALD for forming conformal layers.

In one embodiment a TiN layer is preferably formed by atomic layer deposition (ALD), more preferably by plasma enhanced atomic layer deposition (PEALD). FIG. 12 is a flowchart illustrating an exemplary PEALD process for depositing a TiN layer. A titanium source chemical is pulsed 110 to the reaction chamber. Titanium source chemical molecules adsorb on the substrate surface, self-limitingly, to form no more than a monolayer. Surplus titanium source chemical molecules and possible reaction byproducts are purged away 102. Hydrogen radicals are formed and contacted with the substrate surface for a pulse time 104. The adsorbed titanium source chemical molecules are reduced into elemental titanium metal atoms by the hydrogen radicals. Excess hydrogen radicals and reaction byproducts are purged away 106. A nitrogen source chemical is pulsed into the reaction chamber 108. Excess nitrogen source chemical molecules are purged away 110 and the cycle 112 is repeated until a layer of TiN with the desired thickness is grown. A typical thickness for the TiN layer is 5 nm to 10 nm.

FIG. 13 illustrates another possible process for depositing a TiN layer by PEALD. A titanium source chemical is pulsed 100 to the reaction chamber. Titanium source chemical molecules adsorb on the substrate surface, self-limitingly, to form no more than a monolayer. Surplus titanium source chemical molecules and possible reaction byproducts are purged away 102. Nitrogen radicals are formed and contacted with the substrate surface for a pulse time 120. Several exemplary nitrogen source chemicals that may be used in forming metal nitrides include radicals of N, NH and NH2 as well as excited N2*. The adsorbed titanium source chemical molecules react with nitrogen radicals and form titanium nitride on the surface. Excess hydrogen radicals and reaction byproducts are purged away 122. The cycle 124 is repeated until a layer of TiN of the desired thickness is grown. A typical thickness for the TiN layer is 5-10 nm.

The reactive metal layer may also be deposited by any method known in the art, such as by PVD, CVD, ALD or plasma enhanced ALD (PEALD) processes. In one embodiment the metal layer is deposited by ALD. Source chemicals for use in ALD of the reactive metal layer include, for example, alanes, alkyl aluminum, silanes, germanes, alkylamido titanium compounds such as tetrakis(ethylmethylamido) titanium, and cyclopentadienyl metal compounds.

In the case of a thin film of a very reactive metal, such as aluminum, an ALD process preferably utilizes pulsed plasma and inactive purging and carrier gases. Inactive gases are preferably selected from the group consisting of argon (Ar), helium (He), hydrogen (H2) and mixtures thereof.

For example, in one embodiment a layer of elemental aluminum is deposited by PEALD as outlined in FIG. 14. An aluminum source chemical is pulsed 130 into the reaction chamber. Exemplary ALD source chemicals for the deposition of aluminum include alanes and alkyl aluminum (e.g., trimethyl aluminum). A preferred aluminum source chemical is dimethylethylamine alane (DMEAA), which lacks aluminum-carbon bonds and is therefore less likely to lead to carbon contamination of the aluminum layer. When DMEAA is used, the temperature is preferably kept below the thermal decomposition limit, normally less than about 120° C., more preferably less than about 100° C., and above the condensation limit. Aluminum source chemical molecules adsorb on the substrate surface. Excess aluminum source-chemical molecules and possible reaction byproducts are purged away 132. Hydrogen radicals are formed and contacted with the substrate surface for a pulse time 134. The adsorbed aluminum source chemical molecules react with hydrogen radicals and form elemental aluminum atoms on the substrate surface. Excess hydrogen radicals and reaction byproducts are purged away 136 and the cycle 138 is repeated until a layer of elemental aluminum of the desired thickness is grown. A typical thickness for an aluminum metal layer is 2 nm.

In another embodiment a layer of elemental aluminum is deposited by CVD. Deposition of an aluminum layer by CVD is described, for example, in Kim et al. (“Microstructure and deposition rate of aluminum thin films from chemical vapor deposition with dimethylethylamine alane,” Appl. Phys. Lett. 68 (25): 3567-3569 (1996)) and in Li et al. (“Structural characterization of aluminum films deposited on sputtered-titanium nitride/silicon substrate by metalorganic chemical vapor deposition from dimethyethylamine alane,” Appl. Phys. Lett. 67(23): 3426-3428 (1995)), both of which are hereby incorporated by reference. In both processes, a preferred aluminum source chemical is DMEAA.

A layer of elemental titanium can also be deposited by ALD, as illustrated in FIG. 15. A titanium source chemical is pulsed 150 into the reaction chamber. Titanium source chemical molecules adsorb on the substrate surface, self-limitingly, leaving no more than a monolayer. Excess titanium source-chemical molecules and possible reaction byproducts are purged away 152. Hydrogen radicals are formed and contacted with the substrate surface for a pulse time 154. The adsorbed titanium source chemical molecules react with hydrogen radicals and form elemental titanium atoms on the substrate surface. Excess hydrogen radicals and reaction byproducts are purged away 156. The cycle 158 is repeated until a layer of elemental titanium is grown. A typical thickness for the titanium metal layer is 0.5-2 nm.

In yet another embodiment a stuffed diffusion barrier is formed by depositing a first TiN layer by ALD, depositing an aluminum layer by ALD or CVD on the first TiN layer and depositing a second TiN layer by ALD on the aluminum layer. The structure is annealed in the presence of oxygen, either after depositing the aluminum layer or after depositing the second TiN layer. The aluminum reacts with oxygen during the oxygen anneal to form Al2O3 that stuffs the nitride grain boundaries of one or both TiN layers.

In a further embodiment a stuffed diffusion barrier is formed by depositing a layer of TiN, depositing a layer of silicon thereon, depositing an optional further TiN layer thereover, and annealing such that the silicon reacts with oxygen to form silicon oxide that stuffs the grain boundaries of the TiN layer.

Although the foregoing invention has been described in terms of certain preferred embodiments, other embodiments will be apparent to those of ordinary skill in the art, in view of the disclosure herein. Accordingly, the present invention is not intended to be limited by the recitation of the preferred embodiments, but is instead to be defined by reference to the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3669734Aug 5, 1970Jun 13, 1972Rca CorpMethod of making electrical connections to a glass-encapsulated semiconductor device
US5019531May 19, 1989May 28, 1991Nippon Telegraph And Telephone CorporationProcess for selectively growing thin metallic film of copper or gold
US5098860May 7, 1990Mar 24, 1992The Boeing CompanyMethod of fabricating high-density interconnect structures having tantalum/tantalum oxide layers
US5252518Mar 3, 1992Oct 12, 1993Micron Technology, Inc.Method for forming a mixed phase TiN/TiSi film for semiconductor manufacture using metal organometallic precursors and organic silane
US5254498May 21, 1992Oct 19, 1993Sony CorporationMethod for forming barrier metal structure
US5275973Mar 1, 1993Jan 4, 1994Motorola, Inc.Method for forming metallization in an integrated circuit
US5391517Sep 13, 1993Feb 21, 1995Motorola Inc.Process for forming copper interconnect structure
US5429989Feb 3, 1994Jul 4, 1995Motorola, Inc.Process for fabricating a metallization structure in a semiconductor device
US5592024Oct 28, 1994Jan 7, 1997Kabushiki Kaisha ToshibaSemiconductor device having a wiring layer with a barrier layer
US5674787Jan 16, 1996Oct 7, 1997Sematech, Inc.Selective electroless copper deposited interconnect plugs for ULSI applications
US5856236Jun 14, 1996Jan 5, 1999Micron Technology, Inc.Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer
US5892254Sep 30, 1997Apr 6, 1999Samsung Electronics Co., Ltd.Integrated circuit capacitors including barrier layers having grain boundary filling material
US5913144Sep 20, 1996Jun 15, 1999Sharp Kabushiki KaishaOxidized diffusion barrier surface for the adherence of copper and method for same
US5918150Oct 11, 1996Jun 29, 1999Sharp Kabushiki KaishaMethod for a chemical vapor deposition of copper on an ion prepared conductive surface
US5939788Mar 11, 1998Aug 17, 1999Micron Technology, Inc.Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper
US5985762May 19, 1997Nov 16, 1999International Business Machines CorporationMethod of forming a self-aligned copper diffusion barrier in vias
US6008117Mar 19, 1997Dec 28, 1999Texas Instruments IncorporatedMethod of forming diffusion barriers encapsulating copper
US6025269Oct 15, 1996Feb 15, 2000Micron Technology, Inc.Method for depositioning a substantially void-free aluminum film over a refractory metal nitride layer
US6037257May 8, 1997Mar 14, 2000Applied Materials, Inc.Sputter deposition and annealing of copper alloy metallization
US6107687Mar 16, 1998Aug 22, 2000Mitsubishi Denki Kabushiki KaishaSemiconductor device having interconnection and adhesion layers
US6120842Oct 21, 1997Sep 19, 2000Texas Instruments IncorporatedTiN+Al films and processes
US6126806Dec 2, 1998Oct 3, 2000International Business Machines CorporationEnhancing copper electromigration resistance with indium and oxygen lamination
US6127256Nov 10, 1998Oct 3, 2000Kabushiki Kaisha ToshibaSemiconductor device and method of manufacturing the same
US6130155Jul 2, 1999Oct 10, 2000Infineon AgMethod of forming metal lines in an integrated circuit having reduced reaction with an anti-reflection coating
US6130160Apr 20, 1998Oct 10, 2000Micron Technology, Inc.Methods, complexes and system for forming metal-containing films
US6160314May 5, 1998Dec 12, 2000United Microelectronics Corp.Polishing stop structure
US6160315Jan 6, 2000Dec 12, 2000Applied Materials, Inc.Copper alloy via structure
US6171898Dec 15, 1998Jan 9, 2001Texas Instruments IncorporatedMethod of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing
US6204175Jan 5, 1999Mar 20, 2001Micron Technology, Inc.Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer
US6204179 *Jul 9, 1999Mar 20, 2001Micron Technology, Inc.Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with copper
US6271136Apr 4, 2000Aug 7, 2001Taiwan Semiconductor Manufacturing CompanyMulti-step plasma process for forming TiSiN barrier
US6271592Aug 6, 1999Aug 7, 2001Applied Materials, Inc.Sputter deposited barrier layers
US6342444Mar 10, 2000Jan 29, 2002Kabushiki Kaisha ToshibaMethod of forming diffusion barrier for copper interconnects
US6348402Mar 16, 2000Feb 19, 2002Kabushiki Kaisha ToshibaMethod of manufacturing a copper interconnect
US6380065Nov 8, 1999Apr 30, 2002Sony CorporationInterconnection structure and fabrication process therefor
US6436825Apr 3, 2000Aug 20, 2002Taiwan Semiconductor Manufacturing CompanyMethod of copper barrier layer formation
US6441492Sep 28, 2000Aug 27, 2002James A. CunninghamDiffusion barriers for copper interconnect systems
US6506668Jun 22, 2001Jan 14, 2003Advanced Micro Devices, Inc.Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability
US6924226 *Dec 23, 2002Aug 2, 2005Uri CohenMethods for making multiple seed layers for metallic interconnects
EP0839927A2Oct 31, 1997May 6, 1998Texas Instruments Inc.Method of forming films comprising TiN and Al
JP2000269213A Title not available
JPH113890A Title not available
JPH07326612A Title not available
JPH11111919A Title not available
JPS63299250A Title not available
WO2000075964A2Dec 30, 1999Dec 14, 2000Kim Ki BumMethod of fabricating semiconductor device employing copper interconnect structure
Non-Patent Citations
Reference
1Abstract of presentation of Korean Materials Academic Society, "Improvement of CVD-TiN diffusion barrier performance in Cu metallization by a thin Al interlayer between Cu and TiN," Apr. 1999, Korea.
2Cho et al., "Diffusion barrier properties of metallorganic chemical vapor deposited tantalum nitride films against cu metallization," Journal of the Electrochemical Society, 1999, pp. 3724-3730, vol. 146, No. 10.
3Gong et al., "Interdiffusion and reaction in the Cu/TiN/Si thin film system, " Applied Surface Science, Dec. 1994, pp. 335-339, vol. 92.
4Kim, B. et al., "Microstructure and deposition rate of aluminum thin films from chemical vapor depostion with dimethylethylamine alane," Appl. Phys. Lett., 1996, pp. 3567-3569, vol. 68, No. 25.
5Kim, K. et al., "A novel scheme of CVD-diffusion barrier for Cu metallization," D6.6, p. 95 and Im, Se-Joon et al., "A study on CVD TaN as a diffusion barrier for Cu interconnects," D6.7, pp. 95-96, Presentation at Materials Research Society Symposium-Apr. 2000, San Francisco, abstracts attached.
6Kim, K. et al., "A novel scheme of CVD-diffusion barrier for Cu metallization," D6.6, p. 95 and Im, Se-Joon et al., "A study on CVD TaN as a diffusion barrier for Cu interconnects," D6.7, pp. 95-96, Presentation at Materials Research Society Symposium—Apr. 2000, San Francisco, abstracts attached.
7Kim, K. et al., abstract of presentation at Advanced Metallization Conference, "Improvement of diffusion barrier performance by a thin A1 interlayer deposited between barrier and copper," Oct. 1999, Orlando, FL.
8Kim, S. et al., "A comparative study of film properties of chemical vapor deposition TiN films as diffusion barriers for Cu metallization," Journal of the Electrochemical Society, 1999, pp. 1455-1460, vol. 146, No. 4.
9Kim, Y. et al., "Via poisoning-free dual damascene etching for organic low-k material integration," Materials Research Society Symposium Spring 2001, Symposium L., L5.5.
10Lee et al., "Influence of vacuum-annealing on the diffusion barrier properties of MOCVD TiN for Cu metallization," Journal of the Korean Physical Society, 1999, pp. S65-S70, vol. 35.
11Li et al., "Structural characterization of aluminum films deposited on sputtered-titanium nitride/silicon substrate by metalorganic chemical vapor deposition from dimethylethylamine alane," Appl. Phys. Lett., 1995, pp. 3426-3428, vol. 67, No. 23.
12Mitsuo et al., "Improvement of high-temperature oxidation resistance of titanium nitride and titanium carbide films by aluminum ion implantation," Surface and Coatings Technology, 1998, pp. 98-103, vols. 103-104.
13Nam et al., "Improved diffusion barrier by stuffing the grain boundaries of TiN with a thin Al interlayer for Cu metallization," Applied Physics Letters, 2001, pp. 2549-2551, vol. 79, No. 16.
14Nam et al., "Laterally segregated two phase mixture diffusion barrier for Cu metallization, "Presentation at Advanced Metallization Conference, Oct. 2, 2001, Toyko, Japan, Abstract.
15Rha et al., "Improved TiN film as a diffusion barrier between copper and silicon," Thin Solid Films, May 4, 1998, pp. 134-140, vol. 320.
16World-wide web cubic.mat.ncku.edu.tw/ceramics/homepage/intro-e.htm., "Investigation of diffusion barrier of TiAlN films between Cu and Si (86)," pp. 7-8 and "Diffusion barrier and interface properties of TiAlN between Cu and Si (89)," pp. 10, Mar. 29, 2001.
17Yoon et al., "Improvement of diffusion barrier performance of 10nm TiN layer using a very thin A1 interlayer," Abstract of presentation at Advanced Metallization Conference, Oct. 2000, San Diego, USA.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8659156Oct 18, 2011Feb 25, 2014International Business Machines CorporationInterconnect structure with an electromigration and stress migration enhancement liner
Classifications
U.S. Classification438/687, 257/761, 438/688, 438/358, 438/85, 257/754, 257/770, 438/104, 257/768
International ClassificationH01L21/3205, C23C16/34, C23C16/20, H01L21/28, H01L23/532, H01L21/44, H01L21/285, H01L23/52, H01L21/768, H01L21/00, H01L23/48
Cooperative ClassificationH01L21/76846, H01L21/76858, H01L21/28562, H01L23/53238, H01L21/76856, H01L21/76855
European ClassificationH01L21/768C3D2, H01L21/768C3D2D, H01L21/768C3B4, H01L23/532M1C4, H01L21/768C3D2B, H01L21/285B4H2
Legal Events
DateCodeEventDescription
Nov 6, 2013FPAYFee payment
Year of fee payment: 4
Jan 18, 2011CCCertificate of correction