|Publication number||US7733135 B2|
|Application number||US 12/190,996|
|Publication date||Jun 8, 2010|
|Filing date||Aug 13, 2008|
|Priority date||Oct 31, 2007|
|Also published as||US20090108884|
|Publication number||12190996, 190996, US 7733135 B2, US 7733135B2, US-B2-7733135, US7733135 B2, US7733135B2|
|Inventors||Paras M. Dagli, David John Baldwin, Adam Shook|
|Original Assignee||Texas Instruments Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Classifications (11), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This patent claims the benefit of U.S. Provisional Patent Application No. 60/984,180, filed on Oct. 31, 2007, and claims the benefit of U.S. Provisional Patent Application No. 61/060,362, filed on Jun. 10, 2008, the entireties of which are incorporated by reference.
This disclosure relates generally to differential amplifier driver circuits and, more particularly, to high side boosted gate drive circuits.
Class D amplifiers are popular for signal amplification due to their high efficiency at full power, reduced need for heat sinking, and smaller quiescent currents. Traditional low-voltage (i.e., less than 5V) class D architectures use an n-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) on a low side and a p-channel MOS (PMOS) FET on a high side.
NMOS FETs are appealing to use on the high side of the class D amplifier due to their lower drain-source resistance (RDSon) and higher switching speeds, but they require the gate voltage to be higher than the supply voltage. Such a gate voltage is typically provided by bootstrap circuits, which are often used to provide the floating power supply for the high-side switch gate drive. However, bootstrapping in an integrated circuit (IC) often requires extra pins on the IC and components external to the integrated circuit, which raises complexity and cost. Bootstrapping may also be limited by the frequent charging time requirements that conflict with the gate drive operation, especially under varying duty cycle conditions. If the bootstrap capacitor is not adequately charged, the high-side gate drive may even be completely starved of energy and be, therefore, unable to turn on.
High side boosted gate drive circuits are disclosed. In a particular example, a switching device configured to selectively conduct current in response to a charge being present at a control terminal for a duty cycle. A charging device delivers charge to the control terminal based on the first duty cycle. A charge control device is further included, configured to selectively couple the charging device to deliver charge to the control terminal and to selectively decouple the charging device from the control terminal to charge the charging device. Finally, a discharge control device removes charge from the control terminal.
Certain examples are shown in the above-identified figures and described in detail below. In describing these examples, like or identical reference numbers may be used to identify common or similar elements. The figures are not necessarily to scale and certain features and certain views of the figures may be shown exaggerated in scale or in schematic for clarity and/or conciseness. Although the following discloses example methods and apparatus, it should be noted that such methods and apparatus are merely illustrative and should not be considered as limiting. The example circuits described herein may be implemented using discrete components, integrated circuits (ICs), or any combination thereof.
Additionally, it is contemplated that any form of logic may be used to implement portions of apparatus or methods herein. Logic may include, for example, circuit implementations that are made exclusively in dedicated hardware (e.g., circuits, transistors, logic gates, hard-coded processors, programmable array logic (PAL), application-specific integrated circuits (ASICs), etc.), exclusively in software, exclusively in firmware, or some combination of hardware, firmware, and/or software. Accordingly, while the following describes example methods and apparatus, persons of ordinary skill in the art will readily appreciate that the examples are not the only way to implement such apparatus.
As described below, the examples herein may be used to provide a high side boosted gate drive circuit. One example circuit includes a high side laterally diffused metal oxide semiconductor (LDMOS) transistor, a low side LDMOS transistor, and a high side gate drive circuit to drive the high side LDMOS transistor. An example high side gate drive circuit includes a switching device configured to selectively conduct current in response to a charge being present at a control terminal for a duty cycle and a charging device configured to deliver charge to the control terminal to turn on the switching device. A charge control device selectively couples the charging device to deliver charge to the control terminal and selectively decouples the charging device from the control terminal to charge the charging device while keeping the switching device on. A discharge control device removes charge from the control terminal to turn off the switching device. To avoid completely draining the bootstrap capacitor of energy, the circuit charges and/or maintains a charge in the charging device for at least 50% of the clock cycle, regardless of the input and/or output duty cycle.
In another example, a logic circuit is shown and described that allows the example high side boosted gate drive circuit to operate with very low duty cycles. The logic circuit has a master clock input and a deglitch input, and outputs a clock signal based on the master clock input and the deglitch input. For high input duty cycles, the logic circuit outputs a clock signal that tracks the rising and falling edges of the master clock signal. However, for low input duty cycles the output clock signal from the logic circuit has a falling edge that is delayed to provide enough time for the charging device in the high side gate drive circuit to sufficiently discharge. The clock signal output from the logic circuit is used by the example high side gate drive circuit described in
The example circuit implementations described herein may have a reduced layout area by approximately 40% compared to using a traditional p-channel MOSFET for the high side MOSFET in a process such as LBC7. Further, overall quiescent current may be 30% lower than a traditional architecture such as using a p-channel high side MOSFET and an n-channel low side MOSFET.
The example amplifier circuit 100 may be implemented using an IC, such as a processor chip or a dedicated differential amplifier chip. Further, the differential signaling drivers 101 and 102 may be similar or identical in components and/or configuration. For brevity and clarity, only the differential signaling driver 101 will be described in detail. However, those of ordinary skill in the art will recognize that the inventive concepts may be equally applied to the differential signaling driver 102.
The example differential signaling driver 101 includes a deglitch logic/deglitch logic/clock generator 110, a timing signal generator 120, a high side boosted gate drive circuit 130, and a low side gate driver 140. The differential signaling driver 101 further includes a high side n-channel MOSFET 150, which is driven by the high side boosted gate drive circuit 130, and a low side n-channel MOSFET 160, which is driven by the low side gate driver 140.
The example differential signaling driver 101 receives three input signals and has one output signal (OUT+). The example input signals are a master clock signal (MCLK) and a pulse-width modulated (PWM) input data signals (DATA_P and DATA_N). The example DATA_P and DATA_N signals are PWM signals of the type generated in a Class-D amplifier, having a duty cycle based on a comparison of a integrated differential signal and a high-frequency ramp signal. The MCLK signal may be a standard clock signal having a 50% duty cycle (i.e., active logic level for 50% of the clock cycle). The DATA_P signal may be one signal from a pair of PWM signals, where the corresponding input signal DATA_N is used by the differential signaling driver 102. Alternatively, the DATA_P signal may be a one-sided signal. Further, the duty cycle of DATA_P determines the duty cycle of OUT+.
The deglitch logic/clock generator 110 deglitches the DATA_P signal and generates a clock signal (CLK_P) for use in the timing signal generator 120 from the MCLK signal and the DATA_P signal(s). During normal operation, the high side boosted gate drive circuit 130 tolerates only one DATA_P pulse per MCLK cycle. Any glitch pulses that may occur on the DATA_P signal are filtered out by the deglitch logic/clock generator 110. For high DATA_P and OUT+ duty cycles (e.g., duty cycles greater than approximately 50%), the example deglitch logic/clock generator 110 outputs the CLK_P signal such that CLK_P is equal or substantially equal to MCLK. However, for low DATA_P and OUT+ duty cycles (e.g., between approximately 1% and 50%), the example deglitch logic/clock generator 110 shifts the falling edge of the CLK_P signal in a time-delayed manner relative to MCLK. The shift in the falling edge of the CLK_P signal allows the bootstrap capacitor of the high side boosted gate drive circuit 130 to charge and discharge properly at low duty cycles. It is noted that the definition of a “high” or a “low” duty cycle may change depending on the specific implementation of the differential signaling driver 101.
As described in detail below, the timing signal generator 120 generates timing signals for use in the high side boosted gate drive circuit 130. The generated timing signals may include a CLKL signal, a CLKLZ signal, an HS signal, and an HSD signal. The timing signal generator 120 generates the example timing signals based on combinations of the CLK_P signal, the DATA_P signal, and feedback signals from the high side boosted gate drive circuit 130, using a combination of logic gates and voltage level-shifting circuitry. Example feedback signals include a GATE_HI signal and a GATE_LO signal, which control the high side n-channel MOSFET 150 and low side n-channel MOSFET 160, respectively.
The high side boosted gate drive circuit 130 generates the control signal GATE_HI, which controls the state of the high side n-channel MOSFET 150 (e.g., on or off). As explained below, due to the high gate voltage requirement of the high side n-channel MOSFET 150, the example high side boosted gate driver includes a bootstrapping circuit, which generates a sufficient voltage to drive GATE_HI such as to turn on the high side n-channel MOSFET 150. The timing signals generated by the timing signal generator 120 and the DATA_P signal are used by the high side boosted gate drive circuit 130 to charge energy to and discharge energy from the bootstrapping circuit by selectively switching combinations of switching elements (e.g., transistors) on and off, and further guarantees that the bootstrapping circuit charges with energy and/or maintains a charge for at least 50% of the clock cycle, regardless of the DATA_P duty cycle.
The n-channel MOSFETs 150 and 160 of the example amplifier circuit 100 are output LDMOS transistors included as part of the IC on which the example differential signaling driver 101 is implemented. The power n-channel MOSFETs 150 and 160 are designed to allow relatively large currents and/or voltage differences between the drain, source, and gate terminals. Although the example n-channel MOSFETs 150 and 160 are implemented using LDMOS transistors, any suitable device may be used to provide OUT+ with sufficient current and/or voltage to one or more output devices (e.g., the output device 103). Either or both of the n-channel MOSFETs 150 and/or 160 may be implemented in the IC or external to the IC, using discrete components, additional ICs, or some combination thereof.
The deglitch logic/clock generator 110 generates the clock signals CLK_P and CLK_N based on the duty cycles of DATA_P and DATA_N. For DATA_P duty cycles greater than 50%, the example circuit 200 selects the MCLK signal to use as the CLK_P signal via the output device P 204. The selection device 202 generates SELECT_P depending on the sequence of falling edges on the DATA_P and DATA_N signals. Depending on the duty cycles of each DATA signal, the DATA_P or the DATA_N signal will have a falling edge first in a given MCLK clock cycle, followed by a falling edge on the other DATA signal. The DATA (e.g., DATA_N) signal that has the falling edge first has the duty cycle larger than 50% and, thus, the selection device 202 causes the corresponding output device 204 or 206 to pass through the MCLK signal. In contrast, the other DATA signal (e.g., DATA_N) has a duty cycle less than 50% and the selection device 202 causes the corresponding output device 204 or 206 to delay the falling edge of the output clock signal.
The example DATA_P and DATA_N signals are PWM input signals based on respective high-speed comparator outputs (not shown). The inputs to the comparators are an integrated differential input signal and a triangle wave corresponding to the MCLK signal. For example, the differential signaling driver 101 is designed so the falling CLK_P edge is centered between the rising and falling edges of the OUT+ signal. As described below, the CLK_P output signal only changes state in response to MCLK changing state. The state of the DATA_N signal does not affect the CLK_P signal unless MCLK changes state from logic high to logic low. In such a case, an active (logic low) DATA_N signal prevents a change in the state of the CLK_P signal, delaying CLK_P from following MCLK to logic low until DATA_N returns to logic high. This delay effect only occurs during very low DATA_P duty cycles, and allows a charge pump capacitor to properly discharge energy as described below in
Glitch pulses on the DATA_P and DATA_N signals may occur at any time. The logic circuit 110, in combination with the timing signal generator 130 of
The output devices 204 and 206 of the example circuit 200 shown in
The DATA_P signal is input to a first NOT gate 310 and to a NAND gate 312. An output of the NOT gate 310 is used as a second input to the OR gate 306. The DATA_N signal is input to a second NOT gate 314 and to a NAND gate 316. An output of the NOT gate 314 is used as a second input to the OR gate 308, as an input to an OR gate 316, and as an input to a NAND gate 318. An output of the OR gate 316 is used as a second input to the NAND gate 312. An output of the NAND gate 312 is used as a first input to another NAND gate 320, and an output of the NAND gate 318 is used as the second input to the NAND gate 320. An output of the NAND gate 320 is used as the second input to the OR gate 316, as the second input to the NAND gate 318, and as the selection input C to the multiplexer 302.
A similar configuration is constructed for the selection input C of the multiplexer 304 using NAND gates 322, 324 and 328, and OR gate 326. An output of the NAND gate 324 is fed back to be used as inputs to the NAND gate 322 and the OR gate 326, and is also used as the selection input C for the multiplexer 304.
The example logic gates 312, and 316-320, and 322-328 are used to implement the selection device 202 described in
The output of the multiplexer 302 is CLK_P, which is used as the CLK_P signal for the timing signal generator 130 and the high side boosted gate drive circuit 130 of the differential signaling driver 101. Similarly, the output of the multiplexer 304 is CLK_N, which is used as the CLK_P signal for a corresponding timing signal generator and a corresponding high side boosted gate drive circuit for the differential signaling driver 102.
The example multiplexers 302 and 304 and the logic gates 306-328 of the deglitch logic/clock generator 110 may be integrated into the IC on which the remainder of the differential signaling driver 101 is located. Additionally or alternatively, any or all of the components of the deglitch logic/clock generator 110 may be implemented using discrete components, additional ICs, or some combination thereof. Although an example logic circuit 110 is shown in
In operation, the example logic circuit 110 delays the falling edge of the CLK_P signal when DATA_P has a low duty cycle (e.g., less than 50%) and delays the falling edge of the CLK_N signal when DATA_N has a low duty cycle. In this example, the DATA_N signal and DATA_N signal are active low signals. As shown below in
In the example case that the duty cycle of DATA_P is greater than 50%, the duty cycle of DATA_N is less than 50% as shown by Equation 1:
where d is the duty cycle in percent. As a result, the state of DATA_P changes from logic high to logic low, followed by a change in the state of DATA_N from logic high to logic low, and then followed by the falling edge of MCLK. In this example, the logic to generate the output CLK_P signal (i.e., the multiplexer 302 and the gates 306, and 310-320) will illustrate generating the CLK_P signal for a duty cycle greater than 50%. The logic to generate the CLK_N signal (i.e., the multiplexer 304 and the gates 308, 310, 314, and 322-328) will illustrate generating a delayed CLK_N signal. It is to be understood that for DATA_N duty cycles of less than 50%, the behavior of the logic may be interchanged due to the symmetrical nature of the example logic circuit 110.
The initial states of the NAND gates 320 and 324 may be logic low and/or logic high from a previous clock cycle, but the initial states do not affect the net result of the logic sequence shown in
As mentioned above, the logic sequence shown in
For DATA_P and DATA_N duty cycles of 50%, the logic circuit 110 delays both CLK_P and CLK_N signals until the rising edges of DATA_N and DATA_N, respectively. The delay functionality of the deglitch logic/clock generator circuit 110 is further shown and described in connection with
To generate the HSD signal, the GATE_HI and CLK_P signals are input into a NAND gate 402. The output 404 of the NAND gate 402 is then input to an OR gate 406 with the DATA_N signal. Then, the output 408 of the OR gate 406 is input to an inverting circuit 410 and a voltage-level shifting circuit 412. The example inverting circuit 410 inverts the output 408 of the OR gate 406 using p-channel MOSFET MP1 and n-channel MOSFET MN2. The voltage level-shifting circuit 412, which includes an n-channel MOSFET MN3 and a capacitor C1, increases maximum voltage of the HSD signal from PVDD to 2*PVDD.
To generate the CLKL and CLKLZ signals, the example circuit 500 receives the CLK_P signal and inputs it into a NOT gate 502. An output 504 of the NOT gate 502 is input to a NAND gate 506 with the SD′ signal, which is a logic high in the current example. An output 508 of the NAND gate 506 is input to an OR gate 510 with the SD signal. The OR gate 510 provides an output 512, which is then input to an OR gate 514 with DATA′.
The output of the OR gate 514 is used as the CLKL signal in the high side boosted gate drive circuit 130, as described below in
It is noted that the NOT gate 502 may be omitted from the example circuit 500 by providing the NAND gate 506 with the inverse CLK_P signal from an alternative location. Additionally, if the SD and SD′ signals are not desired in a particular implementation, the NOT gate 502, the NAND gate 506, and the OR gate 510 may be omitted by inputting the CLK_P signal directly into the OR gate 514 instead of the output 512 of the OR gate 510.
The example high side boosted gate drive circuit 130 includes a charging device, implemented as a capacitor CP, which has a terminal CP_P and a terminal CP_N. The capacitor CP is charged and discharged by selectively switching transistors MN9, MN10, MN11, MP12, and/or MP13 on and off. The transistors MN9, MN10, and MP12 are used to implement a charge pump, which can generate a voltage at CP_P greater than the supply voltage PVDD. The transistor MP13 is used to implement a charge control device to control delivery of charge from the charging device CP to the control terminal of the switching device. The transistor MN11 is used as a discharge device to selectively discharge the control terminal of the switching device. Although an example implementation of the switching device, charging device, charge pump, charge control device, and discharge device are described, it should be recognized that other implementations are possible and fall within the scope of the inventive concept.
Depending on the transistors that are on and off at a given moment, CP is charged by a voltage supply PVDD and a ground reference PGND, or discharges to provide GATE_HI with sufficient charge to turn on the high side n-channel MOSFET 160. The transistor MN9 has a source terminal coupled to the CP_P terminal, a drain terminal coupled to PVDD, and a backgate terminal coupled to PVDD. The level-shifted timing signal CLKLZ is coupled to a gate terminal to control the state of MN9 (i.e., on or off). As described below, the CP_P terminal voltage may fluctuate between PVDD and 2*PVDD based on the voltage applied at CP_N. The transistor MN10 selectively couples the CP_N terminal to PGND based on the timing signal CLKL. As described above, the example CLKL and CLKLZ signals increase and decrease voltage at substantially the same times. However, as described above in
In the example of
As noted above, the HS, CLKL, CLKLZ and HSD signals are generated to guarantee that CP will be charged for at least 50% of the clock cycle. The timing signal generator 120 generates the timing signals based on the CLK_P, DATA, and GATE_HI signals such that charging of CP begins at the falling edge of CLK_P, and does not end until after the rising edge of CLK_P. Thus, as shown below in connection with
In the example high side boosted gate drive circuit 130, the transistors MN9 and MN10 are isolated 7V n-channel MOSFETs included in the IC package. However, any appropriate devices may be used to selectively couple PGND to CP_N and/or PVDD to CP_P, where the devices support the applicable currents and/or voltages without damage. Due to the relatively high voltages seen by the terminals of MN11, an extended drain n-channel MOSFET is used, which is constructed as part of the IC. However, other devices may also be used, provided the transistor can support the voltages at the drain-source terminals.
The example transistors MP12 and MP13 are implemented using 7V p-channel MOSFETs included in the IC. MP14 and MP15 as shown in the example generally have lower voltage requirements than MP12 and MP13. The transistors MP12-MP15 may be implemented using the same or substantially the same types and/or sizes of p-channel transistor, or one or more transistors may be implemented using a different type of transistor. Additionally or alternatively, one or more of the transistors may be implemented using one or more additional ICs, one or more discrete component, or some combination thereof.
The example charging device capacitor CP is a high-density bootstrap capacitor included in the IC with the other components of the high side boosted gate drive circuit 130. The capacitance of CP is chosen to provide sufficient energy to GATE_HI and the gate of high side n-channel MOSFET 160. However, any bootstrap capacitor or other energy storage device may be used to implement the charging device, provided there is sufficient energy storage capacity and the energy storage device can support voltages up to 2*PVDD. Other example capacitors include capacitors included in the IC package and external capacitors, such as plastic film, ceramic, and/or electrolytic. Further, single or multiple capacitors may be used in series or in parallel to achieve a desired capacitance value, voltage tolerance, and/or other characteristic.
As mentioned above, the deglitch logic/clock generator 110 delays the clock signal CLK_P for low duty cycles (e.g., approximately 1%-50%) to facilitate proper transfer of charge from CP to the high side n-channel MOSFET 150 before the high side boosted gate drive circuit 130 begins recharging CP. For high duty cycles (i.e., greater than 50%), the master clock signal MCLK is passed through as the CLK_P signal for use by the high side boosted gate drive circuit 130. For low duty cycles, the deglitch logic/clock generator 110 generates a CLK_P signal different than the MCLK signal.
As described in connection with the example deglitch logic/clock generator 110 described in
The example waveform results will be used to describe the normal operation of the example high side boosted gate drive circuit 130 of
After a time determined by the duty cycle of DATA, DATA_N goes high at 906, causing GATE_HI to go low. GATE_HI turns off the high side n-channel MOSFET 150, while GATE_LO turns on the low side n-channel MOSFET 160, coupling OUT+ to PGND and causing OUT+ to go low. HSD also goes low via the example circuit 110 of
When DATA_P next goes low at 908, HS, CLKL, and CLKLZ also go low. As a result, MN9, MN10, and MN11 are turned off while MP12 and MP13 are turned on. Although the HSD signal does not change, MP13 is turned on due to the backgate connection changing voltages via MP14 and MP15. By coupling CP_N to PVDD, the voltage at CP_N jumps to PVDD or substantially to PVDD, and the charge on CP causes CP_P to jump to 2*PVDD. GATE_HI is charged by CP via MP13 and causes the high side n-channel MOSFET 150 to turn on, while the low side n-channel MOSFET 160 is turned off by GATE_LO. Thus, OUT+ goes high. Providing charge to GATE_HI causes CP to discharge energy. GATE_HI is proportional to the capacitances of CP and the high side n-channel MOSFET 150 as shown in Equation 2:
where CGS is the gate-source capacitance of the n-channel MOSFET 150, and CGD is the gate-drain capacitance of the n-channel MOSFET 150. The above-described process iterates (e.g., 904 repeats at 910, 906 repeats at 912) to drive the MOSFET 150 and, thus, OUT+ with a duty cycle equal to or substantially equal to DATA, as shown in
As mentioned above, the high side boosted gate drive circuit 130 guarantees that CP is charging or maintaining charge for at least 50% of the clock cycle. Thus, the time between points 904 and 908 must be greater than or equal to half of the clock cycle, and the time between points 908 and 910 must be less than or equal to half of the clock cycle. As described above, during each cycle CP begins charging when the MCLK signal goes from high to low at point 904. Due to the 50% duty cycle of the MCLK signal, if CP charges or maintains the charge beyond the point 907 where MCLK goes high, a charging rate greater than half of the clock cycle will be achieved. In the example high side boosted gate drive circuit 130, MCLK has a rising edge at point 907, which is halfway between the rising and falling edges of the DATA_N signal. CP begins discharging each cycle at point 908, which is the falling edge of DATA_P and is always after point 907. As a result, CP has a charging cycle greater than half of the clock cycle.
The above-described process may be used with the example DATA_P duty cycles shown in
Although certain methods and apparatus have been described herein, other implementations are possible. The scope of coverage of this patent is not limited to the specific examples described herein. On the contrary, this patent covers all methods and apparatus fairly falling within the scope of the invention.
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|U.S. Classification||327/109, 327/536|
|Cooperative Classification||H03K5/1252, H03K5/1515, H03K19/018521, H03F3/2171|
|European Classification||H03F3/217B, H03K5/1252, H03K19/0185B4, H03K5/151B|
|Aug 21, 2008||AS||Assignment|
Owner name: TEXAS INSTRUMENTS, INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DAGLI, PARAS M.;BALDWIN, DAVID JOHN;SHOOK, ADAM;REEL/FRAME:021431/0670
Effective date: 20080729
Owner name: TEXAS INSTRUMENTS, INCORPORATED,TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DAGLI, PARAS M.;BALDWIN, DAVID JOHN;SHOOK, ADAM;REEL/FRAME:021431/0670
Effective date: 20080729
|Nov 26, 2013||FPAY||Fee payment|
Year of fee payment: 4