US 7734983 B2 Abstract An input control apparatus capable of suppressing characteristic deterioration, reducing the circuit scale of a turbo decoder and effectively using memory of the turbo decoder. In this apparatus, control section (
110) acquires information on a coding rate and coding block length of a received signal, determines the number of bits of systematic part Y1, and parity parts Y2 and Y3 in accordance with the coding rate and/or coding block length and so that the number of bits of one sequence of the parity parts falls below the number of bits of systematic part Y1 and controls bit number reduction section (109) so that the determined number of bits is obtained. Bit number reduction section (109) reduces the number of bits of systematic part Y1, and parity parts Y2 and Y3 output from separation section (108) under the control of control section (110) and decoder (111) performs turbo decoding using each sequence reduced by bit number reduction section (109).Claims(6) 1. An input control apparatus comprising:
a receiving section that receives a signal including bits of a systematic part and bits of parity parts comprising a plurality of sequences, the signal being generated in an external transmission apparatus by turbo coding and puncturing information;
a rate dematching processing section that performs rate dematching processing on the received signal; and
a bit number reduction section that discards bits from the systematic part and bits from the parity parts so that the number of bits in each sequence of the parity parts is less than the number of bits in the systematic part, at a timing between the rate dematching processing and turbo decoding on the signal subjected to the rate dematching processing.
2. An input control apparatus comprising:
a receiving section that receives a signal including bits of a systematic part and bits of parity parts compromising a plurality of sequences, the signal being generated in an external transmission apparatus by turbo coding and puncturing information;
a rate dematching processing section that performs rate dematching processing on the received signal; and
a bit number reduction section that discards bits from the systematic art and bits from the parity parts so that the number of bits in each sequence of the parity parts is less than the number of bits in the systematic part, before performing turbo decoding on the signal subjected to the rate dematching processing, wherein
the bit number reduction section discards the bits from the systematic part and the bits from the parity parts so that the number of bits in the parity parts is determined in accordance with a coding rate and/or coding block length of a bit sequence received as input in a turbo decoder.
3. The input control apparatus according to
4. The input control apparatus according to
5. An input control method comprising the steps of:
receiving a signal including bits of a systematic part and bits of parity parts comprising a plurality of sequences, the signal being generated in an external transmission apparatus by turbo coding and puncturing information;
performing rate dematching processing on the received signal; and
discarding bits from the systematic part and bits from the parity parts so that the number of bits in each sequence of the parity parts is less than the number of bits in the systematic part, at a timing between the rate dematching processing and turbo decoding on the signal subjected to the rate dematching processing.
6. An input control method comprising the steps of:
receiving a signal including bits of a systematic part and bits of parity parts comprising a plurality of sequences, the signal being generated in an external transmission apparatus by turbo coding and puncturing information;
performing rate dematching processing on the received signal; and
discarding bits from the systematic part and bits from the parity parts so that the number of bits in each sequence of the parity parts is less than the number of bits in the systematic part, before performing turbo decoding on the signal subjected to the rate dematching processing, wherein
in the discarding, the bits from the systematic part and the bits from the parity parts are discarded so that the number of bits in the parity parts is determined in accordance with a coding rate and/or coding block length of a bit sequence received as input in a turbo decoder.
Description The present invention relates to an input control apparatus and input control method for quantizing data used for decoding. The signal output from modulation section Next, the configuration of OFDM reception apparatus The signals output from GI removing section Interleaver Element decoder Element decoder Non-Patent Document 1: C. Berrou, A. Glavieux “Near Optimum Error Correcting Coding And Decoding: Turbo-Codes,” IEEE Trans. Commun., Vol. 44, pp. 1261-1271, October 1996. However, the above described conventional turbo decoder has the following problems. The soft information bits of the systematic part and parity parts are quantized uniformly without any distinction between the systematic part and parity parts, and therefore the number of bits input to the turbo decoder is fixed and the same number of bits of systematic part Y Furthermore, in the actual system, the coding rate and coding block length are variable, and therefore the system requires a minimum coding rate defined by the system and a memory capacity capable of responding to a longest block length, but all the memory capacity is not always used, which results in a problem that there remains a free space and memory is not used effectively. It is therefore an object of the present invention to provide an input control apparatus and input control method that suppress characteristic deterioration, reduce the circuit scale of a turbo decoder and allow effective use of the memory of the turbo decoder. The input control apparatus of the present invention adopts a configuration having a bit number reduction section that reduces the number of bits of a systematic part and the number of bits of parity parts having a plurality of sequences input to a turbo decoder and a control section that controls the bit number reduction section so that the number of bits of one sequence of the parity parts falls below the number of bits of the systematic part. According to this configuration, the number of bits is reduced so that the number of bits of one sequence of the parity parts input to the turbo decoder falls below the number of bits of the systematic part, and it is thereby possible to perform a decoding calculation of the turbo decoder with a smaller number of bits and reduce the memory capacity used for this calculation. With regard to the number of bits input to the turbo decoder, the present invention can reduce the memory capacity of the turbo decoder and thereby reduce the circuit scale by reducing the number of bits of one sequence of the parity parts compared to the number of bits of the systematic part. Furthermore, the present invention enables effective use of memory by changing the number of bits of the systematic part and the number of bits of the parity parts input to the turbo decoder in accordance with a coding rate and/or coding block length. Now, an embodiment of the present invention will be explained with reference to the attached drawings. RF conversion section A/D conversion section GI removing section FFT section Demodulation section Separation section Bit number reduction section Control section Decoder Here, the method whereby control section -
- M: Number of bits of systematic part Y
**1** - L: Number of bits of parity parts Y
**2**and Y**3** - R: Coding rate
- N
_{block}: Coding block length
- M: Number of bits of systematic part Y
In above Equation (1), if M is fixed and L is expressed as a function of R, L can be expressed by the following equation:
where, int is a maximum integer that does not exceed the value of the equation in parentheses. In Equation (2), if, for example, R=1, then L=0. In this equation, when coding rate R is low, the number of bits L of the parity parts increases and when the coding rate R is high, the number of bits L of the parity parts decreases. Furthermore, M and L can be obtained using the following method. That is, when certain integer C is used, M can be expressed by following Equation (3) and L can be expressed by Equation (4): where, N Thus, control section Next, bit number reduction section Bit number reduction section Thus, in turbo decoding, bit number reduction section - Number of subcarriers: 1024
- Spreading factor: 8
- Modulation scheme (data): QPSK
- Turbo block length: 3196
- Channel coding: Turbo code (R=⅓, K=4) K: constraint length, Max-Log-MAP decoding
- Iteration count: 8
- Channel model: AWGN
In Thus, according to this embodiment, with regard to the number of bits input to the turbo decoder, it is possible to reduce the memory capacity of the turbo decoder and thereby reduce the circuit scale by reducing the number of bits of one sequence of the parity parts compared to the number of bits of the systematic part. Furthermore, it is possible to effectively use memory by changing the number of bits of the systematic part and the number of bits of the parity parts input to the turbo decoder in accordance with the coding rate and/or coding block length. This embodiment has explained the case where the turbo decoder is mounted on an OFDM reception apparatus as an example, but the present invention is not limited to this and is also applicable to cases where the turbo decoder is mounted on a reception apparatus using optical communication or a reproduction apparatus such as a magnetic disk and an optical disk. Furthermore, not only a turbo code but also a convolutional code can be used. A first aspect of the present invention is an input control apparatus having a bit number reduction section that reduces the number of bits of a systematic part and the number of bits of parity parts having a plurality of sequences input to a turbo decoder and a control section that controls the bit number reduction section so that the number of bits of one sequence of the parity parts falls below the number of bits of the systematic part. According to this configuration, by reducing the number of bits of the systematic part and the number of bits of the parity parts input to the turbo decoder so that the number of bits of one sequence of the parity parts falls below the number of bits of the systematic part, it is possible to perform a decoding calculation of the turbo decoder with a smaller number of bits, thereby reducing the memory capacity used for this calculation. A second aspect of the present invention is the input control apparatus in the above described aspect, wherein the control section controls the bit number reduction section so that the number of bits of the parity parts is obtained in accordance with a coding rate and/or coding block length of a bit sequence input to the turbo decoder. According to this configuration, by reducing the number of bits of the systematic part and the number of bits of the parity parts so that the number of bits of the parity parts is obtained in accordance with the coding rate and/or coding block length of the bit sequence input to the turbo decoder, it is possible to reduce the range of variation in the number of bits per block input to the turbo decoder, thereby reducing unused, free space of memory and enabling effective use of memory. A third aspect of the present invention is the input control apparatus in the above described aspect, wherein the control section performs control so that the number of bits of the parity parts decreases as the coding rate of the bit sequence input to the turbo decoder decreases and the number of bits of the parity parts increases as the coding rate increases. According to this configuration, the number of bits of the parity parts decreases where the number of bits used for decoding increases as the coding rate decreases, the number of bits of the parity parts increases where the number of bits used for decoding decreases as the coding rate increases, and it is possible to thereby reduce the range of variation in the number of bits per block input to the turbo decoder, reduce unused free space of memory and effectively use memory. A fourth aspect of the present invention is the input control apparatus of the above described aspect, wherein the control section performs control so that the number of bits of the parity parts decreases as the coding block length input to the turbo decoder increases and the number of bits of the parity parts increases as the coding block length decreases. According to this configuration, the control section controls the bit number reduction section so that the number of bits of the parity parts decreases as the coding block length increases and the number of bits of the parity parts increases as the coding block length decreases, and it is possible to thereby reduce the range of variation in the number of bits per block input to the turbo decoder, reduce unused free space of memory and effectively use memory. A fifth aspect of the present invention is an input control method having the step of reducing the number of bits of a systematic part and the number of bits of parity parts so that the number of bits of one sequence of the parity parts falls below the number of bits of the systematic part out of the systematic part and parity parts having a plurality of sequences input to a turbo decoder. According to this method, by reducing the respective numbers of bits in accordance with the coding rate and/or coding block length of the bit sequence input to the turbo decoder and so that the number of bits of one sequence of the parity parts falls below the number of bits of the systematic part, it is possible to reduce the range of variation in the number of bits per block input to the turbo decoder, thereby reducing unused free space of memory and enabling effective use of memory. Furthermore, it is possible to perform a decoding calculation of the turbo decoder with a smaller number of bits and thereby reduce the memory capacity used for this calculation. The present application is based on Japanese Patent Application No. 2003-333489 filed on Sep. 25, 2003, entire content of which is expressly incorporated by reference herein. With regard to the number of bits input to a turbo decoder, the input control apparatus and input control method according to the present invention has the effect of reducing the memory capacity of the turbo decoder by reducing the number of bits of one sequence of parity parts compared to the number of bits of a systematic part, and the effect of enabling effective use of memory by changing the number of bits of the systematic part and the number of bits of the parity parts input to the turbo decoder in accordance with a coding rate and/or coding block length, and is suitable for use in an apparatus having a turbo decoder such as a reception apparatus using radio communication, reception apparatus using optical communication and reproduction apparatus such as a magnetic disk and optical disk. Patent Citations
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