|Publication number||US7749896 B2|
|Application number||US 11/210,226|
|Publication date||Jul 6, 2010|
|Filing date||Aug 23, 2005|
|Priority date||Aug 23, 2005|
|Also published as||US9123781, US20070052096, US20100230816, US20150371943|
|Publication number||11210226, 210226, US 7749896 B2, US 7749896B2, US-B2-7749896, US7749896 B2, US7749896B2|
|Inventors||Hung-Wen Su, Shih-Wei Chou, Ming-Hsing Tsai|
|Original Assignee||Taiwan Semiconductor Manufacturing Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (33), Non-Patent Citations (1), Classifications (22), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to semiconductor fabrication, and in particular to semiconductor devices in which damages to a low-k dielectric layer therein can be reduced or even prevented and methods for forming the same.
Reduction of integrated circuit size has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solve this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
Unfortunately, low-k dielectric materials have characteristics that make it difficult to integrate into existing integrated circuit structures and processes. Compared to the conventional silicon dioxide (SiO2), the low-k materials, due to the inherent properties thereof, typically have disadvantages such as low mechanical strength, high moisture absorption, poor adhesion, and instable stress level. Thus, replacement of conventional silicon dioxide (SiO2) with low-k dielectric material in integrated circuit processes or structures becomes problematic, resulting in undesirable reliability problems due to physical damage to the low-k materials.
The low-k-dielectric layer 10 is then processed by, for example, a conventional single damascene process to form a plurality of openings op, filled by a bulk copper layer 14 formed thereon. A diffusion barrier layer 12, such as a tantalum nitride (TaN) layer, is conformably formed between the low-k dielectric layer 10 and the bulk copper layer 14 to prevent dopants or metal ions in the bulk copper layer 14 from diffusing into the low-k dielectric layer 10.
Due to inherently poor mechanical strength of the low-k material, the low-k dielectric layer 10 is damaged and lowered to a depth d1 of more than 200 Å below the top surface of the remaining copper layer 14 a during the described second and third CMP processes, thus forming interconnects with an uneven surface conformation, as shown in
Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. An exemplary method for forming semiconductor devices is provided, comprising providing a dielectric layer with at least one opening therein. A conductive barrier layer is formed over the dielectric layer and the opening. The opening is filled by a conductor over the conductive barrier layer. The exposed portion of the conductive barrier layer is converted into a substantially insulating film.
Another method for forming semiconductor devices is provided, comprising providing a low-k dielectric layer with at least one opening therein. A conductive diffusion barrier layer is conformably formed over the low-k dielectric layer and the opening, wherein the conductive diffusion barrier layer has a thickness less than 10 Å. A conductive layer is formed over the low-k dielectric layer, filling the opening. The portion of the conductive layer above the low-k dielectric layer and the portion of the diffusion barrier over the low-k dielectric layer are removed thereby exposing the top surface of the low-k dielectric layer and forming at least one conductive feature.
In addition, a semiconductor device is provided, comprising a substrate. A low-k dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with reference made to the accompanying drawings, wherein:
In this specification, expressions such as “overlying the substrate”, “above the layer”, or “on the film” simply denote a relative positional relationship with respect to the surface of the base layer, regardless of the existence of intermediate layers. Accordingly, these expressions may indicate not only the direct contact of layers, but also, a non-contact state of one or more laminated layers. In addition, by use of the term “low dielectric constant” or “low-k” herein, is meant a dielectric constant (k value) which is less than the dielectric constant of a conventional silicon oxide. Preferably, the dielectric constant of the low-k is less than about 4.0.
The dielectric layer 100 is then processed by, for example, a conventional single damascene process to form a plurality of openings op with a bulk conductive layer 104 thereon, filling the openings op. A diffusion barrier layer 102 conformably formed between the low-k dielectric layer 100 and the bulk conductive layer 104 prevents conductive dopants or metal ions of the bulk conductive layer 104 from diffusing into the low-k dielectric layer 100. Normally, the diffusion barrier layer 102 comprises electrically conductive material such as tantalum nitride (TaN) or the like. The diffusion barrier layer 102 can be formed by physical vapor deposition (PVD) such as sputtering at a thickness of about 300 Å, normally between 100-500 Å. The bulk conductive layer 104 may comprise, for example, copper or tungsten and is formed by methods such as electroplating or electroless plating.
In the treatment 106, a plasma comprising reactants such as N2, O2, or combination thereof and the like is used to treat the exposed portion of the diffusion barrier layer 102 and the conductive layer 104 a at a power of about 0-250 watts (W) and a pressure of about 0.5-10 torr for conversion to a cap layer 108 of dielectric material. Gas flows of the reactants used in the treatment can be respectively between, for example, 10 sccm and 100 sccm when using N2 and O2. The cap layer 108 can function as an etch stop layer (ESL) for sequential processes. Therefore, the cap layer 108 is transformed to a dielectric layer to thereby insulate the adjacent conductive features S. The cap layer may comprise nitride, oxide, or oxynitride of an metal or metal compound which depending to materials used in the diffusion barrier layer and the reactants used in the treatment 106. Also, the cap layer may comprise metal ions of a trance amount about 10 Å or less since the diffusion barrier layer always comprises metal.
Compared with the convention damascene process illustrated in
The dielectric layer 200 is then processed by, for example, a conventional single damascene process to form openings op, filled by a bulk conductive layer 204 thereon. A diffusion barrier layer 202 conformably between the dielectric layer 200 and the bulk conductive layer 204 prevents conductive dopants or metal ions of the bulk conductive layer 204 from diffusing into the dielectric layer 200. Normally, the diffusion barrier layer 202 comprises electrically conductive material such as tantalum nitride (TaN). Here, the diffusion barrier layer 204 is formed by atomic layer deposition (ALD) and has a thickness of less than 10 Å, preferably between 2-8 Å. The bulk conductive layer 204 may comprise, for example, copper or tungsten and is formed by methods such as electroplating or electroless plating.
Unlike convention damascene process illustrated in
The described methods for forming semiconductor devices like interconnects in which damages to a dielectric layer therein is reduced or even prevented are illustrated in a single damascene scheme but not restricted thereto, the described methods are also applicable for dual damascene scheme or other schemes known by those skilled in the art.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5676587||Dec 6, 1995||Oct 14, 1997||International Business Machines Corporation||Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride|
|US6136680 *||Jan 21, 2000||Oct 24, 2000||Taiwan Semiconductor Manufacturing Company||Methods to improve copper-fluorinated silica glass interconnects|
|US6146988 *||Jan 5, 2000||Nov 14, 2000||Advanced Micro Devices, Inc.||Method of making a semiconductor device comprising copper interconnects with reduced in-line copper diffusion|
|US6221792 *||Jun 24, 1997||Apr 24, 2001||Lam Research Corporation||Metal and metal silicide nitridization in a high density, low pressure plasma reactor|
|US6319766 *||Feb 22, 2000||Nov 20, 2001||Applied Materials, Inc.||Method of tantalum nitride deposition by tantalum oxide densification|
|US6335283 *||Jan 5, 2000||Jan 1, 2002||Advanced Micro Devices, Inc.||Method of reducing in-line copper diffusion|
|US6372636 *||Jun 5, 2000||Apr 16, 2002||Chartered Semiconductor Manufacturing Ltd.||Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene|
|US6458650 *||Jul 20, 2001||Oct 1, 2002||Taiwan Semiconductor Manufacturing Company||CU second electrode process with in situ ashing and oxidation process|
|US6472755 *||Oct 17, 2000||Oct 29, 2002||Advanced Micro Devices, Inc.||Semiconductor device comprising copper interconnects with reduced in-line copper diffusion|
|US6599827 *||May 2, 2001||Jul 29, 2003||Advanced Micro Devices, Inc.||Methods of forming capped copper interconnects with improved electromigration resistance|
|US6638810 *||Nov 5, 2001||Oct 28, 2003||Applied Materials, Inc.||Tantalum nitride CVD deposition by tantalum oxide densification|
|US6696360 *||Mar 15, 2001||Feb 24, 2004||Micron Technology, Inc.||Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow|
|US6717265||Nov 8, 2002||Apr 6, 2004||Intel Corporation||Treatment of low-k dielectric material for CMP|
|US6753250 *||Jun 12, 2002||Jun 22, 2004||Novellus Systems, Inc.||Method of fabricating low dielectric constant dielectric films|
|US6762500 *||Apr 15, 2002||Jul 13, 2004||Micron Technology, Inc.||Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow|
|US6781180 *||Oct 2, 2000||Aug 24, 2004||Infineon Technologies Ag||Trench capacitor and method for fabricating the same|
|US6831363 *||Dec 12, 2002||Dec 14, 2004||International Business Machines Corporation||Structure and method for reducing thermo-mechanical stress in stacked vias|
|US6916737 *||Nov 25, 2003||Jul 12, 2005||Dongbuanam Semiconductor, Inc.||Methods of manufacturing a semiconductor device|
|US7119019 *||Mar 31, 2004||Oct 10, 2006||Intel Corporation||Capping of copper structures in hydrophobic ILD using aqueous electro-less bath|
|US7129133 *||Sep 13, 2004||Oct 31, 2006||Spansion Llc||Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film|
|US7186643 *||Jul 12, 2004||Mar 6, 2007||Micron Technology, Inc.||Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow|
|US7196423 *||Mar 26, 2004||Mar 27, 2007||Taiwan Semiconductor Manufacturing Co., Ltd.||Interconnect structure with dielectric barrier and fabrication method thereof|
|US7199043 *||Dec 30, 2003||Apr 3, 2007||Hynix Semiconductor Inc.||Method of forming copper wiring in semiconductor device|
|US7271700 *||Feb 16, 2005||Sep 18, 2007||International Business Machines Corporation||Thin film resistor with current density enhancing layer (CDEL)|
|US20020130419 *||Apr 15, 2002||Sep 19, 2002||Micron Technology, Inc.||Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow|
|US20020132474 *||Mar 15, 2001||Sep 19, 2002||Ahn Kie Y.||Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow|
|US20040248398 *||Jul 12, 2004||Dec 9, 2004||Micron Technology, Inc.||Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow|
|US20050212135 *||Mar 26, 2004||Sep 29, 2005||Zhen-Cheng Wu||Interconnect structure with dielectric barrier and fabrication method thereof|
|US20060186549 *||Feb 16, 2006||Aug 24, 2006||Nec Electronics Corporation||Semiconductor device and method of manufacturing the same|
|US20060289993 *||Aug 29, 2006||Dec 28, 2006||Micron Technology, Inc.||Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow|
|US20070018330 *||Sep 26, 2006||Jan 25, 2007||Renesas Technology Corporation||Semiconductor device and method of manufacturing the same|
|US20070052096 *||Aug 23, 2005||Mar 8, 2007||Taiwan Semiconductor Manufacturing Co., Ltd.||Semiconductor device and method for forming the same|
|US20070182014 *||Feb 5, 2007||Aug 9, 2007||Nec Electronics Corporation||Semiconductor device and method for manufacturing same|
|U.S. Classification||438/637, 438/627, 438/638|
|Cooperative Classification||H01L2924/0002, H01L21/2855, H01L23/53238, H01L23/528, H01L21/28556, H01L23/53266, H01L21/7684, H01L21/28562, H01L21/76834, H01L21/76843, H01L21/76856, H01L21/76888|
|European Classification||H01L21/768C3D2B, H01L21/768B10S, H01L21/285B4H2, H01L21/768C3B, H01L21/768C2, H01L21/768C8B|
|Aug 23, 2005||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SU, HUNG-WEN;CHOU, SHIH-WEI;TSAI, MING-HSING;REEL/FRAME:016928/0429
Effective date: 20050815
|Dec 11, 2013||FPAY||Fee payment|
Year of fee payment: 4