|Publication number||US7759166 B2|
|Application number||US 11/582,186|
|Publication date||Jul 20, 2010|
|Filing date||Oct 17, 2006|
|Priority date||Oct 17, 2006|
|Also published as||US8241959, US20080090333, US20100270679, WO2008048643A1|
|Publication number||11582186, 582186, US 7759166 B2, US 7759166B2, US-B2-7759166, US7759166 B2, US7759166B2|
|Inventors||Belgacem Haba, Giles Humpston|
|Original Assignee||Tessera, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (29), Non-Patent Citations (5), Referenced by (24), Classifications (51), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention generally relates to microelectronic packages and more particularly relates to microelectronic packages fabricated at the wafer level and to methods of making such packages.
Semiconductor chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself. Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer or a cell phone.
The substrate materials used for packaging semiconductor chips are selected for their compatibility with the processes used to form the packages. For example, during solder or other bonding operations, intense heat may be applied to the substrate. Accordingly, metal lead frames have been used as substrates. Laminate substrates have also been used to package microelectronic devices. Such substrates may include two to four alternating layers of fiberglass and epoxy, wherein successive fiberglass layers may be laid in traversing, e.g., orthogonal, directions. Optionally, heat resistive compounds such as bismaleimide triazine (BT) may be added to such laminate substrates.
Tapes have been used as substrates to provide thinner microelectronic packages. Such tapes are typically provided in the form of sheets or rolls of sheets. For example, single and double sided sheets of copper-on-polyimide are commonly used for fine-line and high-density electronic interconnection applications. Polyimide based films offer good thermal and chemical stability and a low dielectric constant, while copper having high tensile strength, ductility, and flexure has been advantageously used in both flexible circuit and chip sized packaging applications. However, such tapes are relatively expensive, particularly as compared to lead frames and laminate substrates.
Depending on the configuration and other requirements of the microelectronic package, different substrate materials may be used. For example, in a flip-chip configuration, the front or contact-bearing surface of the microelectronic device faces towards a substrate. Each contact on the device is joined by a solder bond to a corresponding contact pad on the substrate, by positioning solder balls on the substrate or device, juxtaposing the device with the substrate, and momentarily reflowing the solder. Flip-chip configurations, however, may encounter problems in thermal expansion mismatch. When the coefficient of thermal expansion (CTE) for the device differs significantly from the CTE for the substrate, the solder connections will undergo fatigue when the package is thermally cycled. This is particularly problematic for flip-chip packages with fine pitch, small bumps, and/or large device footprints. Thus, to enhance reliability, the substrate is typically selected so that the CTE of the substrate closely matches the CTE of the device.
To improve productivity and reduce costs associated with microelectronic manufacturing, there have been many efforts directed to forming microelectronic packages at the wafer-scale level. Wafer-scale assemblies allow a plurality of devices in the form of a wafer to be packaged with a substrate as a single structure. Once formed, the wafer-scale structure is diced and separated into individual packages. However, problems associated with CTE mismatch between the wafer and the substrate are exacerbated due to the size of the wafer-scale structure. Thus, wafer-scale manufacturing of microelectronic packages may require exceptionally close matching of the CTE of the device and the substrate.
U.S. Pat. No. 6,753,208 to MacIntyre describes a chip scale package structure formed by adhering a glass sheet having a pattern of holes matching a pattern of bond pads on a semiconductor wafer so that the pattern of holes on the glass sheet are over the pattern of bond pads on the semiconductor wafer. Metallized pads are formed on the glass sheet adjacent each hole. A conductive trace is formed from each metallized pad on the glass sheet to the bond pad on the semiconductor wafer under the adjacent hole. In addition, the pad extends down the sides of the adjacent hole, which is then filled with a metal plug that electrically connects the pad on the glass sheet to the bond pad on the semiconductor wafer.
In certain embodiments of commonly assigned U.S. patent application Ser. No. 11/025,432, filed Dec. 29, 2004, the disclosure of which is hereby incorporated by reference herein, a microelectronic package includes a microelectronic device, a unitary ceramic substrate, and a plurality of terminals. The microelectronic device has a substantially planar front surface and a plurality of electrical contacts thereon. The substrate has a first substantially planar surface and a second surface opposing the first surface. A window extends from a first opening on the first surface and along a side wall to a second opening on the second surface. A conductive region may be provided on the side wall and/or the second substrate surface. Typically, but not necessarily, the window has varied cross-sectional areas along its lumen as defined by its side wall. The substrate is located between the device and the terminals such that the first surface of the substrate faces the front surface of the device and the first opening is aligned with at least one contact on the front device surface.
The device and the substrate disclosed in the '432 application may be coupled or decoupled to each other. However, there is typically substantially no void between the first surface of the substrate and the front surface of the device. For example, an adhesive may be provided between the device and the substrate. In addition, the package may include a compliant layer between the device and at least one terminal, e.g., between the at least one terminal and the substrate and/or between the device and the substrate. Accordingly, one or more terminals and the substrate may be coupled or decoupled to each other.
The device contacts of the '432 application electrically communicate with the terminals in any of a number of ways. For example, one or more device contacts may be provided in electrical communication with at least one terminal through the window via one ore more conductive regions. This may be achieved by lead bonding or wire bonding the contacts to the conductive region. Once electrical communication is achieved, an encapsulant may be dispensed into the window, optionally filling the window to a substantially void-free degree.
In further embodiments of the '432 application, a wafer-scale microelectronic assembly includes a wafer and a unitary ceramic substrate. The wafer includes an array of microelectronic devices each having a coplanar front surface and a plurality of electrical contacts thereon. The ceramic substrate has a first substantially planar surface and a second surface opposing first surface. One or more windows extend from a first opening on the first surface along a side wall to a second opening on the second surface. The windows may or may not have varied cross-sectional areas. One ore more conductive regions are located on at least one side wall or the second surface. The first surface of the substrate faces the front device surfaces, and each first opening is aligned with at least one electrical contact, typically on different devices. When the wafer has a diameter of at least 200 mm, the substrate and the device may have coefficients of thermal expansion that differ by less than about 3.0 ppm/° C. In other embodiments, the substrate and the device may have coefficients of thermal expansion that differ by less than about 0.1 ppm/° C.
Microelectronic packages also include wafer level packages, which provide an enclosure for a semiconductor component that is fabricated while the die are still in a wafer form. The wafer is subject to a number of additional process steps to form the package structure and the wafer is then diced to free the individual die, with no additional fabrication steps being necessary. Wafer level processing provides an advantage in that the cost of the packaging processes are divided among the various die on the wafer, resulting in a very low price differential between the die and the component. Furthermore, the package footprint is identical to the die size, resulting in very efficient utilization of area on a printed circuit board (PCB) to which the die will eventually be attached. As a result of these features, die packaged in this manner are commonly referred to as wafer level chip sized package (WLCSP).
Conventional wafer level packages share a common trait in that the elements required to form the package structure are built on the surface of the semiconductor wafer. This approach has the drawback that the finished high-value semiconductor wafer is subject to an appreciable number of additional process steps. Thus, a process failure during any one of the packaging steps risks loss of the entire wafer. Thus, there is a need for an alternative approach to building most of the elements of wafer level packages so as to avoid loosing entire wafers during the packaging processes.
In spite of the above advances, there remains a need for improved wafer-scale packages that are cheaper, smaller and lighter and to methods of manufacturing such wafer-scale packages that are economical and reliable.
In one embodiment of the present invention, a method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with the openings extending through the plate, and providing electrically conductive features on the compliant layer. The electrically conductive features may include conductive traces, conductive bond ribbons, conductive terminals, conductive bumps, solder masses, conductive bond pads and/or conductive posts. A dielectric material such as a solder mask or a dielectric film may be provided over at least one of the electrically conductive features on the compliant layer.
After making the subassembly, a semiconductor wafer having a top surface and contacts accessible at the top surface is juxtaposed with the plate. The bottom surface of the plate is attached to the top surface of the semiconductor wafer so that the openings extending through the plate are aligned with the contacts on the wafer. At least some of the electrically conductive features on the compliant layer are electrically interconnected with the contacts on the semiconductor wafer. The electrical interconnections may be made by forming a wire bond between the contacts on the wafer and the electrically conductive features on the compliant layer. After the electrically interconnecting step, the wire bonds may be encapsulated with an encapsulant material such as an epoxy, a silicone or a compliant material. The encapsulant may be transparent, opaque, or have a level of transparency that falls anywhere between transparent and opaque.
In certain embodiments, the compliant layer is attached to the plate using an adhesive and the plate is attached to the semiconductor using an adhesive. The adhesive is preferably attached to the bottom of the plate before the plate is abutted against the semiconductor wafer. The plate is desirably made of a dielectric material. The plate may be rigid and preferably has a coefficient of thermal expansion that matches the coefficient of thermal expansion of the semiconductor wafer. The plate may be made of a material selected from the group consisting of glass and silicon.
In one embodiment, the openings in the plate have larger diameters at the top surface of the plate and smaller diameters at the bottom surface of the plate. The openings in the plate preferably have side walls, which may be tapered between the top and bottom surfaces of the plate. The electrically conductive features desirably extend into the openings in the plate. At least some of the side walls may include a ledge and the electrically conductive features may extend onto the ledges.
In another embodiment of the present invention, a method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface, and openings extending between the top and bottom surfaces, the plate including ledges extending into each opening so that each opening has a larger diameter adjacent the top surface of the plate and a smaller diameter adjacent the bottom surface of the plate. The method includes attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with the openings extending through the plate, and providing electrically conductive features on the compliant layer, whereby at least some of the electrically conductive features extend onto and/or are provided on the ledges extending into each of the openings. At least some of the electrically conductive features are accessible at the top surface of the compliant layer. After the subassembly is made in accordance with the steps outlined above, the bottom surface of the plate is juxtaposed with a semiconductor wafer having a top surface and contacts accessible at the top surface. The bottom surface of the plate is attached with the top surface of the semiconductor wafer so that the openings extending through the plate are aligned with the contacts on the wafer. The contacts on the wafer are desirably electrically interconnected with the electrically conductive features provided on the ledges. After the electrically interconnecting step, the semiconductor wafer may be diced or severed to provide a plurality of microelectronic packages having one or more die.
In one embodiment, the compliant layer may include a plurality of compliant bumps that are spaced from one another. In other embodiments, the electrically conductive features may be formed by plating conductive posts atop the conductive features so that the conductive posts project from the top surface of the compliant layer.
In another embodiment of the present invention, a method of making microelectronic packages includes providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a flexible dielectric substrate to the top surface of the plate, the flexible dielectric substrate having openings extending therethrough that are aligned with the openings extending through the plate, and providing electrically conductive features on the flexible dielectric substrate, such as conductive terminals, conductive pads, conductive traces, conductive posts, etc. The method desirably includes providing a semiconductor wafer having a top surface and contacts accessible at the top surface and attaching the bottom surface of the plate with the top surface of the semiconductor wafer so that the openings extending through the plate are aligned with the contacts on the wafer. At least some of the electrically conductive features on the flexible dielectric substrate are desirably electrically interconnected with the contacts on the semiconductor wafer. The flexible dielectric substrate may be compliant and/or a compliant layer may be provided between the flexible dielectric substrate and the plate.
In yet another embodiment of the present invention, a method of making a microelectronic assembly includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, and attaching a compliant layer to the top surface of the plate. The compliant layer may have openings that are aligned with the openings extending through the plate. The method desirably include providing electrically conductive features on the compliant layer, and after making the subassembly, juxtaposing the bottom surface of the plate with a semiconductor wafer having a top surface and contacts accessible at the top surface. The bottom surface of the plate is desirably attached with the top surface of the semiconductor wafer so that the openings extending through the plate are aligned with the contacts on the semiconductor wafer. At least some of the electrically conductive features on the compliant layer are desirably electrically interconnected with the contacts on the semiconductor wafer.
The attaching a compliant layer step may include disposing an adhesive layer between the compliant layer and the top surface of the plate for attaching the compliant layer to the plate. The step of attaching the bottom surface of the plate to the wafer may include applying a second adhesive layer to the bottom surface of the plate and abutting the second adhesive layer against the top surface of the semiconductor wafer.
In certain embodiments, the plate may have a thickness that varies. In one embodiment, the plate has a reduced thickness adjacent at least one of the openings extending through the plate. The plate may have a shelf adjacent at least one of the openings extending through the plate, the shelf defining a wire bonding land that is located between the top surface of the plate and the bottom surface of the plate. The electrically conductive features on the compliant layer may include conductive traces with at least one of the conductive traces extending to the wire bonding land provided on the shelf of the plate. The electrically interconnecting step may include attaching a first end of a wire bond to one of the contacts on the semiconductor wafer and a second end of the wire bond to the wire bonding land provided on the shelf of the plate.
These and other embodiments of the present invention will be described in more detail below.
The invention disclosed herein is not limited to the specific microelectronic devices or types of electronic products shown and described herein. Moreover, the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.
As used in this specification and the appended claims, the singular article forms “a,” “an,” and “the” include both singular and plural items unless the context clearly dictates otherwise. Thus, for example, reference to “a conductive region,” includes a plurality of conductive regions as well as a single conductive region. Reference to “a microelectronic device” includes a single device as well as a combination of devices, and the like.
In addition, terminology indicative or suggestive of a particular spatial relationship between elements of the invention is to be construed in a relative sense rather than an absolute sense unless the context of usage clearly dictates to the contrary. For example, the term “face-down” as used to describe the spatial orientation of the device does not necessarily indicate that the front surface of the device represents the lowest point of the device. In addition, a “substrate” is not necessarily located below another element, e.g., a microelectronic device of the microelectronic package. Thus, in a package that includes a substrate and a device in a face-down orientation, the substrate may be located above, at the same level, or below the front device surface depending on the package's orientation.
As shown in
As shown in
An adhesive 74 may be used to bond the microelectronic device 52 to the substrate 60. As shown in
A plurality of terminals 76 are provided on the second surface 64 of the substrate 60. Electrically conductive regions 78 in the form of wiring traces may be provided in electrical communication with the terminals. The terminals and the wire traces may comprise one or more electrically conductive materials, and may be formed of the same or different materials.
The substrate 60 and the terminals 76 may be provided as a unitary item. That is, the substrate may be complete with conductive regions 78 in the form wire traces in contact with the terminals 76 before bonding to the microelectronic device 52. Solder 80 and solder resist 82 may be placed on the second surface 64 of the substrate 60 as well. Alternatively, the terminals 76, conductive regions 78, and/or solder 80 may be placed on the substrate 60 after the substrate is bonded to the microelectronic device 52.
As shown in
Alternatively, the window in the substrate may have a different geometry and/or shape, whereby a first opening of the window has a smaller cross-sectional area than that of the second opening. The cross-sectional area of the larger opening may range from twice as large to many times larger than that of the smaller opening. Accordingly, as the window extends between the first and second openings, the window has varied cross-sectional areas along its lumen as defined by its side wall.
It is well known to those skilled in the art that semiconductor wafers are high value items. Thus, it is preferable to minimize as many handling or processing steps of the wafer as is possible, and the present invention seeks to limit the number of processing steps to an absolute minimal. In certain embodiments, the steps are limited to lamination of a subassembly to the wafer and wire bonding the electrical contacts on the subassembly with the conductive pads on a wafer. Both of these steps are well-known by those skilled in the art to be high yielding and easily accomplished. Thus, the basis of the present invention is to fabricate the elements of a wafer level package structure, i.e., redistribution, compliance, solder spheres, conductive protrusions, etc. on an intermediate plate. The intermediate plate is preferably a dielectric material such as glass or silicon that has a coefficient of thermal expansion that is close to or matches that of the semiconductor wafer. The intermediate plate is attached to the wafer only after most or all of the features necessary for forming a reliable electrical interconnection have been formed on the intermediate plate. Because the majority of the processing steps necessary to create the wafer level package are accomplished on the plate before the plate is assembled with the wafer, any yield loss at this preliminary stage does not involve a loss of a semiconductor wafer.
The close match in the coefficient of thermal expansion between the plate and the wafer is desirable because many adhesive joining processes used in the semiconductor industry involve using heat. If the coefficients of thermal expansion are not close or matched, the differences in expansion between the two parts can result in misalignment of the assembled package. Moreover, the fatigue life of the package will generally be longer when subject to thermal cycling or shock if the materials used to fabricate the package have coefficients of thermal expansion that are similar or matched.
After the subassembly including the plate and the flexible dielectric substrate with conductive posts 322 has been assembled, the subassembly is juxtaposed with a semiconductor wafer 315 so that the bottom surface 306 of the plate 302 faces the contact bearing surface of the semiconductor wafer. In addition, the window 308 extending through the plate 302 is aligned with the conductive pads 324 providing on the semiconductor wafer 315.
After the subassembly shown in
Although the present invention is not limited by any particular theory of operation, it is believed that providing the plate 402 with a ledge enables the exposed surface of the encapsulant 430 to be flush or evenly recessed with respect to the conductive features 422, 414 provided at the exterior face of the subassembly. Thus, the ledge enables the encapsulant to have a lower overall height or profile, whereby the encapsulant 430 does not project above the compliant layer 412. The lower profile facilitates testing the wafer level chip sized package and mounting of the individual chip packages on a printed circuit board.
In one embodiment, in order to facilitate the creation of a low profile wire bond, a ball bond connection is formed with the conductive pad 424 and a wedge bond connection is formed with the conductive ledge 409. It is well-known to those skilled in the art that a wedge bond typically has a height that is ⅓ the height of a ball bond. Moreover, in a standard wire bonding step, the wire bond interconnect typically starts with a ball bond and terminates in a wedge bond. Thus, in some embodiments, it is preferable to first connect the wire bond with the conductive pad 424 on the wafer before connecting it with the conductive feature 409 provided on the ledge of the plate 402.
A standard wafer level chip sized package structure requires that a number of planar layers be built up on the surface of the wafer. These layers are mostly formed by dispensing a liquid that is cured to form a solid material. Conventionally, these curable materials are applied directly to the wafer surface for providing a number of functions such as mechanical protection of the wafer surface, environmental protection of the wafer surface and mechanical compliance between the solders sphere and the silicon die.
All but the very smallest wafer level chip sized packages require some mechanical compliance between the solders spheres used to attach the package to a printed circuit board and the die. Such compliance is required because silicon has a much lower of coefficient of thermal expansion than the materials used to make a printed circuit board. Thus, if the assembled package experiences changes in temperature, the printed circuit board and the die will expand and contract by different amounts, with the resulting differential strain inducing fatigue failure of the solder connections. By incorporating a low modulus but extremely elastic layer, i.e., a “compliant” layer in the assembly, the strain will be absorbed by that material rather than by the solders spheres.
Although the material selected for the compliant layer have low modulus, they also are predominately high thermal expansivity materials and undergo significant volume change on curing. This is due to the fact that the compliant layer having low modulus is typically a polymeric material. Due to the properties of the compliant layer, the application of thick layers of compliant material directly onto the surface of a semiconductor wafer will exert sufficient force on the semiconductor wafer to cause it to bow. As is well-known to those skilled in the art, semiconductor wafers must be manufactured to exacting standards of flatness because any bow or warp may create major problems with subsequent processes that involve spin-on films or optical alignment steps. For this reason, with conventional packages, the thickness of compliant films used to form wafer level chip sized packages is often less than ideal for maximum life and reliability of the solder interconnects to the printed circuit board.
In particular embodiments of the present invention, compliant layers of virtually any thickness may be provided over the intermediate plate (e.g., plate 302 in
In other embodiments, the compliant layer may comprise a plurality of compliant bumps that are provided on one surface of the intermediate plate. This structure, commonly referred to as islanding of the compliant layer, is possible because the intermediate plate provides the required environmental and mechanical protection to the semiconductor wafer in the area between the compliant bumps. In conventional wafer layer chip sized packages, if the compliant layer is discontinuous, there will be regions of the wafer surface that are exposed and that are therefore vulnerable to damage. With islands of compliant bumps, however, subdivision of the compliant layer prevents the accumulation of differential strain so that the wafer remains flat.
In certain embodiments, the compliant bumps may be disposed atop the plate 502 using deposition processes such as screen printing whereby a controlled quantity of curable material may be deposited at defined locations. In certain embodiments, silicones are deposited and cured as relatively tall sessile drops. In other embodiments, photo-imageable materials may be applied as a film and then selectively removed to yield similar structures.
The formation of the shorter conductive post 627 and the taller conductive post 622 are particularly important in the present invention. This is because these structures may be formed using a plating operation. Although plating on wafers is practiced commercially, the number of process steps involved represents a significant risk to the final component yield. Furthermore, if the intermediate plate is made of glass or a similar material, such material is considerably more inert toward the constituents of the plating bath than silicon, thereby permitting a wider range of chemistries to be used, which provides material, process and economic advantages. As a result, the short or tall conductive posts 627, 622 may be formed of copper, silver, nickel, tin, gold or combinations of these metals either as alloys or in layers. Nickel and copper-based posts in particular can encompass a wide range of heights suitable for a number of applications.
In the assembly shown in
Although the present invention is not limited by any particular theory of operation, it is believed that providing an intermediate plate having a structure shown in
The microelectronic assembly shown in
In order to provide reliable electrical contacts to lands on a printed circuit board during electrical tests and subsequent solder attach processes, the conductive posts 922 are preferable finished with thin layers of nickel, then gold. These metals are preferably applied by a plating process. The nature of electro and electroless plating processes is that all exposed copper parts will be coated. However, as it is only the conductive posts 922 that need to be coated and gold is a relatively expensive metal, some reduction in part cost is likely if the flexile circuit is only coated with these metals after it has been cut to size and laminated to the intermediate plate. In structures that do not contain an intermediate plate, the semiconductor wafer must also be passed through the plating process, and hence it is at risk owing to breakage or process malfunction.
In the microelectronic assembly shown in
The assembly shown in
One of the difficulties of making the assembly shown in
The availability of a rigid backing plate for the wiring traces and conductive posts affords the possibility of using plating technologies to form both features through a combination of etching and plating processes. Referring to
In another embodiment, referring to
One advantage of completing the fabrication of the conductive traces and posts after laminating them to the intermediate plate 1202 is a saving in the cost of nickel and particularly gold used as a surface finish. Flexible circuits are conventionally prepared in the form of large rectangular sheets of material, so that when immersed in the plating vats, all exposed metal will be coated with nickel and gold. With the structure shown in
Variations of the present invention will be apparent to those of ordinary skill in the art in view of the disclosure contained herein. For example, while the unitary substrates have generally been depicted herein as formed from a single piece, a plurality of pieces may be joined to form a unitary substrate. In addition, solders, conductive pastes, and other electrical connection technologies known in the art may be employed to effect electrical communication between any items of the invention. Furthermore, the inventive packages and assemblies may serve to provide mechanical support to the packaged device or wafer to facilitate their back-grinding. Additional variations of the invention may be discovered upon routine experimentation without departing from the spirit of the present invention.
All patents and patent applications mentioned herein are hereby incorporated by reference in their entireties.
In certain embodiments of the present invention, a particle coating such as that disclosed in U.S. Pat. Nos. 4,804,132 and 5,083,697, the disclosures of which are incorporated by reference herein, may be provided on one or more electrically conductive parts of a microelectronic package for enhancing the formation of electrical interconnections between microelectronic elements and for facilitating testing of microelectronic packages. The particle coating is preferably provided over conductive parts such as conductive terminals or the tip ends of conductive posts. In one embodiment, the particle coating is a metalized diamond crystal coating that is selectively electroplated onto the conductive parts of a microelectronic element using standard photoresist techniques. In operation, a conductive part with the diamond crystal coating may be pressed onto an opposing contact pad for piercing the oxidation layer present at the outer surface of the contact pad. The diamond crystal coating facilitates the formation of reliable electrical interconnections through penetration of oxide layers, in addition to traditional wiping action.
As discussed above, the motion of the posts may include a tilting motion. This tilting motion causes the tip of each post to wipe across the contact pad as the tip is engaged with the contact pad. This promotes reliable electrical contact. As discussed in greater detail in the co-pending, commonly assigned application Ser. No. 10/985,126 filed Nov. 10, 2004, entitled “MICRO PIN GRID ARRAY WITH WIPING ACTION,” the disclosure of which is incorporated by reference herein, the posts may be provided with features which promote such wiping action and otherwise facilitate engagement of the posts and contacts. As disclosed in greater detail in the co-pending, commonly assigned application Ser. No. 10/985,119 filed Nov. 10, 2004, entitled “MICRO PIN GRID WITH PIN MOTION ISOLATION,” the disclosure of which is also incorporated by reference herein, the flexible substrate may be provided with features to enhance the ability of the posts to move independently of one another and which enhance the tilting and wiping action. The present application may also include one or more features of the embodiments disclosed in commonly assigned U.S. provisional application Ser. No. 60/753,605, filed Dec. 23, 2005, the disclosure of which is hereby incorporated by reference herein.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is, therefore, to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
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|U.S. Classification||438/118, 257/E21.511, 438/613, 438/612, 257/737|
|Cooperative Classification||H01L2224/13, H01L2224/11, H01L2924/15787, H01L24/11, H01L24/13, H01L2924/00014, H01L2224/1403, H01L2924/01082, H01L2924/15312, H01L2224/0401, H01L2924/014, H01L2924/01079, H01L2924/01078, H01L2924/01033, H01L2924/01083, H01L2924/01027, H01L2224/13099, H01L2224/114, H01L2224/1147, H01L23/525, H01L2924/01005, H01L2924/01014, H01L2224/484, H01L2924/01028, H01L2224/32225, H01L2924/01047, H01L2924/01006, H01L2924/01029, H01L2224/48091, H01L2924/30107, H01L2224/4824, H01L2224/73215, H01L2224/0603, H01L24/48, H01L2924/0105, H01L2924/30105, H01L2924/15311, H01L2224/116, H01L2224/05599, H01L23/3114, H01L2924/10253|
|European Classification||H01L24/48, H01L24/10, H01L23/525, H01L23/31H1|
|Feb 12, 2007||AS||Assignment|
Owner name: TESSERA, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HABA, BELGACEM;HUMPSTON, GILES;REEL/FRAME:018892/0951;SIGNING DATES FROM 20061215 TO 20070126
Owner name: TESSERA, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HABA, BELGACEM;HUMPSTON, GILES;SIGNING DATES FROM 20061215 TO 20070126;REEL/FRAME:018892/0951
|Dec 27, 2013||FPAY||Fee payment|
Year of fee payment: 4
|Dec 2, 2016||AS||Assignment|
Owner name: ROYAL BANK OF CANADA, AS COLLATERAL AGENT, CANADA
Free format text: SECURITY INTEREST;ASSIGNORS:INVENSAS CORPORATION;TESSERA, INC.;TESSERA ADVANCED TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040797/0001
Effective date: 20161201