|Publication number||US7772094 B2|
|Application number||US 12/345,414|
|Publication date||Aug 10, 2010|
|Priority date||Dec 28, 2007|
|Also published as||US20090170277|
|Publication number||12345414, 345414, US 7772094 B2, US 7772094B2, US-B2-7772094, US7772094 B2, US7772094B2|
|Inventors||Mahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta|
|Original Assignee||Texas Instuments Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (2), Classifications (14), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the priority of U.S. Provisional Application Ser. No. 61/017,355, filed Dec. 28, 2007, entitled “Implant Damage of Layer for Easy Removal and Reduced Silicon Recess”.
The present invention relates generally to semiconductor processing, and more particularly to a method for improving removal rates of a layer formed over a substrate.
In the fabrication of semiconductor integrated circuits (ICs), various structures and circuitry are typically formed on a semiconductor workpiece using a variety of techniques. For instance, various structures are formed, defined and/or electrically isolated from one another in the semiconductor workpiece utilizing various masking and etching processes. As feature sizes become smaller and smaller to accommodate increasing device densities, proper process control is of great importance.
One common technique utilized in defining structures is photolithography. In optical photolithography, for example, an optical mask is typically utilized to produce a pattern in a photoresist layer, wherein the photoresist layer overlies one or more other layers previously formed over a semiconductor substrate. The optical mask is positioned between the photoresist layer and a radiation source, and the photoresist layer is subjected to radiation, such as a visible light or ultraviolet radiation. Portions of the optical mask conventionally comprise a patterned opaque layer, (e.g., chromium), wherein the opaque layer prevents exposure of the underlying photoresist layer. Remaining portions of the optical mask, on the other hand, are transparent, thus allowing exposure of the underlying photoresist layer. Accordingly, an image of the optical mask is reproduced on the photoresist layer via the exposure of the photoresist layer to the radiation through the optical mask.
After exposure, a developer solution is typically introduced to the workpiece, wherein, depending on the type of photoresist material utilized (e.g., positive type or negative type), exposed photoresist material is either removed by the developer solution, or the exposed photoresist material becomes more resistant to dissolution by the developer solution. Thus, a patterned photoresist layer is accordingly formed over the one or more layers, wherein portions of the one or more layers are generally exposed. Material from the one or more layers is then selectively removed, such as by wet or dry etching, therein defining the desired various structures in the workpiece. Adequate control of both the photolithographic process, as well as the etch processes is thus important in achieving the desired resultant semiconductor device(s).
One problem experienced with conventional optical photolithography is a difficulty of obtaining uniform exposure of the photoresist layer underlying transparent portions of the mask. Generally, it is desirable that the light intensity exposing the photoresist be uniform to obtain optimum results. When substantially thick layers of photoresist material are used, the photoresist layer becomes partially transparent upon exposure, such that photoresist material at the surface of the underlying one or more layers is exposed a substantially similar extent as the photoresist at the outer surface. However, light that penetrates the photoresist is often reflected back toward the light source from the surface of the underlying one or more layers formed on the substrate. The angle at which the light is reflected is generally dependent on the topography of the surface of the underlying one or more layers and the type of material of the one or more layers. Further, the reflected light intensity can vary in the photoresist layer throughout its depth or partially though its depth, leading to non-uniform exposure and/or undesirable exposure of the photoresist material. Such exposure of the photoresist layer can lead to poorly controlled dimensions on features (e.g., gates, metal lines, etc.) of the IC.
In an attempt to minimize the variable reflection of light in a photoresist layer, antireflective coatings have been utilized. For example, an antireflective coating is formed over the one or more layers of the workpiece prior to the formation of the photoresist layer. Such antireflective coatings minimize photoresist exposure from surface reflections, and allow exposure across the photoresist layer to be controlled more easily from the radiation emitted from the radiation source incident on the photoresist material.
Antireflective coatings can comprise organic or inorganic materials. For example, inorganic materials, such as silicon-rich silicon dioxide, silicon-rich nitride, and silicon-rich oxynitride, have been utilized quite successfully as antireflective coatings, such as in the patterning of metal lines and polysilicon gates.
The IARC layer 18 is likewise unnecessary and undesirable for further processing. Accordingly,
A well known electrical isolation technique is called trench isolation. In trench isolation, a trench is etched in the substrate and then filled with deposited oxide. Trench isolation is referred to as shallow trench isolation (STI) or deep trench isolation (DTI), depending on the depth of the trench etched in the substrate.
Subsequently, the nitride layer 36 is “pulled back” (e.g., via hot phosphoric acid) to reveal corners 40 of the semiconductor substrate 34 for subsequent oxidation treatment, as illustrated in
Accordingly, a method for semiconductor processing is provided that overcomes critical dimension losses and other shortcomings of the related art. The following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present disclosure is generally directed toward a method for semiconductor processing, wherein a semiconductor substrate having one or more primary layers formed thereon is provided, therein generally defining a semiconductor workpiece. A secondary layer is formed over the one or more primary layers, and one or more species of ions are implanted into the secondary layer, therein structurally weakening the secondary layer. A patterned photoresist layer is formed over the secondary layer, and respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, such as by etching. The patterned photoresist layer is then removed, and at least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer caused by the ion implantation generally increases a removal rate of the at least another portion of the secondary layer.
In accordance with one aspect, the one or more primary layers, for example, comprise a polysilicon layer formed over an oxide layer, such as a gate oxide layer, wherein the secondary layer comprises an inorganic antireflective coating formed over the polysilicon layer. Accordingly, in this example, the removal of at least another portion of the secondary layer comprises removing all of the remaining inorganic antireflective coating. The removal of the at least another portion of the secondary layer, for example, comprises etching at least the secondary layer with hot phosphoric acid. The removal of respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer may further comprise removing at least a portion of the semiconductor substrate not covered by the patterned photoresist layer.
In accordance with another aspect, the secondary layer comprises a nitride layer, such as a shallow trench isolation nitride layer, and wherein the one or more primary layers comprise a pad oxide layer. In this example, the one or more species of ions are implanted into the nitride layer, thus structurally weakening the nitride layer. In another example, removing at least another portion of the secondary layer comprises etching the nitride layer a predetermined amount using hot phosphoric acid, thus exposing corners of active semiconductor substrate disposed thereunder. The removal of at least another portion of the secondary layer may further comprise undercutting the pad oxide layer a predetermined amount using diluted hydrofluoric acid. It is noted that once the nitride is structurally weakened and the at least another portion of the nitride layer is removed, further annealing of the workpiece may take place, where the nitride layer is strengthened.
In accordance with another embodiment, the implant is done after the trench has been filled with oxide and the surface polished back with chemical mechanical polishing (CMP). The nitride and oxide can be removed uniformly in the subsequent hot phosphoric acid strip leading to a more uniform and smaller STI step height. STI step height control is important for improved SRAM yield where transistors are densely packed together.
In accordance with yet another example, the one or more species of ions comprise one or more of argon, arsenic, antimony, indium, and germanium. The implantation of the one or more ion species into the secondary layer, in a preferred embodiment, comprises an ion implantation having a dosage of approximately 1×1015 ions/cm2 or greater, wherein the ion implantation is limited in depth to the secondary layer.
Thus, to the accomplishment of the foregoing and related ends, the disclosure comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the disclosure. These embodiments are indicative, however, of a few of the various ways in which the principles of the disclosure may be employed. Other objects, advantages and novel features of the disclosure will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
The present disclosure is generally directed towards a method for aiding removal of a layer formed during semiconductor processing of a workpiece. In particular, the present disclosure provides a method for structurally weakening the layer via an ion implantation, wherein the structural weakening of the layer generally increases a subsequent removal rate of the layer. Accordingly, the present disclosure will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. It should be understood that the description of these aspects are merely illustrative and that they should not be taken in a limiting sense. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident to one skilled in the art, however, that the present disclosure may be practiced without these specific details.
In accordance with the present disclosure,
The method 100 begins with providing a semiconductor workpiece (e.g., a silicon substrate) having one or more primary layers formed thereon in act 105. A composition and number of the one or more primary layers can vary, depending on the desired resultant structure of the semiconductor process. In order to gain a better understanding of the disclosure, several example embodiments of the method 100 of
In a first embodiment, as illustrated in cross-section in
Referring again to
In accordance with the disclosure, one or more ions species are implanted into the secondary layer in act 115 of
The dosage of the ion implantation, for example, is selected such that the dosage is substantial to cause structural damage in the desired layer. Accordingly, by selecting the species, energy, and dosage of the ion implantation, properties of the one or more primary layers and semiconductor substrate remain generally unaffected, while the ion implantation still provides a substantial structural weakening of the secondary layer.
Again referring to
Accordingly, the patterned photoresist layer 235 is removed in act 130 of
Thus, according to the present disclosure, the structural weakening of the secondary layer caused by the ion implantation of act 115 of
Act 120 of
As illustrated in
Furthermore, subsequent processing of the workpiece 300 may be performed after the at least a portion of the nitride layer 317 is removed, wherein an annealing of the remaining nitride layer can be performed to again structurally strengthen the nitride layer. Such a strengthening of the nitride layer 317 thus facilitates the nitride layer to again act as a stop for subsequent chemical mechanical polishing of the workpiece.
In yet another alternative embodiment, the ion implantation 115 of
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.” Also, “exemplary” as utilized herein merely means an example, rather than the best.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5883011||Jun 18, 1997||Mar 16, 1999||Vlsi Technology, Inc.||Method of removing an inorganic antireflective coating from a semiconductor substrate|
|US6121133||Aug 22, 1997||Sep 19, 2000||Micron Technology, Inc.||Isolation using an antireflective coating|
|US6403151||Apr 18, 2000||Jun 11, 2002||Advanced Micro Devices, Inc.||Method for controlling optical properties of antireflective coatings|
|US7115524||May 17, 2004||Oct 3, 2006||Micron Technology, Inc.||Methods of processing a semiconductor substrate|
|US7229891 *||Mar 6, 2001||Jun 12, 2007||John Howard Coleman||Fabrication method for silicon-on defect layer in field-effect and bipolar transistor devices|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8749866||Dec 15, 2011||Jun 10, 2014||Northrop Grumman Systems Corporation||Plasmonic modulator incorporating a solid-state phase change material|
|WO2013089969A1 *||Nov 16, 2012||Jun 20, 2013||Northrop Grumman Systems Corporation||Plasmonic modulator incorporating a solid-state phase change material|
|U.S. Classification||438/473, 438/514, 257/E21.214, 438/528, 257/607|
|Cooperative Classification||H01L21/76254, H01L21/3086, H01L21/31111, H01L21/32139|
|European Classification||H01L21/762D8B, H01L21/3213D, H01L21/311B2, H01L21/308D4|
|Mar 2, 2009||AS||Assignment|
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NANDAKUMAR, MAHALINGAM;BATHER, WAYNE;MEHTA, NARENDRA SINGH;REEL/FRAME:022334/0806;SIGNING DATES FROM 19970825 TO 20080917
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NANDAKUMAR, MAHALINGAM;BATHER, WAYNE;MEHTA, NARENDRA SINGH;SIGNING DATES FROM 19970825 TO 20080917;REEL/FRAME:022334/0806
|Jan 28, 2014||FPAY||Fee payment|
Year of fee payment: 4