|Publication number||US7785950 B2|
|Application number||US 11/164,114|
|Publication date||Aug 31, 2010|
|Filing date||Nov 10, 2005|
|Priority date||Nov 10, 2005|
|Also published as||CN1971882A, CN100570860C, US20070105299|
|Publication number||11164114, 164114, US 7785950 B2, US 7785950B2, US-B2-7785950, US7785950 B2, US7785950B2|
|Inventors||Sunfei Fang, Jun Jung Kim, Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Young Way Teh|
|Original Assignee||International Business Machines Corporation, Samsung Electronics Co., Ltd, Chartered Semiconductor Manufacturing Ltd|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (105), Non-Patent Citations (26), Referenced by (2), Classifications (9), Legal Events (2) |
|External Links: USPTO, USPTO Assignment, Espacenet|
Dual stress memory technique method and related structure
US 7785950 B2
A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.
1. A method of providing a dual stress memory technique in a semiconductor device including an nFET and a pFET, the method comprising:
forming a first stress layer over the nFET and the pFET, wherein the first stress layer is an intrinsically compressive stressed layer
forming an etch stop layer over the first stress layer;
removing the first stress layer and the etch stop layer over the nFET
forming a second stress layer over a remaining portion of the first stress layer and the nFET, wherein the second stress layer is a tensilely stressed silicon nitride layer;
annealing to memorize stress in the nFET and the pFET, wherein the remaining portion of the first stress layer remains over the pFET during the annealing, and the second stress layer remains over both the nFET and the pFET during the annealing; and;
removing the first and second stress layers and the etch stop layer in their entirety, wherein the memorized stress is retained in the nFET and the pFET after the annealing and the removing of the first and second stress layers.
2. The method of claim 1, wherein the compressive stress silicon nitride includes a high density plasma (HDP) silicon nitride.
3. The method of claim 1, further comprising the step of depositing an additional etch stop layer prior to the first stress layer forming step.
4. The method of claim 1, wherein the compressive stress silicon nitride has a magnitude of stress of no less than 100 MPa after the annealing.
5. The method of claim 1, wherein the annealing step includes using a temperature of no less than approximately 400° C. and no greater than approximately 1200° C.
6. The method of claim 1, wherein each stress layer includes silicon nitride.
7. The method of claim 1, wherein the etch stop layer includes silicon dioxide.
8. A method of providing a dual stress memory technique for a semiconductor device including an nFET and a pFET, the method comprising:
forming a tensile stress layer over only the nFET and forming a compressive stress layer over the pFET and the tensile stress layer overlying the nFET, wherein the compressive stress layer includes silicon nitride;
annealing to memorize stress in the nFET and the pFET, wherein the tensile stress layer remains over only the nFET and the compressive stress layer remains over the pFET and the tensile stress layer overlying the nFET during the annealing; and
removing the compressive and tensile stress layers in their entirety, wherein the memorized stress is retained in the nFET and the pFET after the annealing and the removing of the compressive and tensile stress layers.
9. The method of claim 8, wherein the compressive stress layer forming step includes performing a high density plasma (HDP) deposition of the silicon nitride using the following conditions: approximately 50 mTorr of pressure, approximately 200 standard cubic centimeters (sccm) argon (Ar), approximately 100 sccm of silane (SiH4), approximately 300 sccm of nitrogen (N2), approximately 0-1500 W of radio frequency (RF) bias power and approximately 2000 W-4500 W of RF source power.
10. The method of claim 8, wherein the annealing step includes using a temperature of no less than approximately 400° C. and no greater than approximately 1200 ° C.
11. The method of claim 8, wherein the tensile stress layer includes silicon nitride.
12. The method of claim 8
, wherein the forming step includes:
forming the tensile stress layer over the nFET and the pFET;
forming an etch stop layer over the tensile stress layer;
removing the tensile stress layer and the etch stop layer over the pFET; and
forming the compressive stress layer over a remaining portion of the tensile stress layer and the pFET.
13. The method of claim 12, wherein the etch stop layer includes silicon dioxide.
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to stress memory techniques, and more particularly, to a method of providing a dual stress memory technique and related structure.
2. Background Art
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (nFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (pFET) drive currents).
One manner of providing this stress is referred to as stress memorization technique (SMT), which includes applying an intrinsically stressed material (e.g., silicon nitride) over a channel region and annealing to have the stress memorized in, for example, the gate polysilicon or the diffusion regions. The stressed material is then removed. The stress, however, remains and improves electron or hole mobility, which improves overall performance. The anneal is typically provided as part of a dopant activation anneal.
One problem with SMT is that it is applicable only to n-type field effect transistors (nFETs). In particular, while a compressively stressed silicon nitride layer can be formed over a pFET to impart a compressive stress, the stress is removed for the most part by the subsequent and requisite dopant activation anneal. That is, most of the compressive stress is not memorized in the pFET.
In view of the foregoing, there is a need in the art to provide SMT for both nFETs and pFETs.
SUMMARY OF THE INVENTION
A method for providing a dual stress memory technique in a semiconductor device including an nFET and a pFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.
A first aspect of the invention provides a method of providing a dual stress memory technique in a semiconductor device including an nFET and a pFET, the method comprising the steps of: forming a first stress layer over the semiconductor device; forming an etch stop layer over the first stress layer; removing the first stress layer and the etch stop layer over a first one of the nFET and the pFET; forming a second stress layer over the semiconductor device, wherein a stress layer over the pFET includes a compressive stress silicon nitride; annealing to memorize stress in the semiconductor device; and removing the first and second stress layer and the etch stop layer.
A second aspect of the invention provides a method of providing a dual stress memory technique for a semiconductor device including an nFET and a pFET, the method comprising the steps of: forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, wherein the compressive stress layer include a high stress film that retains at least partial compressive stress during a subsequent anneal; annealing to memorize stress in the semiconductor device; and removing the compressive and tensile stress layers.
A third aspect of the invention provides a semiconductor device comprising: an nFET having a tensile stress memorized into a part thereof; and a pFET having a compressive stress memorized into a part thereof.
The illustrative aspects of the present invention are designed to solve the problems herein described and other problems not discussed, which are discoverable by a skilled artisan.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which:
FIG. 1 shows a preliminary structure for one embodiment of a method according to the invention.
FIGS. 2-7 show a method according to one embodiment of the invention.
It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
Turning to the drawings, FIG. 1 shows a preliminary structure for one embodiment of a method of providing a dual stress memory technique (SMT) for a semiconductor device 100. The preliminary structure includes a substrate 102 having an n-type field effect transistor (nFET) 104 and a p-type field effect transistor (pFET) 106 formed thereon. As shown, semiconductor device 100 has completed initial processing such as conventional shallow trench isolation (STI) 110 formation, well implants, gate dielectric 112 formation, gate conductor 114 formation, and extension/halo/source/drain implants for diffusions 116.
Referring to FIG. 2, in one embodiment of the method, a first step includes forming a tensile stress layer 120 over nFET 104 and a compressive stress layer 122 over pFET 106. Both tensile stress layer 120 and compressive stress layer 122 may include intrinsically stressed silicon nitride (Si3N4). In one preferred embodiment, however, compressive stress layer 122 includes a high density plasma (HDP) silicon nitride (Si3N4), i.e., a silicon nitride formed using a high density plasma deposition process. In one preferred embodiment, the compressive stress layer forming step includes performing a HDP deposition of silicon nitride using the following conditions: approximately 50 mTorr of pressure, approximately 200 standard cubic centimeters (sccm) of argon (Ar), approximately 100 sccm of silane (SiH4), approximately 300 sccm of nitrogen (N2), approximately 0-1500 W of radio frequency (RF) bias power and approximately 2000W-4500W of RF source power. Compressive stress layer 122 thus includes a high stress silicon nitride that enables provision of the dual SMT because it allows retention of compressive stress (full or partial) such that the stress is memorized in parts of pFET 106 during the subsequent anneal step, described below.
The forming step may be provided in any number of fashions, only two illustrative embodiments of which will be described herein. FIGS. 3-6 show the two illustrative embodiments. A first optional preliminary step includes, as shown in FIG. 3, forming an etch stop layer 118, e.g., of silicon dioxide (SiO2), (shown in phantom in FIG. 3 only). Next, a first sub-step, shown in FIG. 3, includes forming a first stress layer 130 over semiconductor device 100. As will be described below, first stress layer 130 may be either tensile stress layer 120 (FIG. 2) or compressive stress layer 122 (FIG. 2). As shown in FIG. 3, however, first stress layer 130 includes an intrinsically tensilely stressed silicon nitride. A second sub-step, also shown in FIG. 3, includes forming an etch stop layer 132 over first stress layer 130. Etch stop layer 132 may include any now known or later developed etch stop material such as silicon dioxide (SiO2). Next, as also shown in FIG. 3, first stress layer 130 and etch stop layer 132 are removed over a first one of nFET 104 and pFET 106 (pFET 106 as shown) to expose one of the FETs. The etching 138 may include use of a patterned mask 136 (shown in phantom) and any conventional dry etching chemistry for the materials used. FIG. 4 shows the resulting structure including exposed pFET 106.
Next, as shown in FIG. 5, a second stress layer 140 is formed over semiconductor device 100. As shown, second stress layer 140 is formed over pFET 106 and, hence, includes the above-described high density, compressive stress silicon nitride. In one alternative embodiment, a next step may include removing second stress layer 140 over nFET 104 prior to the annealing step, described below. The removing step may include use of a patterned mask 146 (shown in phantom) and any conventional dry etching 144 for the materials used. FIG. 6 shows the resulting structure. Where second stress layer 140 is not removed, it should be recognized that some degradation of stress imparted by first stress layer 130 may be present, but that this degradation is minimal.
In an alternative embodiment, the above-described steps may be switched. That is, the forming step may include forming a compressive stress layer 122 over semiconductor device 100, forming an etch stop layer 132 over the compressive stress layer, removing compressive stress layer 122 and etch stop layer 132 over nFET 104, and forming a tensile stress layer 120 over semiconductor device 100. As in the above-described embodiment, tensile stress layer 120 may be optionally removed over pFET 106 prior to the annealing step, described below. Where tensile stress layer 120 is not removed, it should be recognized that some degradation of stress imparted by compressive stress layer 122 may be present, but that this degradation is minimal.
FIG. 6 also shows a second step according to one embodiment of the method, which includes annealing 150 to memorize stress in semiconductor device 100. Annealing 150 preferably includes using a temperature of no less than approximately 400° C. and no greater than approximately 1200° C. The anneal temperature is optimized so that device 100 will be able to memorize the stress from stress layers 120, 122, and not lose the compressive stress on parts of pFET 106, which would result in a neutral or tensile stress thereon. For example, one conventional plasma-enhanced chemical vapor deposited (PECVD) compressive silicon nitride, which is formed with approximately −1.8 GPa of stress drops to approximately 0.04 GPa, i.e., a tensile stress, after anneal. In contrast, one embodiment an HDP compressive stress silicon nitride according to the invention is formed with approximately −3.0 GPa, which results in a stress of no less than −100 MPa, thus retaining a compressive stress. In one embodiment, the compressive stress may be in the range of approximately −1 GPa.
FIG. 7 shows a third step including removing stress layers 120, 122 and etch stop layer 132. This removing step 148 may include a wet or dry etch, or combination of them; for example, a wet or dry etch to remove etch stop layer 132 and then a wet strip using hot phosphorous acid to remove silicon nitride stress layers. FIG. 7 also shows a semiconductor device 200 according to the invention including an nFET 204 having a tensile stress 260 memorized into a part thereof, e.g., gate conductor 214 and/or diffusion region 216, and a pFET 206 having a compressive stress 262 memorized into a part thereof, e.g., gate conductor 220 and/or diffusion region 222.
The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3602841||Jun 18, 1970||Aug 31, 1971||Ibm||High frequency bulk semiconductor amplifiers and oscillators|
|US4665415||Apr 24, 1985||May 12, 1987||International Business Machines Corporation||Field-effect transistor|
|US4853076||Jul 9, 1987||Aug 1, 1989||Massachusetts Institute Of Technology||Heat treatment while crystallizing to produce tensile stress which produces electron mobility|
|US4855245||Oct 4, 1988||Aug 8, 1989||Siemens Aktiengesellschaft||Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate|
|US4952524||May 5, 1989||Aug 28, 1990||At&T Bell Laboratories||Diffusion barrier layer; thermal stress-relieving layer|
|US4958213||Jun 12, 1989||Sep 18, 1990||Texas Instruments Incorporated||Method for forming a transistor base region under thick oxide|
|US5006913||Nov 2, 1989||Apr 9, 1991||Mitsubishi Denki Kabushiki Kaisha||Stacked type semiconductor device|
|US5060030||Jul 18, 1990||Oct 22, 1991||Raytheon Company||Pseudomorphic HEMT having strained compensation layer|
|US5081513||Feb 28, 1991||Jan 14, 1992||Xerox Corporation||Electronic device with recovery layer proximate to active layer|
|US5108843||Nov 27, 1989||Apr 28, 1992||Ricoh Company, Ltd.||Thin film semiconductor and process for producing the same|
|US5134085||Nov 21, 1991||Jul 28, 1992||Micron Technology, Inc.||Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories|
|US5310446||Jul 13, 1992||May 10, 1994||Ricoh Company, Ltd.||Single crystal semiconductor films superimposed to form multilayer element, applying energy to melt and cooling|
|US5354695||Apr 8, 1992||Oct 11, 1994||Leedy Glenn J||Membrane dielectric isolation IC fabrication|
|US5371399||Aug 9, 1993||Dec 6, 1994||International Business Machines Corporation||Compound semiconductor having metallic inclusions and devices fabricated therefrom|
|US5391510||Apr 7, 1994||Feb 21, 1995||International Business Machines Corporation||A diamond-like-carbon layer is used as masking structure to protect gate dielectric layer from contamination during high temperature annealing, removal by plasma etching, forming metal gate electrode in space vacated by masking layer|
|US5459346||Nov 17, 1994||Oct 17, 1995||Ricoh Co., Ltd.||Semiconductor substrate with electrical contact in groove|
|US5471948||May 11, 1994||Dec 5, 1995||International Business Machines Corporation||Method of making a compound semiconductor having metallic inclusions|
|US5557122||May 12, 1995||Sep 17, 1996||Alliance Semiconductors Corporation||Semiconductor electrode having improved grain structure and oxide growth properties|
|US5561302||Sep 26, 1994||Oct 1, 1996||Motorola, Inc.||Enhanced mobility MOSFET device and method|
|US5565697||Jun 2, 1995||Oct 15, 1996||Ricoh Company, Ltd.||Semiconductor structure having island forming grooves|
|US5571741||Jun 7, 1995||Nov 5, 1996||Leedy; Glenn J.||Membrane dielectric isolation IC fabrication|
|US5592007||Jun 7, 1995||Jan 7, 1997||Leedy; Glenn J.||Membrane dielectric isolation transistor fabrication|
|US5592018||Jun 7, 1995||Jan 7, 1997||Leedy; Glenn J.||Membrane dielectric isolation IC fabrication|
|US5670798||Mar 29, 1995||Sep 23, 1997||North Carolina State University||Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same|
|US5679965||Nov 9, 1995||Oct 21, 1997||North Carolina State University||Continuously graded layers of aluminum gallium nitride to reduce or eliminate conduction band or valence band offsets|
|US5683934||May 3, 1996||Nov 4, 1997||Motorola, Inc.||Enhanced mobility MOSFET device and method|
|US5840593||Mar 10, 1997||Nov 24, 1998||Elm Technology Corporation||Membrane dielectric isolation IC fabrication|
|US5861651||Feb 28, 1997||Jan 19, 1999||Lucent Technologies Inc.||Second layer of doped polycrystalline silicon separated by nitrogen doped silicon oxide|
|US5880040||Apr 15, 1996||Mar 9, 1999||Macronix International Co., Ltd.||Gate dielectric based on oxynitride grown in N2 O and annealed in NO|
|US5940716||Mar 14, 1997||Aug 17, 1999||Samsung Electronics Co., Ltd.||Methods of forming trench isolation regions using repatterned trench masks|
|US5940736||Mar 11, 1997||Aug 17, 1999||Lucent Technologies Inc.||Method for forming a high quality ultrathin gate oxide layer|
|US5946559||Jun 7, 1995||Aug 31, 1999||Elm Technology Corporation||Method of forming a field effect transistor|
|US5960297||Jul 2, 1997||Sep 28, 1999||Kabushiki Kaisha Toshiba||Shallow trench isolation structure and method of forming the same|
|US5989978||Jul 16, 1998||Nov 23, 1999||Chartered Semiconductor Manufacturing, Ltd.||Shallow trench isolation of MOSFETS with reduced corner parasitic currents|
|US6008126||Feb 23, 1998||Dec 28, 1999||Elm Technology Corporation||Membrane dielectric isolation IC fabrication|
|US6025280||Apr 28, 1997||Feb 15, 2000||Lucent Technologies Inc.||Use of SiD4 for deposition of ultra thin and controllable oxides|
|US6046464||Aug 13, 1997||Apr 4, 2000||North Carolina State University||Integrated heterostructures of group III-V nitride semiconductor materials including epitaxial ohmic contact comprising multiple quantum well|
|US6066545||Dec 7, 1998||May 23, 2000||Texas Instruments Incorporated||Birdsbeak encroachment using combination of wet and dry etch for isolation nitride|
|US6090684||Jul 29, 1999||Jul 18, 2000||Hitachi, Ltd.||Method for manufacturing semiconductor device|
|US6107143||Sep 10, 1998||Aug 22, 2000||Samsung Electronics Co., Ltd.||Method for forming a trench isolation structure in an integrated circuit|
|US6117722||Feb 18, 1999||Sep 12, 2000||Taiwan Semiconductor Manufacturing Company||SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof|
|US6133071||Oct 15, 1998||Oct 17, 2000||Nec Corporation||Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package|
|US6165383||Oct 15, 1998||Dec 26, 2000||Organic Display Technology||Anthracene derivatives having at least one reactive silyl group that is effective to form siloxane bonds|
|US6221735||Feb 15, 2000||Apr 24, 2001||Philips Semiconductors, Inc.||Method for eliminating stress induced dislocations in CMOS devices|
|US6228694||Jun 28, 1999||May 8, 2001||Intel Corporation||Method of increasing the mobility of MOS transistors by use of localized stress regions|
|US6246095||Sep 3, 1998||Jun 12, 2001||Agere Systems Guardian Corp.||System and method for forming a uniform thin gate oxide layer|
|US6255169||Feb 22, 1999||Jul 3, 2001||Advanced Micro Devices, Inc.||Process for fabricating a high-endurance non-volatile memory device|
|US6261964||Dec 4, 1998||Jul 17, 2001||Micron Technology, Inc.||Material removal method for forming a structure|
|US6265317||Jan 9, 2001||Jul 24, 2001||Taiwan Semiconductor Manufacturing Company||Top corner rounding for shallow trench isolation|
|US6274444||Aug 10, 1999||Aug 14, 2001||United Microelectronics Corp.||Method for forming mosfet|
|US6281532||Jun 28, 1999||Aug 28, 2001||Intel Corporation||Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering|
|US6284623||Oct 25, 1999||Sep 4, 2001||Peng-Fei Zhang||Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect|
|US6284626||Apr 6, 1999||Sep 4, 2001||Vantis Corporation||Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench|
|US6319794||Oct 14, 1998||Nov 20, 2001||International Business Machines Corporation||Structure and method for producing low leakage isolation devices|
|US6361885||Nov 19, 1998||Mar 26, 2002||Organic Display Technology||Anodes and cathodes for electroluminescent device|
|US6362082||Jun 28, 1999||Mar 26, 2002||Intel Corporation||Methodology for control of short channel effects in MOS transistors|
|US6368931||Mar 27, 2000||Apr 9, 2002||Intel Corporation||Thin tensile layers in shallow trench isolation and method of making same|
|US6372291 *||Dec 23, 1999||Apr 16, 2002||Applied Materials, Inc.||In situ deposition and integration of silicon nitride in a high density plasma reactor|
|US6403486||Apr 30, 2001||Jun 11, 2002||Taiwan Semiconductor Manufacturing Company||Method for forming a shallow trench isolation|
|US6403975||Apr 8, 1997||Jun 11, 2002||Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev||Components have faborable optical and electrical properties and are suitable for integration on a si substrate.|
|US6406973||Jun 29, 2000||Jun 18, 2002||Hyundai Electronics Industries Co., Ltd.||Forming separation layer|
|US6461936||Jan 4, 2002||Oct 8, 2002||Infineon Technologies Ag||Double pullback method of filling an isolation trench|
|US6476462||Dec 7, 2000||Nov 5, 2002||Texas Instruments Incorporated||MOS-type semiconductor device and method for making same|
|US6483171||Aug 13, 1999||Nov 19, 2002||Micron Technology, Inc.||Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same|
|US6493497||Sep 26, 2000||Dec 10, 2002||Motorola, Inc.||Electro-optic structure and process for fabricating same|
|US6498358||Jul 20, 2001||Dec 24, 2002||Motorola, Inc.||Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating|
|US6501121||Nov 15, 2000||Dec 31, 2002||Motorola, Inc.||Semiconductor structure|
|US6506652||Dec 9, 1999||Jan 14, 2003||Intel Corporation||Method of recessing spacers to improved salicide resistance on polysilicon gates|
|US6509618||Jan 4, 2000||Jan 21, 2003||Intel Corporation||Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates|
|US6521964||Aug 30, 1999||Feb 18, 2003||Intel Corporation||Device having spacers for improved salicide resistance on polysilicon gates|
|US6531369||Feb 14, 2002||Mar 11, 2003||Applied Micro Circuits Corporation||Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)|
|US6531740||Jul 17, 2001||Mar 11, 2003||Motorola, Inc.||Integrated impedance matching and stability network|
|US6621392||Apr 25, 2002||Sep 16, 2003||International Business Machines Corporation||Micro electromechanical switch having self-aligned spacers|
|US6635506||Nov 7, 2001||Oct 21, 2003||International Business Machines Corporation||Method of fabricating micro-electromechanical switches on CMOS compatible substrates|
|US6717216||Dec 12, 2002||Apr 6, 2004||International Business Machines Corporation||SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device|
|US6831292||Sep 20, 2002||Dec 14, 2004||Amberwave Systems Corporation||Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same|
|US6881665 *||Aug 9, 2000||Apr 19, 2005||Advanced Micro Devices, Inc.||Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist|
|US20010009784||Feb 14, 2001||Jul 26, 2001||Yanjun Ma||Preparing substrate, isolating active region, depositing gate oxide, depositing first and second selective etchable layers over gate oxide layer, etching to undercut first etchable layer, implanting ions, etching, depositing oxide, metallizing|
|US20020063292||Nov 29, 2000||May 30, 2002||Mark Armstrong||CMOS fabrication process utilizing special transistor orientation|
|US20020074598||Nov 9, 2001||Jun 20, 2002||Doyle Brian S.||Methodology for control of short channel effects in MOS transistors|
|US20020086472||Dec 29, 2000||Jul 4, 2002||Brian Roberds||Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel|
|US20020086497||Dec 6, 2001||Jul 4, 2002||Kwok Siang Ping||Beaker shape trench with nitride pull-back for STI|
|US20020090791||Jun 28, 1999||Jul 11, 2002||Brian S. Doyle||Method for reduced capacitance interconnect system using gaseous implants into the ild|
|US20030032261||Aug 8, 2001||Feb 13, 2003||Ling-Yen Yeh||Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation|
|US20030040158||Aug 21, 2002||Feb 27, 2003||Nec Corporation||Semiconductor device and method of fabricating the same|
|US20030057184||Sep 22, 2001||Mar 27, 2003||Shiuh-Sheng Yu||Method for pull back SiN to increase rounding effect in a shallow trench isolation process|
|US20030067035||Sep 28, 2001||Apr 10, 2003||Helmut Tews||Gate processing method with reduced gate oxide corner and edge thinning|
|US20040029323 *||Jun 29, 2001||Feb 12, 2004||Akihiro Shimizu||Semiconductor device and method for fabricating the same|
|US20040113174 *||Dec 12, 2002||Jun 17, 2004||International Business Machines Corporation||Isolation structures for imposing stress patterns|
|US20050093059 *||Oct 30, 2003||May 5, 2005||Belyansky Michael P.||Structure and method to improve channel mobility by gate electrode stress modification|
|US20050093081 *||Nov 4, 2003||May 5, 2005||Internatioanal Business Machines Corporation||Oxidation method for altering a film structure and cmos transistor structure formed therewith|
|US20050156208 *||Sep 30, 2004||Jul 21, 2005||Taiwan Semiconductor Manufacturing Company, Ltd.||Device having multiple silicide types and a method for its fabrication|
|US20050194596||Apr 21, 2005||Sep 8, 2005||Victor Chan||Increasing carrier mobility in NFET and PFET transistors on a common wafer|
|US20050199958 *||Mar 10, 2004||Sep 15, 2005||Taiwan Semiconductor Manufacturing Co., Ltd.||Method for selectively stressing MOSFETs to improve charge carrier mobility|
|US20060091471 *||Jun 10, 2005||May 4, 2006||Kai Frohberg||Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress|
|US20060148270 *||Jan 5, 2005||Jul 6, 2006||Wei Lu||High density plasma and bias RF power process to make stable FSG with less free F and SiN with less H to enhance the FSG/SiN integration reliability|
|US20060228848 *||Mar 31, 2005||Oct 12, 2006||International Business Machines Corporation||Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals|
|US20070010073 *||Jul 6, 2005||Jan 11, 2007||Chien-Hao Chen||Method of forming a MOS device having a strained channel region|
|US20070018252 *||Jul 21, 2005||Jan 25, 2007||International Business Machines Corporation||Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same|
|US20070040225 *||Aug 22, 2005||Feb 22, 2007||Yang Haining S||High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same|
|US20070075360 *||Sep 30, 2005||Apr 5, 2007||Alpha &Omega Semiconductor, Ltd.||Cobalt silicon contact barrier metal process for high density semiconductor power devices|
|US20070105299||Nov 10, 2005||May 10, 2007||International Business Machines Corporation||Dual stress memory technique method and related structure|
|JPS6476755A|| ||Title not available|
|SG132585A1|| ||Title not available|
|SG151256A1|| ||Title not available|
|1||A. Shimizu, et al., "Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement." International Electron Devices Meeting, IEEE, Mar. 2001.|
|2||B. Doyle, et al., "Recovery of Hot-Carrier Damage in Reoxidized Nitrided Oxide MOSFETs." IEEE Electron Device Letters, vol. 13, No. 1, Jan. 1992, pp. 38-40.|
|3||C.J. Huang, et al., "Temperature Dependence and Post-Stress Recovery of Hot Electron Degradation Effects in Bipolar Transistors." IEEE 1991 Bipolar Circuits and Technology Meeting 7.5, pp. 170-173.|
|4||Chen et al., "Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application," Symposium on VLSI Technology Digest of Technical Papers, pp. 56-57, 2004.|
|5||D.C. Houghton, et al., "Equilibrium Critical Thickness for SI 1-x GEx Strained Layers on (100) Si". Appl. Phys. Lett. 56 (5) , Jan. 29, 1990, pp. 460-462.|
|6||F. Ootsuka, et al., "A Highly Dense, High-Performance 130nm Node CMOS Technology for Large Scale System-on-a-Chip Application." International Electron Devices Meeting, 23.5.1, IEEE, Apr. 2000.|
|7||G. Zhang, et al., "A New 'Mixed-Mode' Reliability Degradation Mechanism in Advanced Si and SiGe Bipolar Transistors." IEEE Transactions on Electron Devices, vol. 49, No. 12, Dec. 2002, pp. 2151-2156.|
|8||G. Zhang, et al., "A New ‘Mixed-Mode’ Reliability Degradation Mechanism in Advanced Si and SiGe Bipolar Transistors." IEEE Transactions on Electron Devices, vol. 49, No. 12, Dec. 2002, pp. 2151-2156.|
|9||Gregory Scott, et al., "NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress." International Electron Devices Meeting, 34.4.1, IEEE, Sep. 1999.|
|10||H. Li, et al., "Design of W-Band VCOs with High Output Power for Potential Application in 77 GHz Automotive Radar Systems." 2003 IEEE GaAs Digest, pp. 263-266.|
|11||H. Wurzer, et al., "Annealing of Degraded mpn-Transistors- Mechanisms and Modeling." IEEE Transactions on Electron Devices, vol. 41, No. 4, Apr. 1994, pp. 533-538.|
|12||H.S. Momose, et al., "Analysis of the Temperature Dependence of Hot-Carrier-Induced Degradation in Bipolar Transistors for Bi-CMOS." IEEE Transactions on Electron Devices, vol. 41, No. 6, Jun. 1994, pp. 978-987.|
|13||H.S. Momose, et al., "Temperature Dewndence of Emitter-Base Reverse Stress Degradation and its Mechanism Analyzed by MOS Structures." Paper 6.2, pp. 140-143.|
|14||IPOS International Search Report with Written Opinion, Jul. 15, 2009, 11 pages.|
|15||J.C. Bean, et al., "GEx SI 1-x/Si Strained-Layer Superlattice Grown by Molecular Beam Epitaxy". J. Vac. Sci. Technol. A 2(2), Apr.-Jun. 1984, pp. 436-440.|
|16||J.H. Van Der Nerve, "Regular Articles". Journal of Applied Physics, vol. 34, No. 1, Jan. 1963, pp. 117-122.|
|17||J.W. Matthews, et al., "Defects in Epitaxial Multilayers". Journal of Crystal Growth 27 (1974), pp. 118-125.|
|18||K. Ota, et al., "Novel Locally Strained Channel Technique for High Performance 55nm CMOS." International Electron Devices Meeting, 2.2.1, IEEE, Feb. 2002.|
|19||Kern Rim, et al., "Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs." 2002 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 98-99.|
|20||Kern Rim, et al., "Transconductance Enhancement in Deep Submicron Strained-Si n-MOSFETs". International Electron Devices Meeting, 26, 8, 1, IEEE, Sep. 1998.|
|21||M. Khater, et al., "SiGe HBT Technology with Fmax/Ft=350/300 GHz and Gate Delay Below 3.3 ps", 2004 IEEE, 4 pages.|
|22||R.H.M. Van De Leur, et al., "Critical Thickness for Pseudomorphic Growth of Si/Ge Alloys and Superlattices". J. Appl. Phys. 64 (6), Sep. 15, 1988, pp. 3043-3050.|
|23||S.R. Sheng, et al., "Degradation and Recovery of SiGe HBTs Following Radiation and Hot-Carrier Stressing." pp. 14-15.|
|24||Shinya Ito, et al., "Mechanical Stress Effect of Etch-Stop Nitride and Its Impact on Deep Submicron Transistor Design." International Electron Devices Meeting, 10.7.1, IEEE, Apr. 2000.|
|25||Subramanian S. Iyer, et al., "Heterojunction Bipolar Transistors Using Si-Ge Alloys". IEEE Transactions on Electron Devices, vol. 36, No. 10, Oct. 1989, pp. 2043-2064.|
|26||Z. Yang, et al., "Avalanche Current Induced Hot Carrier Degradation in 200 GHz SiGe Heterojunction Bipolar Transistors." pp. 1-5.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8482042 *||Jan 22, 2010||Jul 9, 2013||Infineon Technologies Ag||Strained semiconductor device and method of making same|
|US20100015766 *||Jul 21, 2009||Jan 21, 2010||Texas Instruments Incorporated||Complementary stress memorization technique layer method|
|Apr 11, 2014||REMI||Maintenance fee reminder mailed|
|Nov 10, 2005||AS||Assignment|
Owner name: CHARTERED SEMICONDUCTOR MANUFACTURING LTD, SINGAPO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TEH, YOUNG WAY;REEL/FRAME:016764/0808
Effective date: 20051102
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FANG, SUNFEI;LUO, ZHIJIONG;NG, HUNG Y.;AND OTHERS;REEL/FRAME:016764/0515;SIGNING DATES FROM 20051028 TO 20051108
Owner name: SAMSUNG ELECTRONICS CO., LTD, KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KIM, JUN JUNG;REEL/FRAME:016764/0583
Effective date: 20051027
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FANG, SUNFEI;LUO, ZHIJIONG;NG, HUNG Y.;AND OTHERS;SIGNING DATES FROM 20051028 TO 20051108;REEL/FRAME:016764/0515