|Publication number||US7817390 B2|
|Application number||US 12/461,237|
|Publication date||Oct 19, 2010|
|Filing date||Aug 5, 2009|
|Priority date||Nov 28, 2007|
|Also published as||US7755871, US20090135533, US20090296295|
|Publication number||12461237, 461237, US 7817390 B2, US 7817390B2, US-B2-7817390, US7817390 B2, US7817390B2|
|Inventors||Ming-Dou Ker, Chin-Hao Chen, Ryan Hsin-Chin Jiang|
|Original Assignee||Amazing Microelectronic Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (1), Classifications (4), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a Divisional of U.S. application Ser. No. 11/987,222 filed Nov. 28, 2007 now U.S. Pat. No. 7,755,871. This application claims priority to U.S. application Ser. No. 11/987,222 filed Nov. 28, 2007, which is incorporated by reference.
1. Field of the Invention
The present invention relates to a power-rail electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to a power-rail ESD protection circuit with ultra-low gate leakage.
2. Description of the Prior Art
In CMOS technology, the device dimension of transistor has been scaled toward the nanometer region. As MOS transistors get smaller and the gate oxide gets thinner, tunneling current through the isolation barrier becomes a non-negligible component with a potential impact on circuit operation and performance. More specifically, the high gate current will render traditional power-rail ESD clamps circuit mal-functional, necessitating modification to existing circuits to minimize sensitivity to the MOS capacitor gate tunneling leakage.
A power-rail ESD clamp circuit provides a low-impedance path from VDD to VSS for ESD current.
In the circuits shown in
For advanced technologies with very thin gate oxide. The thinner gate oxide MOS capacitor gets the smaller capacitor area. The thin gate oxide MOS capacitor in the detecting circuit 14 is associated with significant stand-by power consumption because of the large gate tunneling leakage current. Further, the large gate leakage current of the classic RC-triggered power-rail clamp circuit and CR-coupled power-rail clamp circuit may cause the clamping device 12 mistriggered. Due to these problems, modified power clamps with a ultra-low gate leakage are highly desirable. The requirement for an improved power-rail ESD clamp circuit is not just reduction of the capacitor size, but reduction of the gate leakage current at the same time to avoid mistriggering the clamping device 12.
The main scope of the invention is to provide ESD protection circuits for solving the aforementioned problems. According to the invention, the connecting configuration of this gate oxide MOS capacitor is variable under different operation conditions.
An embodiment according to the invention is an ESD protection circuit including a clamping module and a detecting module. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a thin gate oxide MOS capacitor. The triggering unit has an input terminal, an output terminal, and a switching terminal. The output terminal is coupled to and used for triggering the clamping module. The resistor is coupled between the negative power line and the input terminal of the triggering unit. The thin gate oxide MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit; the second end is switched to the positive power and negative power by switch terminal of trigger unit to solve the thin gate oxide leakage problem.
During a normal power operation, the switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the negative power line. In an ESD event, the switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, during normal power operations, the gate tunneling leakage is eliminated. Moreover, the problem of mistriggering can be prevented.
The advantage and spirit of the invention may be understood by the following recitations together with the appended drawings.
Please refer to
The triggering unit 84A has an input terminal (I), an output terminal (O), and a switching terminal (S). The output terminal (O) is coupled to and used for triggering the clamping module 82. The resistor, which can be replaced as a MOS resistor, is coupled between negative power line (VSS) and the input terminal (I). A first end of the capacitor is also coupled to the input terminal (I), and a second end of the capacitor is selectively coupled positive power line (VDD) or negative power line (VSS).
In this embodiment, the thin gate oxide MOS capacitor is a PMOS with its gate terminal as the first end; the source, drain and bulk terminals of the PMOS are coupled together as the second end. In other applications, the PMOS can be replaced by an NMOS. In practice, the first end and the second end can be swap.
According to the invention, in an ESD event, the switching terminal (S) enables the second end of the capacitor to be coupled with VDD. Thereby, the capacitor and the resistor are connected in series between VDD/VSS and function as the CR combination in
On the contrary, during normal power operations, the switching terminal (S) enables the second end of the capacitor to be coupled with VSS. In this configuration, both ends of the capacitor are substantially coupled to VSS. Hence, there is nearly no gate tunneling leakage through the capacitor. Further, since the voltage at the input terminal (I) will not be affected by gate tunneling leakage, and the problem of mistriggering is accordingly prevented.
Moreover, it can be seen the two MOSs functioning as switches in
According to the invention, the thin gate oxide MOS capacitor in the ESD detecting unit is coupled to different power lines during normal power operation and in an ESD event. Because the two ends of the capacitor are substantially coupled to the same power line, the problems of gate tunneling leakage and mistriggering can be effectively prevented.
With the example and explanations above, the features and spirits of the invention will be hopefully well described. Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teaching of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4797899 *||Dec 15, 1986||Jan 10, 1989||Maxim Integrated Products, Inc.||Integrated dual charge pump power supply including power down feature and rs-232 transmitter/receiver|
|US5946177||Aug 17, 1998||Aug 31, 1999||Motorola, Inc.||Circuit for electrostatic discharge protection|
|US6385021||Apr 10, 2000||May 7, 2002||Motorola, Inc.||Electrostatic discharge (ESD) protection circuit|
|US6724603||Aug 9, 2002||Apr 20, 2004||Motorola, Inc.||Electrostatic discharge protection circuitry and method of operation|
|US6989979||Sep 22, 2003||Jan 24, 2006||Pericom Semiconductor Corp.||Active ESD shunt with transistor feedback to reduce latch-up susceptibility|
|US20040109270 *||Dec 10, 2002||Jun 10, 2004||Michael Stockinger||Transient detection circuit|
|US20060050451 *||Dec 2, 2004||Mar 9, 2006||Tseng Jen-Chou||Electrostatic discharge protection circuit|
|US20090273955 *||May 1, 2008||Nov 5, 2009||Tseng Tang-Kuei||Optimum structure for charge pump circuit with bipolar output|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US9413169||Apr 2, 2014||Aug 9, 2016||Globalfoundries Inc.||Electrostatic discharge protection circuit with a fail-safe mechanism|
|Aug 5, 2009||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KER, MING-DOU;CHEN, CHIN-HAO;JIANG, RYAN HSIN-CHIN;SIGNING DATES FROM 20071113 TO 20071123;REEL/FRAME:023086/0204
Owner name: AMAZING MICROELECTRONIC CORP., TAIWAN
|Apr 21, 2014||FPAY||Fee payment|
Year of fee payment: 4