|Publication number||US7820480 B2|
|Application number||US 11/986,620|
|Publication date||Oct 26, 2010|
|Filing date||Nov 21, 2007|
|Priority date||Jun 25, 2003|
|Also published as||CN1836319A, CN100463125C, EP1652227A2, US7795710, US20060151860, US20080076206, WO2005004200A2, WO2005004200A3|
|Publication number||11986620, 986620, US 7820480 B2, US 7820480B2, US-B2-7820480, US7820480 B2, US7820480B2|
|Inventors||Shafidul Islam, Romarico Santos San Antonio, Anang Subagio|
|Original Assignee||Unisem (Mauritius) Holdings Limited|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Referenced by (8), Classifications (38), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This patent application is a divisional application of U.S. patent application Ser. No. 10/561,381 entitled “Lead Frame Routed Chip Pads for Semiconductor Packages” filed on Dec. 16, 2005, which corresponds with PCT application US2004/019523, filed Jun. 18, 2004 and claims priority to, U.S. Provisional Patent Application Ser. No. 60/482,527, filed Jun. 25, 2003 the entirety of all applications is incorporated herein by reference.
1. Field of the Invention
This invention relates to a lead frame for a molded plastic package of the type that encapsulates one or more semiconductor devices. More particularly, the lead frame is formed by a sequential metal removal process that selectively patterns external lead ends, routing circuits and internal lead ends from a single electrically conductive substrate.
2. Description of the Related Art
One type of package used to encase semiconductor devices is a molded plastic package. The semiconductor device is encased in a block of polymer resin that provides environmental protection. Electrical signals are transmitted between the semiconductor device and external circuitry, such as a printed circuit board (“PCB”), by a number of different electrically conductive structures. In a leaded package, an electrically conductive lead frame has inner lead ends and opposing outer lead ends. The lead frame configuration is typically formed by chemical etching. The pitch of the inner lead ends is limited by etching considerations to about the thickness of the lead frame. As a result, the leads terminate a distance from the semiconductor device and are electrically interconnected to input/output pads on the semiconductor device by small diameter wires. The leads extend outward from the inner lead ends to terminate at outer lead ends that are soldered to contact pads on external circuitry. The footprint (surface area on a printed circuit board or other external structure) occupied by this type of leaded package is significantly greater than the footprint of the semiconductor device.
There is a desire in the semiconductor packaging industry to minimize the footprint of semiconductor packages with a goal to obtain chip-scale packages where the footprint of the package is not greater than the footprint of the semiconductor device. In a leaded package, there is always a sizable difference between the bond-pad pitch at the inner leads and the land-pitch external to the package which is utilized for circuit board attach. The bond-pad pitch trends to achieve finer geometries to maximize the use of silicon real estate, while the circuit board level pitch remains more widely spaced for PCB routing and soldering. The fan-out of the lead frame from chip bond-pad pitch to external land pitch causes the package to occupy a much larger footprint than the semiconductor device. This is contrary to the concept and demand for Chip-Scale-Packaging (“CSP”).
The trend towards CSP has driven the evolution of “array” packages with external lands arranged in a grid array at a suitable circuit board-attach pitch. This gird array is constrained within the footprint of the chip. However, this package requires the semiconductor device bond-pads to be routed to desired land positions by use of an interface, often called an interposer. As disclosed in U.S. Pat. No. 6,477,034, the interposer is a multi-layer, usually a thin 2-layer or 3-layer, flexible or similar substrate that enables the pitch fan-out and routing. U.S. Pat. No. 6,477,034 is incorporated by reference in its entirety herein. Interposers are not preferred. In addition to a major cost addition, extra processing steps are required during package assembly.
Ball grid array (“BGA”) packages use printed circuit board substrates for circuit routing and for supporting land repositioning within application limitations, that is to compromise technology limitations in routing features/capabilities against board-attach soldering limits. To enable dense packaging and positioning of the lands, many BGA substrates utilize multi-layer configuration with vias. However, use of such BGA substrates and the addition of vias significantly increase the cost and the processing steps.
A method to manufacture a lead frame for a Quad Flat No-lead (“QFN”) package is disclosed in U.S. Pat. No. 6,498,099 to McLellan et al. that is incorporated by reference in its entirety herein. A first side of an electrically conductive substrate is partially etched to define a pad attach and inner lead ends. A semiconductor device is bonded to the partially defined pad attach and electrically interconnected to partially defined inner lead ends by wire bonds or the like. The semiconductor device, partially defined pad attach, partially defined inner leads and wire bonds are then encapsulated in a polymer molding resin. The opposing second side of the electrically conductive substrate is then etched to electrically isolate the pad attach and inner lead ends and to define outer lead ends.
Another method for the manufacture of a QFN package is disclosed in commonly owned U.S. patent application Ser. No. 10/134,882 that was filed on Apr. 29, 2002 and is incorporated by reference in its entirety herein. Ser. No. 10/134,882 was published on Oct. 30, 2003 as United States Patent Application Publication US 2003/0203539 A1.
There remains, however, a need for a method for the manufacture of chip-scale and other semiconductor packages with accurately positioned inner and outer lead ends and routing circuits that do not require complex manufacturing steps or the inclusion of supplemental interposer circuits. Further there remains a need for the packages manufactured by this method.
In accordance with a first embodiment of the invention, there is provided a package for encasing at least one semiconductor device. The package includes a lead frame having opposing first and second ends. The first ends terminate in an array of lands adapted to be bonded to external circuitry and the second ends terminate at an array of chip attach sites. These chip attach sites are directly electrically interconnected to input/output pads on the at least one semiconductor device. Routing circuits electrically interconnect the array of lands and the array of chip attach sites. A first molding compound is disposed between individual lands of the array of lands and a second molding compound encapsulates the at least one semiconductor device, the array of chip attach sites and the routing circuits.
It is a feature of this embodiment that chip-scale packages and packages to encase multiple devices are readily provided. A further feature is that the lead frame is formed from a monolithic electrically conductive structure and supported by the first molding compound. This causes the lead frame to be robust and have few problems with a loss of coplanarity.
In accordance with a second embodiment of the invention, there is provided a process for the manufacture of a package to encase at least one semiconductor device. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites and routing circuits electrically interconnecting the array of lands and the array of chip attach sites, (d) directly electrically interconnecting input/output pads on the at least one semiconductor devices to chip attach site members of the array of chip attach sites, and (e) encapsulating the at least one semiconductor device, the array of chip attach sites and the routing circuits with a second molding compound.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference numbers and designations in the various drawings indicated like elements.
With reference to
As shown in
A first molding compound is then disposed within the channels 16. As shown in
Preferably, the first molding resin 18 is electrically non-conductive and preferably a polymer molding resin, such as an epoxy, having a flow temperature in the range of 250° C. to 300° C. Alternatively, the first molding resin may be a low temperature thermal glass composite such as those used to attach a lead frame to a ceramic base in a CERDIP, CERPAK or CERDIP package.
This assembly, a lead frame precursor 20 as illustrated in
As shown in
As illustrated in
A semiconductor device 28 is directly electrically interconnected to the chip attach sites 24 as shown in
With reference to
The combination of chip attach sites 24, chip attach pillars 34, routing circuits 26 and lands 14 is referred to as a “Re-Distributed Lead Frame” or RDLF. The RDLF is formed from a single electrically conductive substrate as a monolithic structure. In the package embodiment shown in
One or more embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.
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|U.S. Classification||438/107, 257/673, 257/675, 438/124, 438/108, 438/123, 257/672, 257/669, 257/676, 257/671, 257/674, 257/670, 257/666, 257/692, 438/121, 257/667, 257/668|
|International Classification||H01L23/498, H01L23/31, H01L, H01L21/00|
|Cooperative Classification||H01L2924/01019, H01L24/48, H01L24/49, H01L23/49838, H01L2924/19041, H01L23/3121, H01L2224/49171, H01L2924/01079, H01L2224/48227, H01L23/49861, H01L23/3114, H01L2224/16, H01L2924/10253|
|European Classification||H01L23/31H1, H01L23/498G, H01L23/31H2, H01L23/498L|
|Jan 4, 2011||CC||Certificate of correction|
|Apr 28, 2014||FPAY||Fee payment|
Year of fee payment: 4