|Publication number||US7824981 B2|
|Application number||US 11/980,154|
|Publication date||Nov 2, 2010|
|Filing date||Oct 30, 2007|
|Priority date||Jun 6, 2003|
|Also published as||US7297634, US20050201150, US20080070390|
|Publication number||11980154, 980154, US 7824981 B2, US 7824981B2, US-B2-7824981, US7824981 B2, US7824981B2|
|Original Assignee||Chih-Hsin Wang|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (100), Non-Patent Citations (48), Referenced by (2), Classifications (38), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a Continuation of U.S. patent application Ser. No. 11/055,427, filed Feb. 9, 2005, which application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/585,238 filed Jul. 1, 2004 and U.S. Provisional Patent Application Ser. No. 60/626,326 filed Nov. 8, 2004. This application is a Continuation-In-Part of U.S. patent application Ser. No. 11/007,907, filed on Dec. 8, 2004, now U.S. Pat. No. 7,115,942. This application is also a Continuation-In-Part of U.S. patent application Ser. No. 10/457,249, filed on Jun. 6, 2003, now U.S. Pat. No. 6,958,513.
The present invention relates to semiconductor device and semiconductor memory device. More particularly, the present invention relates to methods and apparatus on transporting charges in these devices using piezo-ballistic-charges injection mechanism. Charge states of memory devices can be altered by injecting piezo-ballistic holes or by injecting piezo-ballistic electrons on charge storage regions of memory cells for erase and for program operations, respectively.
Ballistic transport of charge carriers is a well-known phenomenon in solid state physics. It represents charge carriers transporting in an active layer of conductive material (e.g. a semiconductor crystal) without scattering at all (i.e. transporting in a “ballistic” way). The active layer has to be kept thin enough to permit carrier transmission with substantially no scattering. Under these conditions, the transport of carriers resembles that in vacuum, but with the effective mass and group velocity of the carriers in the conductive material. One application of such physics has been proposed in a three terminals device (or “transistor”) in an article by Mead (see Mead, “The Tunnel Emission Amplifier,” Proceedings of the IRE, vol. 48, pp. 359-361, 1960), which is hereby incorporated by reference. U.S. application Ser. No. 09/942,338, which is hereby incorporated by reference, disclosed operation method on non-volatile memory cells based on the charge injection mechanism and energy band structure illustrated in the noted article. However, there are several fundamental problems associated with the charge injection mechanism and energy band structure in the noted article. Further, there are fundamental problems when such mechanism and band structure are employed for non-volatile memory operation. Moreover, there are several problems in the prior art memory cell need to be considered.
The present invention can best be understood with an understanding on how ballistic charge injection mechanism works, how prior art energy band structure is constructed, and how the devices are operated.
The ballistic hot electron injection for programming prior art memory cell is done similarly to the ballistic hot hole injection except by reversing the bias polarity. Referring to
Problems on Charge Injection Mechanism of Prior Art
It is known that there are various types of holes, namely the light-hole (LH) and the heavy-hole (HH), in semiconductors (e.g. Si, Ge, GaAs etc.). The light-hole has a lighter effective mass than the heavy-hole, and difference between them depends on the band structure of the valence sub-bands of semiconductors. Prior art did not distinguish these two different types of holes while employing ballistic hole injection mechanism for erasing prior art memory cells. Further, the prior art did not teach the effects associated with these two types of holes on the injection mechanism. Thus, the injection scheme employed in prior art is believed to suffer from following problems:
1) Low Injection Efficiency
It is known that the population of holes in a semiconductor is primarily of the heavy-hole (HH). This is to first order due to its larger density-of-state effective mass. For example, in silicon, it is known the HH occupied about 80 percent of the total population of holes (see, for example, Fischetti et al., Journal of Appl. Physics, vol. 94, pp. 1079-1095, 2003). Further, it is known the ballistic carrier transport is characterized by its mean-free-path, where a ballistic carrier having a longer mean-free-path can transport a longer distance without scattering. The mean-free-path is approximately inversely proportional to the mass of the carriers. Therefore, HH typically has a shorter mean-free-path, and are more likely to experience scattering events through interacting with other types of carriers (e.g. phonons). Thus, a ballistic HH is more prone to loose its ballistic nature during its transport in a semiconductor region. When a ballistic HH transports at energy greater than its thermal energy, it is therefore more likely to loose its energy to become a thermal carrier. Even not loosing all its energy, HH can have its energy component in the direction to the floating gate region (or targeted destination) be significantly lowered such that the hole has insufficient energy to surmount the barrier height 34 of the insulator 26. In other words, when ballistic holes are employed for erasing prior art memory cells, since the majority population of the hole carriers are of the HH type, which has a shorter mean-free-path, most of the supplied holes cannot contribute to the erase operation as anticipate. This causes waste on total current. The combined effects of population and effective mass result in the ballistic hole injection efficiency significantly lower than one usually can expect. (Here, the efficiency is defined as number of charges collected compared to total number of charges supplied).
2) Higher Power Consumption and Slower Erase Speed
The aforementioned effects were ignored in prior art memory cells, and hence the cells require more electrical current be supplied, thus consuming more electric power, in order to complete an erase operation. Further, the low hole injection efficiency in prior art cells can result in slow erase problem when implementing the cells in their product applications.
Problems on Parasitic-Electrons Backward Injection
Please refer to
Problems on Parasitic-Holes Backward Injection
Parasitic holes backward injection problem is another major problem for the mechanism employed in prior art. Please refer to
This problem also exists in operating the amplifier by Mead, wherein metal is employed as the material for base, which is equivalent to the ballistic gate 12 in
Problems on Impact Ionization
In addition to the problems described above, the injection mechanism and energy band structure employed in prior art also can suffered from impact ionization problem.
Likewise, impact ionization problem can also happen in ballistic gate 12 and can be triggered by electrons 40 or by energetic electrons 40′ transported from tunneling gate 10. As described above, these electrons 40 and 40′ are inadvertently generated under the bias condition for program operation. The presence of these electrons is not desirable as they carry a much higher energy than that carried by electrons 31. As illustrated in
It is now clear that the impact ionization and the inversion layer formation can exist in the tunneling gate 10 in the energy band structure for the ballistic injection scheme of prior art. All these effects can create parasitic electrons 40 and 40′ in tunneling gate 10. The effects and the parasitic electrons in the tunneling gate region 10 were not taken into account in the prior art. These effects are uncontrollable, where current can unduly increase to result in current loading issue on supporting circuitry for memory operations. The effects further cause reliability problem. To avoid these problems in program operation, the allowable maximum voltage between gates 10 and 12 of prior art cells has to be limited under a threshold voltage to avoid the formation of electrons 40 and/or 40′ in tunneling gate 10. The range between the minimum and the maximum program voltages defines a workable voltage range for program operation of prior art, and is quite narrow for the injection mechanism employed in prior art (less than about 0.6V). The cell structure in prior art thus demands stringent control on the threshold voltage, and is believed having low manufacturability yield and difficulties in practical applications.
Similar to the program operation, for the erase operation (referring to
Problems on Dielectric Breakdown
Please refer to
Problems on Parasitic Capacitance
In the energy band structure and cell structure of prior art, the thickness of the tunneling dielectric layer 28 is chosen with a limitation typically in the range of about 2 nanometer to 4 nanometer (“nm” hereinafter) in order to permit charge carriers tunneling through that layer. Therefore, it results in a large parasitic capacitance C between gates 10 and 12, and is undesirable as it introduces adverse impact on cell operation. The capacitance issue can be better understood by referring to the diagram in
Problems on Large Resistance
In the prior art, ballistic gate 12 is the active layer for ballistic transport and is required to be with a thickness in the range of a few times of the mean-free path of carrier scattering (typically in the range of 10-20 nm), in order to permit the injected carriers transporting through ballistic gate 12 with good efficiency. The needs on a thin thickness unavoidably results in a high sheet resistance to that layer. As described earlier, to reduce parasitic electron tunneling (see
The adverse effect of a large R on memory cell performance can be understood from several directions. First, it can cause a large signal delay due to the combining effects of the large R and the large C (i.e. the RC delay). This is particularly a main issue on cell operation as the RC delay can limit the speed on accessing a memory cell when embedded in a large memory array. Secondly, for disturb prevention on un-selected cells, an optimum set of predetermined voltages usually are required to be applied to those cells. However, due to the RC delay, voltages on un-selected cells can be different than the desired values, and hence cell disturb is more prone to happen. Furthermore, the large R can combine with a large current I to result in a IR effect, which can cause a voltage drop when passing a voltage in a signal line. The effect prevents the voltage on a designated electrode of a memory cell from reaching its desired level, and hence can adversely impact cell operation. For example, the adverse impact on an unselected cell can be an undesired cell disturb, where the cell state is unintentionally changed from one logic state (e.g. a “0”) to the other (e.g. a “1”). The IR impact on a selected cell can be a slower speed on cell operations (i.e. program, erase, and read operations).
Problems on Weak Voltage-Dependence of Tunneling Current
The energy band structure in prior art is constructed to permit charge carriers of one type tunneling from tunneling gate 10 to ballistic gate 12 at a current level similar to that for the backward injected parasitic electrons. This results in weak voltage-dependence on the current-voltage relationship. For example, the current for an erase disable condition (i.e. the condition to prevent an unselected cell from an erase disturb) is seen only 104 times lower than that for the erase condition. Similar results can be seen in the program disable condition of prior art. Therefore, unselected cells in prior art are prone to cell disturb issues in both program and erase operations.
The aforementioned problems (e.g. impact ionization, dielectric breakdown, parasitic capacitance, large resistance, and weak voltage-dependent tunneling current etc.) also exist in the transistor by Mead. Further, another major problem encountered by the transistor is to do with the low transfer ratio due to the low efficiency of the injection mechanism. Choosing electron as the ballistic carriers for transistor operation can somewhat improve the transfer ratio due to a higher efficiency for electron than that for holes. However, the efficiency typically still ranges from about 0.01 to about 0.4, and thus prevents the transistor from practical applications.
These problems can be overcome in accordance with one aspect of the present invention by providing a piezo-ballistic-charge-injection mechanism. Employing the mechanism, the present invention further provides technique altering effective mass of ballistic charge carriers and hence its mean-free-path. Additionally, employing the mechanism, the present invention provides technique increasing carriers population in sub-bands or valleys favorable to their transport. The piezo-ballistic-charge-injection mechanism is implemented in cell structures in accordance with the present invention. Further, these problems can be overcome in accordance with another aspect of the present invention by providing a barrier height engineering concept on energy band structure, by providing a novel method altering barrier heights, by providing injection filter structures, and by providing new structures on cell and devices.
It is an object of the invention to provide a new injection mechanism and methods, and to devise energy band structure for semiconductor devices and nonvolatile memory.
It is another object of the invention to provide method operating the semiconductor devices and nonvolatile memory using the aforementioned energy band structure and the injection mechanism.
Briefly, a preferred embodiment of the present invention is a semiconductor device. The device comprises a first conductive region, a second conductive region disposed adjacent to and insulated from the first conductive region, a third conductive region disposed adjacent to and insulated from the second conductive region, and a strain source providing mechanical stress to at least one of the first and the second conductive regions.
Briefly, another preferred embodiment of the present invention is a method operating a semiconductor device having a first conductive region, a second conductive region disposed adjacent to and insulated from the first conductive region, a third conductive region disposed adjacent to and insulated from the second conductive region, and a strain source providing mechanical stress to at least one of the first and the second conductive regions. The method comprises the steps of placing a first voltage on the first conductive region, placing a second voltage on the second conductive region, and placing a third voltage on the third conductive region to inject charge carriers from the first conductive region through the second conductive region into the third conductive region via piezo-ballistic-charge-injection mechanism.
Briefly, another preferred embodiment of the present invention is a method operating a nonvolatile memory cell having a plurality of states. The memory cell comprising a first conductive region, a second conductive region, a charge injection filter in between the first and the second conductive regions, a third conductive region disposed adjacent to and insulated from the second conductive region, a strain source providing mechanical stress to at least one of the first and the second conductive regions, and spaced-apart source and drain regions of a first conductivity type in a body of a semiconductor of a second conductivity type. The method comprising the steps of applying a first voltage to the first conductive region, applying a second voltage to the second conductive region, applying a body voltage to the body, applying a source voltage to the source region, and applying a drain voltage to the drain region to establish one of the plurality of states of the memory cell by injecting ballistic charge carriers from the first conductive region through the second conductive region into the third conductive region via piezo-ballistic-charge-injection mechanism.
Summary on Advantages of the Present Invention:
These and other objects and advantages of the present invention will become clear to those skilled in the art in view of the description of the preferred embodiment as described herein and as illustrated in the figures of the drawings.
The invention is herein described, by ways of example only, with reference to the accompanying drawings, wherein
Embodiments of the present invention described in the following detailed description are directed at injection mechanisms, methods and memory cell structures. Those of ordinary skill in the art will realize that the detailed description is illustrative only and is not intended to restrict the scope of the claimed inventions in any way. Other embodiments of the present invention, beyond those embodiments described in the detailed descriptions, will readily suggest themselves to those of ordinary skill in the art having the benefit of this disclosure. Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. Where appropriate, the same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or similar parts.
In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will be appreciated that the development effort on achieving specific goals can vary from one implementation to another and from one manufacturer to another. Such efforts might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.
Piezo-effect is a well-known physical phenomenon in solid-state physics. Piezo-effect can change electrical properties of a semiconductor material when a mechanical stress is applied to such material (see Pikus and Bir, Symmetry and Strain-Induced Effects in Semiconductors, New York: Wiley, 1974). The mechanical stress can be originated from a strain source (also can be termed as “stressor”) that is either internal or external to the material. This mechanical stress can be either in compressive form (compression), or in tensile form (tension), and can results in a strain in the material. It breaks the symmetry within the crystal lattice and hence deforms the potential therein. Some well-known applications of the piezo-effect on semiconductors (e.g. silicon) are piezo-resistive effect in resistors, piezo-junction effect in bipolar transistors and diodes, piezo-Hall effect in sensors, and piezo-FETs in MOS transistors (“MOSFETs”).
The present invention provides the application of the piezo-effect to the ballistic charge carrier injection and transport. A novel piezo-ballistic-charge-injection mechanism is provided with illustrations made herein to various embodiments of memory cells and semiconductor devices.
It is known that when a strain is in presence in semiconductors, it can split valleys in conduction band and degeneracy in valence sub-bands of HH and LH (see Hensel et al., “Cyclotron Resonance Experiments in Uniaxially Stressed Silicon: Valence Band Inverse Mass Parameters and Deformation Potentials, Phys. Rev. 129, pp. 1141-1062, 1963).
It is known that the effective mass of a lifted valence sub-band to first order can be shifted linearly with stress (see Hensel et al., “Cyclotron Resonance Experiments in Uniaxially Stressed Silicon: Valence Band Inverse Mass Parameters and Deformation Potentials, Phys. Rev. 129, pp. 1141-1062, 1963, and see Hinckley et al., “Hole Transport Theory in Pseudomorphic Si1-xGex Alloys Grown on Si(001) Substrates,” Phys. Rev. B, 41, pp. 2912-2926, 1990). Employing this relationship in together with the relationship between effective mass and mean-free-path, the present invention provides a method to alter the mean-free-path of piezo-ballistic-charges. This method represents another embodiment of the piezo-ballistic-charge-injection mechanism, and is illustrated by adjusting the level of the stress along direction parallel to the direction of charge transport.
It should also now be clear that ballistic hole injection with heavy-hole can exist and can reduce the erase efficiency when employing ballistic hole mechanism of prior art for erase operation of memory cells. It should also be clear that the transport mechanism of ballistic carriers (LH, HH, or electrons) can be altered by employing the piezo-ballistic-charge-injection mechanism. It should also be clear to those of ordinary skill in the art that the teachings of this disclosure can be applied to select different type of stress (e.g. tensile or compressive stress) and to change the axis of the stress through which the holes population and their mean-free-path are altered such that the injection efficiency in these cases can be enhanced.
Although the forgoing discussion has focused on injection of piezo-holes, it will be clear to those ordinary skills in the art that similar considerations, their effects and advantages apply to piezo-ballistic-electrons-injection. Further, although the forgoing discussion has focused on semiconductor (e.g. silicon), it will be clear to those ordinary skills in the art that similar considerations, their effects and advantages apply to other type of conductors (e.g. TiN, TaN, Si1-xGex alloys etc.).
The STG 60 can be biased positively with respect to the SBG 66 to inject piezo-ballistic holes. The bias permits both types of holes 72 and 73 in STG 60 region to tunnel through a tunneling barrier having a valence band barrier height 75 between valence band 60 b of STG 60 and valence band 63 b of TD 63. While traversing SBG 66, the HH 73 can experience strong scattering and hence lose its energy to become HH 73 a. Therefore, HH 73 cannot be injected into CSR 68. The LH 72, however, behaves very differently from the HH 73. Due to its longer mean-free-path, the LH 72 can traverse the SBG 66 with much less scattering than the HH 73. Therefore, LH can preserve their energy at level higher than the valence band 66 b of SBG 66 while traversing SBG 66. Some of these holes are able to reach the interface between SBG 66 and RD 70. When this positive bias is increased to a value such that those LH have energy higher than the barrier height 77, the LH 72 will be able to enter the valence band 70 b of RD 70, making their way through RD 70 and be collected on CSR 68.
It is noted that while STG 60 is strained under the mechanism described herein, the SBG region 66 can also be strained under a condition in accordance with another embodiment of the piezo-ballistic-charge-injection mechanism such that the mean-free-path of holes traversing the SBG region 66 can be longer than mfp* of that region. For example, this can be done by applying a compressive stress to SBG 66 to take advantage on the effect shown in
The charge injection filter 62 is disposed in between the STG 60 and the SBG 66 to permit transporting charge carriers of one polarity type (e.g. LH 72) from the STG 60 through the SBG 66 to the CSR 68 and to block transporting charge carriers of an opposite polarity type (e.g. electrons 74) from the SBG 66 to the STG 60. For the piezo-ballistic-hole-injection shown in
The charge injection filter provided herein is based on a barrier height engineering concept. One specific embodiment illustrated in the present invention comprises a p+ polysilicon for the STG 60, a silicon dioxide (“oxide”) layer for the TD 63, a silicon nitride (“nitride”) layer for the BD 64, and an n+ polysilicon for the SBG 66. The n+ polysilicon is considered for SBG 66 due to several considerations. A major consideration lies in the much higher solid solubility for n-type impurities (e.g. Arsenic, phosphorous etc) than that for p-type impurities (e.g. Boron). Impurity with a higher solid solubility is desirable as it usually can dope the silicon heavier to result in a lower sheet resistance, and is favorable for integrated circuits (IC) application. In the embodiment, polysilicon is employed as the material for STG 60 and SBG 66 due to its well proven yieldability, manufacturability, and compatibility with state of the art IC technology. An oxide with a thickness of about 7 nm to 10 nm is employed for the RD 70 due to the same reason. The oxide layer used for TD 63 can be with a thickness in the range of about 1.5 nm to 4 nm and preferably in the range of about 2 nm to 3.5 nm. The thickness of TD 63 layer is chosen in the range where charge-carriers (electrons, LH or HH) transporting across the layer are primarily through the direct tunneling mechanism. The thickness of BD 64 is chosen to block charge-carriers from tunneling through both BD 64 and TD 63 layers when a modest voltage in the range of about 1 V to about 2.5V is applied between STG 60 and SBG 66. The thickness of BD 64 is further chosen to permit one type of charge carriers (e.g. LH) transporting in the forward direction and to block the other type of charge carriers (e.g. electrons) from transporting in the backward direction when in a higher voltage range (3V or higher). As will be described in the barrier height engineering theory hereinafter, the selection on thickness of BD 64 is also determined by it dielectric constant. In general, the thickness of BD 64 can be thinner or thicker than that of TD 63 provided the tunneling stack of TD 63 and BD 64 can effectively meet the forgoing requirements. For example, in the specific embodiment, if an oxide with 3 nm (or 30 Å) is chosen for TD 63, then the minimum thickness for BD 64 can be about 2 nm (or 20 Å) or thicker. For the specific embodiment, the oxide for TD 63 can be a HTO (high temperature oxide) or a TEOS layer formed by using conventional deposition technique, or a thermal oxide by using thermal oxidation technique well-known in the art. The nitride for BD 64 can be a high quality nitride without charge trapping centers in its band gap. This high quality nitride can be formed in NH3 (ammonia) ambient at a high temperature (e.g. 1050° C.) by using, for example, RTN (Rapid Thermal Nitridation) technique well-known in the art.
Barrier Height Engineering for Piezo-Ballistic-Holes-Injection
A greater detail on the barrier height engineering concept is now provided.
It is now clear that with the energy band structure in accordance with the present invention, there are two hole barriers 85 and 87 relevant to the forward injected piezo-ballistic-charges of LH 72 and HH 73. Similarly, there are two electron barriers 78 and 81 relevant to the backward injected electrons 74 in SBG 66. To permit an efficient piezo-ballistic-charge-injection, it is desirable that the barriers heights of the first and the second hole barriers 85 and 87 can be electrically altered to assist the forward injection of piezo-ballistic-charges. In a contrast, to block the electrons 74 in SBG 66 from backward injection into STG 60, it is desired to keep the barrier heights 79 and 80 of the first electron barrier 78, and the barrier heights 82 and 83 of the second electron barrier 81 high enough through out the voltage range for the piezo-ballistic charge injection.
The barrier height 86 (ΔΦVH
V′TD is the voltage drop across TD 63 during piezo-ballistic-hole-injection, and is expressed as
V′ TD=(V a −V fb)/[1+(∈TD *T BD)/(∈BD *T TD)].
Va is the applied voltage across STG 60 and SBG 66;
Vfb is the flat-band voltage;
∈TD and ∈BD is the dielectric constant for TD 63 and BD 64, respectively; and
TTD and TBD is the thickness for TD 63 and BD 64, respectively.
Similarly, the barrier height 82 (ΔΦCE
V′BD is the voltage drop across BD 64 during piezo-ballistic-hole-injection, and is expressed as
V′ BD=(V a −V fb)/[1+(∈BD *T TD)/(∈TD *T BD)].
Based on the theory, a concept on engineering barrier height for selectively filtering charge carriers is provided herein. From the formula (1) and (2) provided herein, it is clear that barrier height 86 (ΔΦVH
This effect is provided in the present invention and is used for charge injection, charge blocking, and charge filtering. The effect can become clearer with referencing to
It is desirable to maintain a trapezoidal-shaped band structure for the first electron barrier 78 in BD 64 within voltage range used for injecting piezo-ballistic-holes. This can be achieved by keeping the voltage across BD 64 (V′BD) less than the barrier height 79 (ΔΦCE
The energy band in
For the specific embodiment, voltage of STG 60 is chosen in the range of about +5.0 V to about +6.0 V relative to voltage of SBG 66 for the piezo-ballistic-holes-injection.
The forgoing illustration on the piezo-ballistic-charge-injection and the barrier height engineering is made on holes. Similar illustration can be made for injecting piezo-electrons, and is described next for completeness.
Barrier Height Engineering for Piezo-Ballistic-Electrons-Injection
Turning now to
Turning back to
VTD is the voltage drop across TD during piezo-ballistic-electron-injection, and is expressed as
V TD=(V a −V fb)/[1+(∈TD *T BD)/(∈BD *T TD)];
Va is the applied voltage across STG 60 and SBG 66;
Vfb is the flat-band voltage;
Similarly, the barrier height 99 a (ΔΦVH
VBD is the voltage drop across BD 64 during piezo-ballistic-electron-injection, and is expressed as
V BD=(V a −V fb)/[1+(∈BD *T TD)/(∈TD *T BD)].
From the foregoing formula (3) and (4), it is clear that barrier height 94 (ΔΦVE
It is desirable to keep the voltage across BD (VBD) be less than the barrier height 98 a in voltage range normally used for piezo-ballistic-electrons injection. Keeping VBD lower than barrier height 98 a is desirable because it can maintain a trapezoidal-shaped band structure for holes barrier 98 in BD 64 to block the backward injected LH and HH more effectively. This barrier structure can become clear by referring to
One of the unique portions of the present invention lies in the effects provided by the barrier height engineering concept and its implementation in the injection filter. The effects remove requirement on a large work function for the SBG 66 material in prior art. Furthermore, the injection filter provides voltage divider function, permitting voltage applied between STG 60 and SBG 66 be divided and shared by BD 64 and TD 63 without compromising piezo-ballistic-charge-injection. The voltage divider function can resolve the dielectric breakdown problem in prior art. Moreover, impact-ionization problem in STG 60, which can be triggered by the backward injected charge carriers, can be effectively resolved while suppressing these carriers from backward injection by employing the injection filter.
It is thus clear the injection filter and the energy band structure illustrated in the present invention can effectively block charge carriers of one polarity type from transporting along a backward direction while passing charge carriers of an opposite polarity type transporting along a forward direction during the piezo-ballistic-charge-injection. Thus, the charge injection filter 62 provides charge filtering mechanism to “purify” the charge flow. Though not required, it is generally desirable that the material for SBG 66 has a Fermi level in the flat band condition lies in about the middle of the energy band gap of BD 64 of charge filter 62 to best utilize the charge filtering mechanism when the band structure and the injection mechanism are employed in constructing memory cells.
Barrier Heights Engineering for Disturb Prevention
As employing the ballistic charge injection mechanism and energy band structure of the prior art in memory cell 100 placed in an array environment, cell state (e.g. a “0”) can be unintentionally changed to the other state (e.g. a “1”) during the useful lifetime of usage due to cumulative disturbance introduced while conducting cell operations (e.g. program, erase, and read) throughout other cells that are within a same memory array. As will be described herein, the prior art cell is prone to these types of disturb problems. These disturb problems can however be solved with the piezo-ballistic-charge-injection mechanism and energy band structure of the present invention.
Program disturb can happen in an unselected memory cell in a memory array while programming a selected cell using the piezo-ballistic-electrons-injection mechanism. The worse case for program disturb corresponds to the situation when CSR 68 of an unselected cell is positively charged (e.g. in the erased state). Turning now back to
where VTD is the potential across TD 63 when a voltage of program disturb is applied between STG 60 and SBG 66. By keeping a positive value for ΔΦVE
Similarly, a second barrier is the barrier 93 having barrier heights 94 (ΔΦVE
where VBD is the potential across BD 64 when the voltage of program disturb is applied between STG 60 and SBG 66. By keeping a positive value for ΔΦVE
With the barrier height engineering concept, the energy band structure constructed in the present invention provides a more effective structure preventing the program disturb than that in the prior art. Referring back to
As is clear mathematically in this formula, keeping the magnitude of Vpd lower than a summation of ΔΦCB
As described hereinbefore, the barrier height engineering permits a portion of Vpd be dropped across BD 64 region. Therefore, the voltage across TD 63 is lower than that in the prior art. A lower voltage across TD 63 can prevent the formation of conduction electrons in the p+ polysilicon of STG 60, and hence prevents program disturb caused by the higher energy electrons 40 that occur in prior art. In the situation where electrons 40 do get formed in STG 60, program disturb of electrons 40 can be suppressed by keeping the two barrier heights, 94 and 95, of the trapezoidal barrier high enough such that electrons 40 can be blocked from tunneling through TD 63 and BD 64. This can be done through optimizing the barrier structure, as taught in the barrier height engineering theory.
Erase disturb can happen in an unselected memory cell in a memory array while erasing a selected cell using the piezo-ballistic-holes-injection mechanism. The worse case for erase disturb corresponds to the situation when CSR 68 of the unselected cell is negatively charged (e.g. in the programmed state). Please turn back to
where V′TD is the potential across TD 63 during the erase disturb. Thus, by keeping a positive value for ΔΦVE
Similarly, a second barrier is the barrier 87 having barrier heights 86 (ΔΦVH
where V′BD is the potential across BD 64 during the erase disturb. By keeping a positive value for ΔΦVH
Turning now to
With the barrier height engineering concept, the energy band constructed in the present invention provides a more effective structure preventing the erase disturb in the memory cell. Referring back to
As is clear mathematically in this formula, keeping Ved lower than the summation of ΔΦVB
For the specific embodiment, voltage of STG 60 is chosen in the range of about +2.0 V to about +2.5 V relative to voltage of SBG 66 for erase disturb prevention.
Although the forgoing discussions in
The Memory Cells of the Present Invention
The memory cells of the present invention can be programmed by employing the piezo-ballistic-electron-injection mechanism and erased by employing the piezo-ballistic-hole-injection mechanism described hereinbefore.
The strain material 65 can be a dielectric providing different types of stress (e.g. compressive stress or tensile stress) and is used for generating piezo-effect in STG 60 and SBG 66 for the piezo-ballistic-charge-injection. The stress can be a uniaxial stress with a stress axis generally parallel to the surface of the second portion 67 b of SBG 66 and along a first direction shown in a dash arrow 71. A preferred embodiment for the strain material 65 comprises nitride. The stress level and physical properties of the nitride can be controlled by the thickness and process conditions in its formation. For example, by changing the pressure on chemical elements (e.g. silane) during its formation, magnitude on stress level in the range of about 50 MPa to about 1 giga Pascal (“GPa”) can be achieved. The nitride can be formed to have either tensile stress or compressive stress by employing well-known chemical-vapor-deposition (“CVD”) techniques such as thermal-CVD (for tensile stress nitride) or plasma-CVD (for compressive stress nitride). Further, the stress level of nitride can be tailored or even be relaxed if necessary by using well-known technique, such as ion implanting Ge into the nitride with implant dosage above a threshold level (e.g. about 1×1014 atoms/cm2).
It should be clear to those of ordinary skill in the art having the benefit of this disclosure that the strain source resulting in piezo-effect on SBG and STG in the present invention need not be originated from the strain material 65 and need not be from its shown location, but rather can be from any other means and in any other regions in the memory cell. Further, the stress need not be of the uniaxial type but rather can be other type (e.g. biaxial type). For example, the strain source can be from the SBG when a polysilicon is employed as material for that region. This is because polysilicon can provide tensile stress with stress level typically in the range of about 200 MPa to about 500 MPa. Another material for the strain source is tungsten-silicide, which is a widely used material in manufacturing semiconductor IC. Tungsten-silicide provides stress level in the range of about 1.5 GPa to about 2 GPa, and can be employed alone as the material for SBG or can be formed atop of a polysilicon layer to collectively form the SBG. Other materials such as amorphous silicon, poly SiGe, TaN, TiN etc. can also be considered as material for supporting the piezo-ballistic-charge-injection. Moreover, means introducing strain need not be from employing strain materials, but rather can be through other approaches, such as ion implanting heavy atoms (e.g. Si, Ge, As etc.) into the regions of crystal to be strained. Implanting heavy atoms at dosage above a critical dosage can disturb the periodicity of crystal lattice, and create dislocation loops and hence stress in that region. Further the stress in that region can provide strain to region adjacent to it. The stress in the implanted region can be preserved by implanting atom such as nitrogen in that region to prevent stress from being relaxed in later processing steps during cell manufacturing. The ion implantation approach has the advantage on process simplicity as it does not require depositing and etching strain material. Further it can form stress in implanted regions and hence can localize the stress in regions where strain effect is most desired. Among all these approaches, they all provide desired piezo-effect for the piezo-ballistic-charge-injection in accordance with the present invention. Additionally, although one strain source is illustrated in memory cells in accordance with the present invention, it should be clear to those of ordinary skill in the art that two or more strain sources can coexist in the same cell to provide any variations on stress (tensile or compressive) to various regions of memory cell falling within the scope of the appended claims.
It is thus clear that the strain source can be arranged in different ways to strained regions (e.g. STG 60) in memory cell in accordance with the present invention. The strength of the strain effect of a strain source on strained regions is typically stronger in regions in direct contact with the strain source, and can be somewhat weaker and relaxed in regions not in direct contact therewith. In some cases, the strain can be even of a reverse type in strained regions not in direct contact with the strain source. For example, the strain in these regions can be of compressive type of strain when a tensile type of strain source is disposed adjacent thereto and insulated therefrom. These combined effects provide a scheme to separately optimize the strains in STG and in SBG for an optimum usage of the piezo-ballistic-charges-injection mechanism.
The isolation scheme for all the memory cells disclosed so far are illustrated based on junction isolation scheme, where drain 57 of two adjacent cells are isolated by the well 3.
It should be clear to those of ordinary skill in the art that although the cell structures from 500 to 580 in forgoing embodiments are illustrated with the strain material 65 in contact with SBG 66 directly, other alternative configurations on the SBG 66, such as examples shown in
In the prior art, material with a larger work function is one of the major criteria on material selection for ballistic gate 12, where ballistic charges traverse. The present invention removes this constraint totally, and the material for the ballistic transport region SBG 66 can be any kind of conductive materials. To emphasize this effect, the piezo-ballistic-charges-injection mechanism of the present invention is illustrated by choosing material of a smaller work function, namely, n+ polysilicon, for SBG 66. It should be apparent to those of ordinary skill in the art that the material for SBG 66 of the present invention is not limited to n+ polysilicon, but can encompass any other type of conductive materials such as p+ polysilicon, amorphous silicon, porous polysilicon, poly SiGe, Pt, Au, Tungsten (W), Mo, Ru, Ta, silicide (e.g. NiSi, CoSi), TaN, TiN etc.
It should be noted that in the injection filter the dielectric constant of BD 64 is illustrated to be greater than that of TD 63. It should be clear to those of ordinary skill in the art that the teaching of this disclosure can be applied to modify the injection filter to effectively block the parasitic charge carriers (electrons or holes) from backward injection. For example, the BD 64 layer of the filter can be modified to material having energy gap narrower and dielectric constant similar to that of TD 63. Moreover, the layer of BD 64 need not be a material with a uniform chemical element but can be a material with graded composition on its element. Further, the filter need not comprise two dielectrics (i.e. TD and BD) but can comprise any number of layers of dielectrics such that the filter can effectively block and filter charges. For example, an additional layer of dielectric can be placed on the other side of BD 64 to form the filter having BD 64 disposed in between TD 63 and the additional layer. The additional layer can have material property and thickness similar to that of TD described earlier. In addition, any appropriate dielectric, such as oxynitride (“SiON”), aluminum oxide (“Al2O3”), hafnium oxide (“HfO2”), zirconium oxide (“ZrO2”), tantalum pen-oxide (“Ta2O5”) etc. can be used in place of oxide or nitride. Furthermore, any composition of those materials and the alloys formed thereof, such as hafnium oxide-oxide alloy (“HfO2—SiO2”), hafnium-aluminum-oxide alloy (“HfAlO”), hafnium-oxynitride alloy (“HfSiON”) etc. can be used in place of oxide or nitride.
It is to be understood that the present invention is not limited to the illustrated herein and embodiments described above, but encompasses any and all variations falling within the scope of the appended claims. For example, although the present invention is illustrated in nonvolatile memories of electrically erasable programmable read only memory (EEPROM), it should be apparent to those having ordinary skill in the art that it can be extended to any other type of nonvolatile memories (such as Electrical Programmable Memory or EPROM). Further, although the present invention is illustrated in a single cell, it should be apparent to those of ordinary skill in the art that a plurality of cells of the present invention can be arranged in a rectangular array of rows and columns in a NAND or a NOR array architecture well known in the art.
Additionally, the present invention is illustrated in non-volatile memory cell storing charges on CSR of a conductive or semiconductor material (i.e. the “floating-gates”) that is electrically insulated from but capacitively coupled to surrounding electrodes. In such storage scheme, charges are evenly distributed through out the conductive region. However, it should be apparent to those of ordinary skill in the art that the present invention is not limited to the illustrated herein and embodiments described above, but can encompass any other types of schemes and media for storing charges. For example, the memory cells of the present invention can store charges in localized storage sites such as nano-particle or in traps of a dielectric layer. The advantage of these charge storing schemes is a negligible interference between adjacent cells when they are arranged in a memory array. Furthermore, in the event there is a local breakdown in surrounding insulators of one of the storage sites, charges stored at other sites can still be retained. The dielectric having traps as the storage sites can be a nitride layer formed, for example, by using LPCVD (Low-Pressure-Chemical-Vapor-Deposition) technique well-known in the art. Other dielectrics such as HfO2 and ZrO2 having traps of a deeper trapping energy can also be considered as material for the trapping dielectric. The nano-particles as the storage sites can be silicon nano-crystals each in an oval shape having a diameter in the range of about 2 nm to about 7 nm, and can be formed by using well-known CVD technique. The nano-particles are not limited to the silicon nano-particles but can be nano-crystals of any other type of materials (e.g. Ge, SiGe alloy, HfO2 etc.) that can effectively store charges.
Furthermore, the strain material of the present invention need not be disposed on both sides of STG, need not be disposed over SBG, need not be rectangular in their cross-sections, need not be in direct contact with STG, need not be in direct contact with SBG, but rather can be disposed over STG, can be disposed under SBG, can be in any position adjacent to STG and SBG, can be any size and shape in their cross-sections, can be in indirect contact with STG, and can be in indirect contact with SBG that effectively provide strain to STG and to SBG in each memory cell. Additionally, the strain material of the present invention need not be nitride, need not be a dielectric, need not be providing tensile stress, need not be providing compressive stress, but rather can be any other types of material and can provide any type of stress (e.g. shear stress) that effectively provide piezo-effect for piezo-ballistic-charges injection.
Moreover, the charge storage region of the present invention need not be in rectangular shape in their top view, need not be in rectangular in their cross-sections, but rather can be any size and shape in their top view and in their cross-sections that effectively store charges and effectively connects the drain 57 and source 56 regions in each memory cell. Additionally, the top surface portion of the charge storage region need not be co-planar with the substrate surface, but rather can be at any level under or above the substrate surface that permit the charge storage region to effectively store charges, effectively capacitive-coupled with SBG 66 and the body 59, and effectively connects the drain 57 and source 56 regions in each memory cell. Similarly, the bottom surface portion of the charge storage region need not be parallel to the substrate surface, need not be flat, but rather can be with other shape that permit charge storage region to effectively store charges, effectively capacitive-coupled with SBG 66 and the body 59, and effectively connects the drain 57 and source 56 regions in each memory cell. Likewise, the top and the bottom surface portion of TD 63 and BD 64 need not be parallel to the substrate surface, need not be flat, need not be co-planar with the substrate surface, but rather can be at any level under or above the substrate surface, in any angle with the substrate surface, and with other shape that can effectively permit piezo-effect charge carriers tunneling in the forward direction and blocked in the backward direction. Additionally, the surface of the channel region need not be co-planar with the substrate surface, but rather can be at any level under or above the substrate surface or in any angle with the substrate surface that effectively connects the drain 57 and source 56 regions in each memory cell. Moreover, source 56 and drain 57 regions, and/or source and drain lines, can be swapped. Further, those of skill in the art will recognize the source resulting in strain need not be termed “strain source” but can be in any other terms (e.g. “stressor”, “stress source” etc.) that can provide mechanical stress to generate piezo-effect on charge injection and transports.
It should be clear to those of ordinary skill in the art that the teachings of this disclosure can be applied to modify the architecture of the strain source and the charge injection filter through which the effects resulting in the advantages of the present invention can be achieved.
Self-Limiting Ballistic Charge Injection on Memory Cell Operation
The self-limiting mechanism and its usage on cell design and cell operation will now be provided using a simple capacitance model. The CSR 68 is approximately at a potential given by the following equation:
V CSR=(Q CSR +ΣC i V i)/C total (9)
ΣC i V i =C CSR-S *V S +C CSR-D *V D +C CSR-SBG *V SBG +C CSR-B *V B
C total =C CSR-S +C CSR-D +C CSR-SBG +C CSR-B,
QCSR is the total injected charges (electrons or holes) accumulated on the CSR 68;
CCSR-S is the capacitance between CSR 68 and source 56;
CCSR-D is the capacitance between CSR 68 and drain 57;
CCSR-SBG is the capacitance between CSR 68 and SBG 66;
CCSR-B is the capacitance between CSR 68 and body 59; and
VS, VD, VSBG, and VB are voltages placed at source, drain, SBG, and body, respectively.
In the situation where a cell is free of any charge in its initial state, the CSR potential VCSR
Self-limiting injection mechanism is illustrated for program operation when a first type of charges (e.g. electrons) is selected as the ballistic carriers. Referring to
E=(Q CSR −Q CSR
Tinsulator is the thickness of RD 70.
The barrier height 76 a (Φe) resulted in the opposing field seen by electron carriers in RD 70 can be approximated by
Φe =q(Q CSR −Q CSR
ΔKe is the energy difference 102 a between the electron-carrier kinetic energy 102 and barrier height 76 at the interface between SBG 66 and RD 70; and
q is the electron unit charge.
Therefore, in the situation where Φe is less than zero (i.e. ΔKe being greater than q(QCSR−QCSR
Both the effects described above forms the self-limiting injection mechanism for cell programmed by using piezo-ballistic charge injection. In the initial program stage, so long as the electron carriers 89 can surmount the barrier height 76, carriers are allowed to transport through RD 70 to reach CSR 68. As program event continues, electron charges will continue build up on CSR 68, the potential of CSR 68 will decrease to reach a lower value VCSR
At the completion of a programming event, the total amount of charges on the CSR 68 can be approximated by a simple equation shown as below:
Q CSR =C total(V CSR
In a different form, the total charges can be expressed approximately as:
Q CSR =Q CSR
Therefore, at the end of a programming cycle, the total charges accumulated on the CSR 68 are determined by two major parameters. First, it's determined by the extra energy 102 a (ΔKe) that is over the barrier height 76 for the electron carriers 89. Since the extra energy 102 a is set by the voltage difference between STG 60 and SBG 66, a selection on the bias between gates 60 and 66 hence determines the amount of charges stored on CSR 68. The total cell capacitance Ctotal has a scaling effect and can be optimized through cell design to assist the effect herein. For example, a larger value for the total cell capacitance will result in the need on a smaller bias between gates 60 and 66 for storing a same amount of charges on CSR 68. The second parameter determining the total CSR charges is to do with the CSR charges yielding the flat band condition in RD 70, which in turn can be determined by the voltages applied to each electrodes (e.g. drain 57) of the memory cell as well as the capacitor components of corresponding electrodes. Thus with a choice on a set of these parameters, the present invention allows memory cells be programmed to a state a priori.
Both formulas (11) and (12) suggest effects that can be applied to store multi-level logic states in a memory cell. For example, as suggested in formula (11), to store four levels of logic states (namely, 00, 01, 10, and 11 states) in cell 200 of the present invention, four discrete amounts of charges for QCSR can be stored on CSR by setting VCSR
It is now clear that the injection of electrons onto CSR will continue until the blocking effect on the ballistic electrons taking place. The blocking effect is due to the rising of the energy bands in the CSR 68, which is equivalent to the lowering of the CSR potential as electron charges accumulated thereon. As a result, an injection barrier and its opposing field is formed in RD 70 and the barrier continue to rise as more ballistic electrons injected into and accumulated on the CSR 68. This effect decreases the electron flow from STG 60 onto the CSR 68 until to a point the barrier is high enough to completely block incoming ballistic electrons. The charge blocking mechanism is highly voltage-sensitive. In other words, its current dependence on voltage is more sensitive than that usually observed in the Fowler-Nordheim tunneling. Further, RD 70 is typically with thickness of about 6 nm or thicker, where the voltage-less-sensitive charge tunneling, namely the direct-tunneling phenomenon, is not permitted. These effects provide an effective self-limiting mechanism for ballistic charge injection. The self-limiting mechanism provides a method permitting charges be stored on CSR at multi-level states. This can be done by for example, injecting incremental levels of charges on CSR through incrementally adjusting the bias at regions (such as the drain 57) adjacent to the CSR 68 or through incrementally adjusting the bias between STG 60 and SBG 66. The mechanism thus permits storing multi-level logic states in memory cells of the present invention.
Self-limiting injection mechanism is further provided for erase operation when a second type of charges (e.g. holes) is selected as the injected carriers. Referring to
At the completion of an erase cycle, the total charges on the CSR 68 can be approximated by a simple equation shown as below:
Q CSR =C total(V CSR
In a different form, the total charges can be expressed approximately as:
Q CSR =Q CSR
where ΔKh is the energy difference 104 a between the hole-carrier kinetic energy 104 and barrier height 77 at the interface between SBG 66 and RD 70, and is set by bias between gates 60 and 66.
Therefore, at the end of an erase cycle, the total charges accumulated on CSR 68 are determined by two major parameters in formula (14). First, it can be determined by the extra energy 104 a (ΔKh) that is over the barrier height 77 for the holes 72. A selection on the bias between gates 60 and 66 hence determines the amount of charges stored on CSR 68. The second parameter determining the total CSR charges is QCSR
It should be appreciated by those of ordinary skill in the art that the provision disclosed herein on the self-limiting mechanism is generally true for operating cells using either type of charges. For example, holes can be selected for program operation and electrons can be selected for erase operation. Further, the multi-level logic states can be stored in memory cells by using either type of injection mechanisms.
For memory cells in accordance with the present inventions, it should be noted that both program and erase operations can be done with absolute bias at a level less than or equal to 3.3V. Furthermore, the erase mechanism and cell architecture enable the individually erasable cells feature, which is ideal for storing data such as constants that required periodically changed. The same feature is further extendable to small group of such cells which are erased simultaneously (e.g. cells storing a digital word, which contains 8 cells). Additionally, the same feature is also further extendable to such cells which are erasable simultaneously in large group (e.g. cells storing code for software program, which can contain 2048 cells configured in page, or contain a plurality of pages in block in array architecture).
Finally, the read operation of the cells in accordance with the present invention is described herein for completeness on cell operations. The read operation can best be described when cells are arranged in a rectangular array of rows and columns, wherein a plurality of cells are constructed in NOR or NAND architecture well-known in the art. The read operation can be illustrated in cells having source 56 and drain 57 of n-type conductivity, and body 59 of p-type conductivity. To read a selected memory cell in an array, a ground potential is applied to the source of the cell. A read voltage of approximately +1 volt is applied to the drain and approximately 2.5 volts (depending upon the power supply voltage of the device) is applied to SBG 66 of the selected cell. Other regions (i.e. STG 60 and body 59) are at ground potential. If CSR 68 of the selected cell is positively charged (i.e. CSR is discharged of electrons), then the channel 58 is turned on. Thus, an electrical current will flow from source 56 to drain 57 of the selected cell. This would be the “1” state.
On the other hand, if CSR 68 is negatively charged, the channel 58 is either weakly turned on or is entirely shut off. Even when SBG and drain are raised to the read potential, little or no current will flow through channel 58. In this case, either the current is very small compared to that of the “1” state or there is no current at all. In this manner, the selected memory cell is sensed to be programmed at the “0” state. Ground potential is applied to source 56, drain 57, and SBG 66 for cells in non-selected columns and rows so only the selected memory cell is read. For both selected and non-selected memory cells, ground potential is applied to the body region 59. It should be appreciated by those having ordinary skill in the art that although the read scheme here is illustrated on cell having two logic states (i.e. “0” and “1”), it should be obvious that the scheme can be applied to cell having multi-level of states (e.g. 00, 01, 10, and 11).
The memory cell can be formed in an array with peripheral circuitry including conventional row address decoding circuitry, column address decoding circuitry, sense amplifier circuitry, output buffer circuitry and input buffer circuitry, which are well known in the art.
It is to be understood that the present invention on charge injection mechanism is not limited to the memory cells illustrated herein and embodiments described above but can be extended to any other type of semiconductor devices. For example, the mechanisms in
The unique portion of present invention lies in the effects provided by the piezo-ballistic-charge-injection mechanism and by the barrier-height-engineering. These effects result in unique components in the cell and transistor structures, namely, the strain source for the piezo-ballistic-charge-injection mechanism and the injection filter for the barrier-height-engineering. Although both the components are illustrated simultaneously in the structures, it should be clear to those of ordinary skill in the art that the two components need not coexist in the same cell or transistor, but can exist in any variations falling within the scope of the appended claims. For example, the memory cells of the present invention can comprise the strain source without the injection filter.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3943543||Jul 26, 1974||Mar 9, 1976||Texas Instruments Incorporated||Three level electrode configuration for three phase charge coupled device|
|US3944849||Jun 26, 1974||Mar 16, 1976||Texas Instruments Inc.||Charge transfer device signal processing|
|US4072977||Jul 9, 1976||Feb 7, 1978||Texas Instruments Incorporated||Read only memory utilizing charge coupled device structures|
|US4462090||Jun 30, 1982||Jul 24, 1984||Tokyo Shibaura Denki Kabushiki Kaisha||Method of operating a semiconductor memory circuit|
|US4698787||Nov 21, 1984||Oct 6, 1987||Exel Microelectronics, Inc.||Single transistor electrically programmable memory device and method|
|US4957877||Nov 21, 1988||Sep 18, 1990||Intel Corporation||Process for simultaneously fabricating EEPROM cell and flash EPROM cell|
|US5029130||Jan 22, 1990||Jul 2, 1991||Silicon Storage Technology, Inc.||Single transistor non-valatile electrically alterable semiconductor memory device|
|US5053839||Aug 21, 1990||Oct 1, 1991||Texas Instruments Incorporated||Floating gate memory cell and device|
|US5070480||Jan 8, 1990||Dec 3, 1991||Caywood John M||Nonvolatile associative memory system|
|US5095344||Jun 8, 1988||Mar 10, 1992||Eliyahou Harari||Highly compact eprom and flash eeprom devices|
|US5115289||Aug 5, 1991||May 19, 1992||Hitachi, Ltd.||Semiconductor device and semiconductor memory device|
|US5146426||Nov 8, 1990||Sep 8, 1992||North American Philips Corp.||Electrically erasable and programmable read only memory with trench structure|
|US5153880||Mar 12, 1990||Oct 6, 1992||Xicor, Inc.||Field-programmable redundancy apparatus for memory arrays|
|US5161157||Nov 27, 1991||Nov 3, 1992||Xicor, Inc.||Field-programmable redundancy apparatus for memory arrays|
|US5235544||Nov 9, 1990||Aug 10, 1993||John Caywood||Flash EPROM cell and method for operating same|
|US5268319||Oct 15, 1991||Dec 7, 1993||Eliyahou Harari||Highly compact EPROM and flash EEPROM devices|
|US5270980||Oct 28, 1991||Dec 14, 1993||Eastman Kodak Company||Sector erasable flash EEPROM|
|US5280446||Jun 8, 1992||Jan 18, 1994||Bright Microelectronics, Inc.||Flash eprom memory circuit having source side programming|
|US5286994||Jun 23, 1992||Feb 15, 1994||Rohm Co., Ltd.||Semiconductor memory trap film assembly having plural laminated gate insulating films|
|US5426316||Jun 8, 1994||Jun 20, 1995||International Business Machines Corporation||Triple heterojunction bipolar transistor|
|US5429965||May 18, 1992||Jul 4, 1995||Shimoji; Noriyuki||Method for manufacturing a semiconductor memory|
|US5432739||Jun 17, 1994||Jul 11, 1995||Philips Electronics North America Corporation||Non-volatile sidewall memory cell method of fabricating same|
|US5517044||Dec 20, 1994||May 14, 1996||Nec Corporation||Non-volatile semiconductor memory device having thin film transistors equipped with floating gates|
|US5523243||Jun 8, 1994||Jun 4, 1996||International Business Machines Corporation||Method of fabricating a triple heterojunction bipolar transistor|
|US5557122||May 12, 1995||Sep 17, 1996||Alliance Semiconductors Corporation||Semiconductor electrode having improved grain structure and oxide growth properties|
|US5559735||Mar 28, 1995||Sep 24, 1996||Oki Electric Industry Co., Ltd.||Flash memory having select transistors|
|US5563083||Apr 21, 1995||Oct 8, 1996||Pein; Howard B.||Method of fabricating non-volatile sidewall memory cell|
|US5621738||Dec 10, 1991||Apr 15, 1997||Eastman Kodak Company||Method for programming flash EEPROM devices|
|US5714766||Sep 29, 1995||Feb 3, 1998||International Business Machines Corporation||Nano-structure memory device|
|US5739567||Nov 8, 1994||Apr 14, 1998||Wong; Chun Chiu D.||Highly compact memory device with nonvolatile vertical transistor memory cell|
|US5764096||Nov 21, 1996||Jun 9, 1998||Gatefield Corporation||General purpose, non-volatile reprogrammable switch|
|US5768192||Jul 23, 1996||Jun 16, 1998||Saifun Semiconductors, Ltd.||Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping|
|US5780341||Dec 6, 1996||Jul 14, 1998||Halo Lsi Design & Device Technology, Inc.||Low voltage EEPROM/NVRAM transistors and making method|
|US5790455||Jan 2, 1997||Aug 4, 1998||John Caywood||Low voltage single supply CMOS electrically erasable read-only memory|
|US5792670||Jun 6, 1995||Aug 11, 1998||Sgs-Thomson Microelectronics S.R.L.||Method of manufacturing double polysilicon EEPROM cell and access transistor|
|US5822242||Mar 5, 1997||Oct 13, 1998||Macronix International Co, Ltd.||Asymmetric virtual ground p-channel flash cell with latid n-type pocket and method of fabrication therefor|
|US5838039||Jul 8, 1996||Nov 17, 1998||Matsushita Electronics Corporation||Semiconductor memory having a tunneling region|
|US5847427||Dec 16, 1996||Dec 8, 1998||Kabushiki Kaisha Toshiba||Non-volatile semiconductor memory device utilizing an oxidation suppressing substance to prevent the formation of bird's breaks|
|US5847996||Apr 26, 1996||Dec 8, 1998||Sandisk Corporation||Eeprom with split gate source side injection|
|US5883409||Aug 7, 1997||Mar 16, 1999||Sandisk Corporation||EEPROM with split gate source side injection|
|US5966329||Oct 9, 1997||Oct 12, 1999||Programmable Microelectronics Corporation||Apparatus and method for programming PMOS memory cells|
|US5973356||Jul 8, 1997||Oct 26, 1999||Micron Technology, Inc.||Ultra high density flash memory|
|US6002152||Dec 9, 1998||Dec 14, 1999||Sandisk Corporation||EEPROM with split gate source side injection with sidewall spacers|
|US6080995||Jun 3, 1998||Jun 27, 2000||Sony Corporation||Quantum device|
|US6088263||Nov 15, 1999||Jul 11, 2000||Programmable Silicon Solutions||Non-volatile memory using substrate electrons|
|US6091104||Mar 24, 1999||Jul 18, 2000||Chen; Chiou-Feng||Flash memory cell with self-aligned gates and fabrication process|
|US6103573||Jun 30, 1999||Aug 15, 2000||Sandisk Corporation||Processing techniques for making a dual floating gate EEPROM cell array|
|US6104057||Aug 24, 1998||Aug 15, 2000||Ricoh Company, Ltd.||Electrically alterable non-volatile semiconductor memory device|
|US6201732||Feb 2, 2000||Mar 13, 2001||John M. Caywood||Low voltage single CMOS electrically erasable read-only memory|
|US6211562||Feb 24, 1999||Apr 3, 2001||Micron Technology, Inc.||Homojunction semiconductor devices with low barrier tunnel oxide contacts|
|US6303940||Jun 25, 1999||Oct 16, 2001||Agere Systems Guardian Corp.||Charge injection transistor using high-k dielectric barrier layer|
|US6313487||Jun 15, 2000||Nov 6, 2001||Board Of Regents, The University Of Texas System||Vertical channel floating gate transistor having silicon germanium channel layer|
|US6368915||Mar 16, 2000||Apr 9, 2002||U.S. Philips Corporation||Method of manufacturing a semiconductor device|
|US6372617||Oct 10, 2000||Apr 16, 2002||Nec Corporation||Method of manufacturing non-volatile memory|
|US6384451||Mar 9, 2000||May 7, 2002||John Caywood||Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell|
|US6388922||Jun 9, 2000||May 14, 2002||Sanyo Electric Co., Ltd.||Semiconductor memory and method of operating semiconductor memory|
|US6407424||Sep 2, 1998||Jun 18, 2002||Micron Technology, Inc.||Flash memory with nanocrystalline silicon film floating gate|
|US6411545||Nov 14, 2000||Jun 25, 2002||John Millard And Pamela Ann Caywood 1989 Revokable Living Trust||Non-volatile latch|
|US6426896||May 22, 2000||Jul 30, 2002||Actrans System Inc.||Flash memory cell with contactless bit line, and process of fabrication|
|US6449189||Aug 1, 2001||Sep 10, 2002||Micron Technology, Inc.||Flash memory cell for high efficiency programming|
|US6451652||Sep 7, 2000||Sep 17, 2002||The John Millard And Pamela Ann Caywood 1989 Revocable Living Trust||Method for forming an EEPROM cell together with transistor for peripheral circuits|
|US6469343||Oct 5, 2000||Oct 22, 2002||Nippon Steel Corporation||Multi-level type nonvolatile semiconductor memory device|
|US6479863||Dec 6, 2000||Nov 12, 2002||John M. Caywood||Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell|
|US6503785||May 21, 2001||Jan 7, 2003||Actrans System Inc.||Flash memory cell with contactless bit line, and process of fabrication|
|US6525371||Sep 22, 1999||Feb 25, 2003||International Business Machines Corporation||Self-aligned non-volatile random access memory cell and process to make the same|
|US6525962||Apr 5, 2000||Feb 25, 2003||Cypress Semiconductor Corporation||High current and/or high speed electrically erasable memory cell for programmable logic devices|
|US6534816||Mar 1, 2000||Mar 18, 2003||John M. Caywood||Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell|
|US6555865||Jul 10, 2001||Apr 29, 2003||Samsung Electronics Co. Ltd.||Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same|
|US6574140||Dec 5, 2000||Jun 3, 2003||The John Millard And Pamela Ann Caywood 1989 Revocable Living Trust||Low voltage single supply CMOS electrically erasable read-only memory|
|US6580124||Aug 14, 2000||Jun 17, 2003||Matrix Semiconductor Inc.||Multigate semiconductor device with vertical channel current and method of fabrication|
|US6580642 *||Apr 29, 2002||Jun 17, 2003||Silicon Storage Technology, Inc.||Method of erasing nonvolatile tunneling injector memory cell|
|US6593624||Sep 25, 2001||Jul 15, 2003||Matrix Semiconductor, Inc.||Thin film transistors with vertically offset drain regions|
|US6621107||Aug 23, 2001||Sep 16, 2003||General Semiconductor, Inc.||Trench DMOS transistor with embedded trench schottky rectifier|
|US6680505||Mar 28, 2002||Jan 20, 2004||Kabushiki Kaisha Toshiba||Semiconductor storage element|
|US6709928||Jul 31, 2001||Mar 23, 2004||Cypress Semiconductor Corporation||Semiconductor device having silicon-rich layer and method of manufacturing such a device|
|US6721205||Dec 14, 2000||Apr 13, 2004||Sony Corporation||Nonvolatile semiconductor memory device and methods for operating and producing the same|
|US6734105||Nov 15, 2001||May 11, 2004||Hyundai Electronics Industries Co., Ltd.||Method for forming silicon quantum dots and method for fabricating nonvolatile memory device using the same|
|US6744111||May 15, 2003||Jun 1, 2004||Koucheng Wu||Schottky-barrier tunneling transistor|
|US6745370||Jul 14, 2000||Jun 1, 2004||Heuristics Physics Laboratories, Inc.||Method for selecting an optimal level of redundancy in the design of memories|
|US6747310||Oct 7, 2002||Jun 8, 2004||Actrans System Inc.||Flash memory cells with separated self-aligned select and erase gates, and process of fabrication|
|US6753568||Jul 28, 1999||Jun 22, 2004||Hitachi, Ltd.||Memory device|
|US6756633||Jun 25, 2002||Jun 29, 2004||Silicon Storage Technology, Inc.||Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges|
|US6791883||Jun 24, 2002||Sep 14, 2004||Freescale Semiconductor, Inc.||Program and erase in a thin film storage non-volatile memory|
|US6815764 *||Mar 17, 2003||Nov 9, 2004||Samsung Electronics Co., Ltd.||Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same|
|US6847556||Aug 18, 2003||Jan 25, 2005||Samsung Electronics Co., Ltd.||Method for operating NOR type flash memory device including SONOS cells|
|US6853583||Sep 16, 2002||Feb 8, 2005||Impinj, Inc.||Method and apparatus for preventing overtunneling in pFET-based nonvolatile memory cells|
|US6894339||Jan 2, 2003||May 17, 2005||Actrans System Inc.||Flash memory with trench select gate and fabrication process|
|US6897514||Feb 5, 2002||May 24, 2005||Matrix Semiconductor, Inc.||Two mask floating gate EEPROM and method of making|
|US6936884||Oct 14, 2003||Aug 30, 2005||Samsung Electronics Co., Ltd.||Nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon memory|
|US6952032||Aug 31, 2004||Oct 4, 2005||Micron Technology, Inc.||Programmable array logic or memory devices with asymmetrical tunnel barriers|
|US6958513||Jun 6, 2003||Oct 25, 2005||Chih-Hsin Wang||Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells|
|US7015102||Apr 13, 2005||Mar 21, 2006||Chih-Hsin Wang||Method of forming floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells made thereby|
|US7074672||Feb 10, 2004||Jul 11, 2006||Silicon Storage Technology, Inc.||Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor|
|US7115942 *||Dec 8, 2004||Oct 3, 2006||Chih-Hsin Wang||Method and apparatus for nonvolatile memory|
|US7149118||Sep 7, 2004||Dec 12, 2006||Impinj, Inc.||Method and apparatus for programming single-poly pFET-based nonvolatile memory cells|
|US7297634 *||Feb 9, 2005||Nov 20, 2007||Marvell World Trade Ltd.||Method and apparatus for semiconductor device and semiconductor memory device|
|US20050167734||Nov 19, 2004||Aug 4, 2005||The Regents Of The University Of California||Flash memory devices using large electron affinity material for charge trapping|
|US20050247972||May 6, 2004||Nov 10, 2005||Micron Technology, Inc.||Ballistic direct injection NROM cell on strained silicon structures|
|US20060284236||Jun 21, 2005||Dec 21, 2006||Micron Technology, Inc.||Back-side trapped non-volatile memory device|
|US20070008778 *||Sep 25, 2006||Jan 11, 2007||Chih-Hsin Wang||Methods for operating semiconductor device and semiconductor memory device|
|1||Bock et al., "3.3ps SiGe Bipolar Technology", Proceeding of the IEDM, pp. 255-258, 2004.|
|2||C.A. Mead, "The Tunnel-Emission Amplifier", Proceedings of the IRE, pp. 359-361, 1960.|
|3||Caywood, John M. et al; "A Novel Nonvolatile Memory Cell Suitable for Both Flash and Byte-Writable Applications"; IEEE Transactions on Electron Devices, vol. 49, No. 5, May 2002; pp. 802-807.|
|4||First Examination Report from the State Intellectual Property Office of the People's Republic of China dated Aug. 30, 2007 for Chinese Application No. 2005100804259; 9 pages.|
|5||First Examination Report from the State Intellectual Property Office of the People's Republic of China dated Sep. 6, 2007 for Chinese Application No. 2005100804314; 8 pages.|
|6||Fischetti et al., "Six-bank k.p. calculation of hole mobility in silicon inversion layers: dependence on surface . . . " Journal of Appl. Physics, vol. 94, pp. 1079-1095, 2003.|
|7||H. Fujiwara et al; "High-Efficiency Programming with Inter-Gate Hot-Electron Injection for Flash . . . ," Digest of Non-Volatile Semiconductor Memory Workshop, Feb. 2000; p. 127.|
|8||Heiblum, M. et al; "Direct Observation of ballistic Transport in GaAs," pp. 2200-2203, vol. 55, Physical Review Letters; 1985.|
|9||Hensel et al., Cyclotron Resonance Experiments in Uniaxially Stressed Silicon: Valence Band Inverse Mass Parameters and Deformation . . . , Phys. Rev. 129, pp. 1141-1162, 1963.|
|10||Hinckley et al., "Hole Transport Theory in Pseudomorphic Si1-xGex Alloys Grown on Si(001) Substrates", Phys. Rev. B, 41, pp. 2912-2926. 1990.|
|11||Kitamura et al; "A Low Voltage Operating Flash Cell with High Coupling Ratio Using Horned Floating Gate with Fine HSG"; Jun. 1998 Symposium on FLSI Technology Digest of Technical Papers; pp. 104-105.|
|12||Kuo et al; "FEFET-A High Density, Low Erase Voltage, Trench Flash EEPROM"; Apr. 1994 Symposium on VLSI Technology Digest of Technigal Papers; pp. 51-52.|
|13||Kuo et al; "FEFET—A High Density, Low Erase Voltage, Trench Flash EEPROM"; Apr. 1994 Symposium on VLSI Technology Digest of Technigal Papers; pp. 51-52.|
|14||Lai, Stefan; "Flash Memories: Where We Were and Where We Are Going"; Sep. 1998 IEEE; pp. 971-973.|
|15||Lenzlinger and Snow; "Fowler-Nordheim Tunneling into Thermally Grown SiO2," J. Appl. Phys., vol. 40, No. 1, Jan. 1969; pp. 278-283.|
|16||Nicollian and Brews; "MOS Physics and Technology," Wiley-Interscience, 1982, "Photo I-V method-Basics", pp. 512-515.|
|17||Nicollian and Brews; "MOS Physics and Technology," Wiley-Interscience, 1982, "Photo I-V method—Basics", pp. 512-515.|
|18||Pein, H. et al; "Performance of the 3-D Sidewall Flash EPROM Cell", IEDM Technical Digest, pp. 11-14, 1993.|
|19||S. Sze; "Physics of Semiconductor Devices," Wiley-Interscience, 1981, "Schotky Effect", pp. 250-253.|
|20||SMA111-Compound Semiconductors; Lecture 2-Metal-Semiconductor Junctions-Outline; C. G. Fonstad; Feb. 2003; 22 pages.|
|21||SMA111—Compound Semiconductors; Lecture 2—Metal-Semiconductor Junctions—Outline; C. G. Fonstad; Feb. 2003; 22 pages.|
|22||U.S. Appl. No. 09/860,704, filed Nov. 2003, Harari et al.|
|23||U.S. Appl. No. 09/866,938, filed Oct. 2001, Noble et al.|
|24||U.S. Appl. No. 09/881,332, filed Dec. 2002, Jones et al.|
|25||U.S. Appl. No. 09/916,555, filed Mar. 2002, Wang et al.|
|26||U.S. Appl. No. 09/925,134, filed Jan. 2004, Haran, et al.|
|27||U.S. Appl. No. 09/942,338, filed Feb. 2004, Caywood.|
|28||U.S. Appl. No. 09/955,285, filed Dec. 2002, Kim.|
|29||U.S. Appl. No. 10/040,724, filed May 2003, Wang et al.|
|30||U.S. Appl. No. 10/066,376, filed Oct. 2002, Kouznetsov et al.|
|31||U.S. Appl. No. 10/105,741, filed Sep. 2003, Kianian, et al.|
|32||U.S. Appl. No. 10/183,834, filed Jul. 2003, Wang et al.|
|33||U.S. Appl. No. 10/192,291, filed Jul. 2003, Wang.|
|34||U.S. Appl. No. 10/205,289, filed Mar. 2003, Wang.|
|35||U.S. Appl. No. 10/330,851, filed Jul. 2003, Lee et al.|
|36||U.S. Appl. No. 10/348,267, filed Jul. 2003, Jones et al.|
|37||U.S. Appl. No. 10/393,896, filed Sep. 2004, Chen et al.|
|38||U.S. Appl. No. 10/409,407, filed Oct. 2004, Chen et al.|
|39||U.S. Appl. No. 10/718,662, filed Jul. 2004, Kan et al.|
|40||U.S. Appl. No. 10/776,483, filed Aug. 2004, Kianian, et al.|
|41||U.S. Appl. No. 10/791,486, filed Aug. 2004, Harari.|
|42||U.S. Appl. No. 10/797,296, filed Dec. 2004, Lee et al.|
|43||U.S. Appl. No. 10/799,180, filed Sep. 2004, Yuan et al.|
|44||U.S. Appl. No. 10/848,982, filed Oct. 2004, Wang.|
|45||U.S. Appl. No. 10/849,975, filed Oct. 2004, Wang et al.|
|46||U.S. Appl. No. 10/850,031, filed Oct. 2004, Wang et al.|
|47||Vogelsang et al., "Electron Mobilities and high-Field Drift Velocity in Strained Si9licon on Silicon-Germanium Substrate", IEEE Trans. on Electron Devices, pp. 2641-2642, 1992.|
|48||Wang, Chih Hsin; "Three-Dimensional DIBL for Shallow-Trench Isolated MOSFET's"; IEEE Transactions on Electron Devices, vol. 46, No. 1, Jan. 1999; pp. 139-144.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8664712 *||Nov 15, 2010||Mar 4, 2014||Soitec||Flash memory cell on SeOI having a second control gate buried under the insulating layer|
|US20110134698 *||Jun 9, 2011||Carlos Mazure||FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER|
|U.S. Classification||438/261, 257/315, 438/257, 257/E21.17, 438/265, 257/E21.585, 365/185.18, 257/316, 257/E27.103, 438/259, 257/324, 257/E21.68|
|International Classification||H01L27/115, H01L29/788, H01L29/423, H01L21/8247, G11C16/04, H01L21/331, H01L21/336|
|Cooperative Classification||H01L29/42324, H01L27/11521, G11C16/0416, H01L29/7881, H01L27/115, H01L27/11568, H01L29/7883, H01L29/42336, H01L29/792, H01L29/7885|
|European Classification||H01L29/788B6B, H01L27/115G4, H01L29/423D2B2D, H01L29/788B, H01L29/792, H01L29/788B4, H01L27/115, H01L27/115F4, H01L29/423D2B2|