|Publication number||US7825516 B2|
|Application number||US 10/316,484|
|Publication date||Nov 2, 2010|
|Filing date||Dec 11, 2002|
|Priority date||Dec 11, 2002|
|Also published as||CN1295786C, CN1507047A, US20040113277|
|Publication number||10316484, 316484, US 7825516 B2, US 7825516B2, US-B2-7825516, US7825516 B2, US7825516B2|
|Inventors||Stefanie Ruth Chiras, Michael Wayne Lane, Sandra Guy Malhotra, Fenton Reed Mc Feely, Robert Rosenberg, Carlos Juan Sambucetti, Philippe Mark Vereecken|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (51), Non-Patent Citations (1), Referenced by (3), Classifications (32), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention is in the field of the use of a metal such as copper (Cu) that may exhibit diffusion and electromigration properties as the metal conductor in lines and interconnections in semiconductor integrated circuits and in particular to the formation of conductors of such material in such integrated circuits within a dielectric material and with a self aligned metal capping layer.
The technology for interconnections that are to serve as vias, lines and other patterns and interconnects in integrated circuit and semiconductor chip structures is well developed in the art. In these structures multilevel wiring patterns are embedded in a dielectric material with wiring patterns and vias being separated by dielectric materials with different dielectric properties. Materials such as copper (Cu) are receiving attention in the art as having the potential of being able to improve performance by reducing conductor resistance. However; under the physical conditions of ever smaller dimension and increasing current, driven by the desire for increasing performance, the properties of diffusion and electromigration of such materials, are exhibiting difficult to solve contamination and leakage control problems and reliability issues.
Protective layers, commonly called by such terminology as “liners”, “barriers” or “caps” are being employed in efforts to limit outdiffusion and electromigration. However, any protective materials also have to have good adherence to the various other dielectric materials in the structure.
At the present state of the art; the problems are addressed, in one solution, by using, for copper conductor lines on a silicon substrate using silicon dioxide as the interconnect dielectric material, and the material silicon nitride as the cap material. However the presently relied on silicon nitride material, while having the desired high resistivity properties also has a relatively high dielectric constant of 7 to 8 which operates to increase the effective dielectric constant of the structure (Keff) and may also detrimentally affect the intralevel capacitance.
In another solution; also directed to the diffusion and electromigration problems for the material Cu, the desired results are achieved including the further ability to be able to select a capping material that maintains the desired low (Keff) established by the surrounding dielectric material. That technology is described in application Ser. No. 09/361,573 filed Jul. 27, 1999, of Hu et al, and is assigned to the assignee of this application. In that technology a self aligned metal cap is produced in a two step procedure involving Cobalt Tungsten Phosporous (CoWP) deposition. The deposited material covers and protects the top copper surface while achieving the desired adhesion in the structure and to serve as an impedance to electromigration.
As further progress in the art is sought, low dieletric constant (low k) intermetal dilectric materials appear to have the more promising properties
A need is present for a simpler procedural approach in integrated circuit technology wherein a conductor material such as Cu is protected from the effects of electromigration and diffusion yet can be positioned in a selectably low Keff dielectric structure.
In integrated circuit technology; a conductive element of an electromigration and diffusion sensitive metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the metal of the conductive element is positioned in a selectable K eff dielectric material. The metal is surrounded by a material having properties that resist diffusion of atoms out of the metal and serves as a source of a film thickness cap that is to form over the metal. The cap is to provide environmental protection and catalytic availability for use in further processing. The technology of the invention provides an intermediate conductive element product and method of manufacture that can be used as a wiring conductor or interconnect in many semiconductor integrated structures.
The conductive element is fabricated by forming an accommodating trench in a to be chemical-mechanical processed (CMP) interface surface, in a selectable, preferably (low K) dielectric. The trench is lined with a region made up of a layer or layers of a material or materials capable of controlling out diffusion from the metal into the preferably (low K) dielectric material and is further capable of providing a source for a diffusant that when diffused to the surface of the metal by an operation such as annealing forms a self aligned protective cap over the metal. The portion of the trench inside the lining is filled with the metal. An annealing temperature cycle is applied to the metal in the lined trench structure in forming the protective cap. The structure of the conductive element may then be planarized along the CMP planarization surface to residual remove any liner material and any excess metal material above the planar surface. The dielectric member can, if desired, be eroded away from the side away from the planar surface to expose the bottom of the trench for further contacting.
At the present state of the art, major sources of problems in the development of integrated circuits with diffusion and electromigration sensitive metals, such as copper, as wiring conductors and interconnects, are arising from contamination at the supporting dielectric interface by the diffusion out of the metal into the dielectric, and from reaction with other materials at the metal to next stage interface.
The functions of the region 16 are to provide an outdiffusion and electromigration inhibiting capability with respect to the conductor metal to be included in the trench 15 and to serve as a source of a diffusant element that is to later diffuse out of the region 16 through the to be provided conductor metal and then to serve as a self aligned cap thereover. The lining region layer 16 may be selected from the following:
For stacked liners A/B: A may be selected from W, Ta or Ti; their nitrides and silicides or combinations thereof and B may be selected from Pd, Rh, Co, Pt, Ir, Ru, and Ag where the thickness of the B layer is <100 A.
For alloy liners A(B) the above ingredient relationships hold and the proportion of B in the alloy is <75%. The total lining region element 16 thickness is in the range of about 30-300 angstroms for a line width spacing of about 0.1 micrometers.
In connection with
The intermediate product depicted in
What has been described is the technology of providing a diffusion and electromigration protected conductive element in a dielectric with a self aligned cap where the conductor in the dilectric is surrounded by a material that is resistant to out diffusion and serves as a source of a capping material that can diffuse to the cap position.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5604156 *||Nov 20, 1995||Feb 18, 1997||Samsung Electronics Co., Ltd.||Wire forming method for semiconductor device|
|US5674787 *||Jan 16, 1996||Oct 7, 1997||Sematech, Inc.||Selective electroless copper deposited interconnect plugs for ULSI applications|
|US5793112 *||Sep 18, 1996||Aug 11, 1998||Mitsubishi Denki Kabushiki Kaisha||Multilevel embedded wiring system|
|US6107687 *||Mar 16, 1998||Aug 22, 2000||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device having interconnection and adhesion layers|
|US6153935 *||Sep 30, 1999||Nov 28, 2000||International Business Machines Corporation||Dual etch stop/diffusion barrier for damascene interconnects|
|US6184138 *||Sep 7, 1999||Feb 6, 2001||Chartered Semiconductor Manufacturing Ltd.||Method to create a controllable and reproducible dual copper damascene structure|
|US6214728 *||Nov 20, 1998||Apr 10, 2001||Chartered Semiconductor Manufacturing, Ltd.||Method to encapsulate copper plug for interconnect metallization|
|US6251786 *||Sep 7, 1999||Jun 26, 2001||Chartered Semiconductor Manufacturing Ltd.||Method to create a copper dual damascene structure with less dishing and erosion|
|US6265779 *||Aug 11, 1998||Jul 24, 2001||International Business Machines Corporation||Method and material for integration of fuorine-containing low-k dielectrics|
|US6303505 *||Jul 9, 1998||Oct 16, 2001||Advanced Micro Devices, Inc.||Copper interconnect with improved electromigration resistance|
|US6358832 *||Aug 18, 2000||Mar 19, 2002||International Business Machines Corporation||Method of forming barrier layers for damascene interconnects|
|US6395607 *||Jun 9, 1999||May 28, 2002||Alliedsignal Inc.||Integrated circuit fabrication method for self-aligned copper diffusion barrier|
|US6515367 *||Apr 15, 2002||Feb 4, 2003||Advanced Micro Devices, Inc.||Sub-cap and method of manufacture therefor in integrated circuit capping layers|
|US6521523 *||Jun 15, 2001||Feb 18, 2003||Silicon Integrated Systems Corp.||Method for forming selective protection layers on copper interconnects|
|US6528409 *||Apr 29, 2002||Mar 4, 2003||Advanced Micro Devices, Inc.||Interconnect structure formed in porous dielectric material with minimized degradation and electromigration|
|US6627557 *||Mar 29, 2001||Sep 30, 2003||Kabushiki Kaisha Toshiba||Semiconductor device and method for manufacturing the same|
|US6645853 *||Dec 5, 2001||Nov 11, 2003||Advanced Micro Devices, Inc.||Interconnects with improved barrier layer adhesion|
|US6649522 *||Sep 18, 2002||Nov 18, 2003||Micron Technology, Inc.||Etch stop in damascene interconnect structure and method of making|
|US6723600 *||Apr 18, 2001||Apr 20, 2004||International Business Machines Corporation||Method for making a metal-insulator-metal capacitor using plate-through mask techniques|
|US6730594 *||Oct 25, 2002||May 4, 2004||Renesas Technology Corp.||Method for manufacturing semiconductor device|
|US6743310 *||Feb 22, 2002||Jun 1, 2004||Advanced Micro Devices, Inc.||Method of forming nitride capped Cu lines with improved adhesion and reduced electromigration along the Cu/nitride interface|
|US6753250 *||Jun 12, 2002||Jun 22, 2004||Novellus Systems, Inc.||Method of fabricating low dielectric constant dielectric films|
|US6764951 *||Feb 28, 2002||Jul 20, 2004||Advanced Micro Devices, Inc.||Method for forming nitride capped Cu lines with reduced hillock formation|
|US6790773 *||Aug 28, 2002||Sep 14, 2004||Novellus Systems, Inc.||Process for forming barrier/seed structures for integrated circuits|
|US6797145 *||Dec 9, 2002||Sep 28, 2004||Lex Kosowsky||Current carrying structure using voltage switchable dielectric material|
|US6797652 *||Mar 15, 2002||Sep 28, 2004||Advanced Micro Devices, Inc.||Copper damascene with low-k capping layer and improved electromigration reliability|
|US6815329 *||Apr 2, 2002||Nov 9, 2004||International Business Machines Corporation||Multilayer interconnect structure containing air gaps and method for making|
|US6831003 *||May 31, 2002||Dec 14, 2004||Advanced Micro Devices, Inc.||Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration|
|US6836017 *||Jan 20, 2004||Dec 28, 2004||Advanced Micro Devices, Inc.||Protection of low-k ILD during damascene processing with thin liner|
|US6841479 *||Apr 10, 2002||Jan 11, 2005||Cabot Microelectronics Corporation||Method of reducing in-trench smearing during polishing|
|US6849923 *||Mar 4, 2002||Feb 1, 2005||Kabushiki Kaisha Toshiba||Semiconductor device and manufacturing method of the same|
|US20010030366 *||Mar 7, 2001||Oct 18, 2001||Hiroshi Nakano||Semiconducting system and production method|
|US20020053741 *||Nov 6, 2001||May 9, 2002||Tomio Iwasaki||Semiconductor device and method for producing the same|
|US20020056879 *||May 3, 2001||May 16, 2002||Karsten Wieczorek||Field effect transistor with an improved gate contact and method of fabricating the same|
|US20020098681 *||Nov 13, 2001||Jul 25, 2002||Chao-Kun Hu||Reduced electromigration and stressed induced migration of Cu wires by surface coating|
|US20020132471 *||Mar 16, 2001||Sep 19, 2002||International Business Machines Corporation||High modulus film structure for enhanced electromigration resistance|
|US20020175362 *||Apr 11, 2000||Nov 28, 2002||Mcteer Allen||Use of ALN as copper passivation layer and thermal conductor|
|US20030001240 *||Jul 2, 2001||Jan 2, 2003||International Business Machiness Corporation||Semiconductor devices containing a discontinuous cap layer and methods for forming same|
|US20030087513 *||Oct 25, 2002||May 8, 2003||Junji Noguchi||Method for manufacturing semiconductor device|
|US20030111730 *||May 28, 2001||Jun 19, 2003||Kenichi Takeda||Semiconductor device and method manufacuring the same|
|US20030116439 *||Dec 21, 2001||Jun 26, 2003||International Business Machines Corporation||Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices|
|US20030134505 *||Jan 17, 2002||Jul 17, 2003||International Business Machines Corporation||Fine-pitch device lithography using a sacrificial hardmask|
|US20040084773 *||Oct 31, 2002||May 6, 2004||Johnston Steven W.||Forming a copper diffusion barrier|
|US20040113279 *||Dec 16, 2002||Jun 17, 2004||International Business Machines Corporation||Copper recess process with application to selective capping and electroless plating|
|US20040147117 *||Jan 20, 2004||Jul 29, 2004||Advanced Micro Devices, Inc.||Protection of low-k ILD during damascene processing with thin liner|
|US20040157425 *||Feb 3, 2004||Aug 12, 2004||Lsi Logic Corporation||Multi-step process for forming a barrier film for use in copper layer formation|
|US20040238965 *||Jun 29, 2004||Dec 2, 2004||Tomio Iwasaki||Semiconductor device and method for producing the same|
|US20050037604 *||Sep 24, 2004||Feb 17, 2005||International Business Machines Corporation||Multilayer interconnect structure containing air gaps and method for making|
|US20050082674 *||Nov 9, 2004||Apr 21, 2005||Kabushiki Kaisha Toshiba||Semiconductor device and manufacturing method of the same|
|US20050158985 *||Feb 16, 2005||Jul 21, 2005||Shyng-Tsong Chen||Copper recess process with application to selective capping and electroless plating|
|JP2000208511A *||Title not available|
|1||U.S. Appl. No. 09/361,573, filed Jul. 27, 1999, Hu et al., Titled Reduced Electromigration and Stressed Induced Migration of Cu Wires by Surface Coating.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7999391 *||Feb 6, 2007||Aug 16, 2011||Nec Corporation||Multilayered wiring structure, and method for manufacturing multilayered wiring|
|US9142456 *||Jul 30, 2013||Sep 22, 2015||Lam Research Corporation||Method for capping copper interconnect lines|
|US20100163834 *||Jun 30, 2009||Jul 1, 2010||Heon Yong Chang||Contact structure, method of manufacturing the same, phase changeable memory device having the same, and method of manufacturing phase changeable memory device|
|U.S. Classification||257/774, 257/522, 257/768, 257/E23.144, 257/762, 257/760, 257/276, 257/761, 257/E23.167, 257/767, 257/763, 257/764, 257/766, 257/734|
|International Classification||H01L23/532, H01L21/768|
|Cooperative Classification||H01L21/76843, H01L21/76874, H01L21/76838, H01L23/53238, H01L21/76849, H01L2924/3011, H01L21/76867, H01L21/76873, H01L2924/0002|
|European Classification||H01L21/768C3B, H01L21/768C3F, H01L21/768C, H01L21/768C3B8, H01L21/768C3S2, H01L23/532M1C4, H01L21/768C3S4|
|Dec 11, 2002||AS||Assignment|
Owner name: IBM CORPORATION, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHIRAS, STEFANIE R.;LANE, MICHAEL W.;MALHOTRA, SANDRA G.;AND OTHERS;REEL/FRAME:013584/0113;SIGNING DATES FROM 20021118 TO 20021209
Owner name: IBM CORPORATION, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHIRAS, STEFANIE R.;LANE, MICHAEL W.;MALHOTRA, SANDRA G.;AND OTHERS;SIGNING DATES FROM 20021118 TO 20021209;REEL/FRAME:013584/0113
|Jun 13, 2014||REMI||Maintenance fee reminder mailed|
|Oct 31, 2014||FPAY||Fee payment|
Year of fee payment: 4
|Oct 31, 2014||SULP||Surcharge for late payment|