|Publication number||US7839194 B2|
|Application number||US 12/256,422|
|Publication date||Nov 23, 2010|
|Priority date||Nov 21, 2007|
|Also published as||US20090128207|
|Publication number||12256422, 256422, US 7839194 B2, US 7839194B2, US-B2-7839194, US7839194 B2, US7839194B2|
|Inventors||Kun-Yung Chang, Ting Wu|
|Original Assignee||Rambus Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (35), Referenced by (11), Classifications (9), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to U.S. Provisional Ser. No. 60/989,750, filed Nov. 21, 2007, which is incorporated herein by reference in its entirety.
The disclosed embodiments relate generally to clock circuits. More particularly, the disclosed embodiments relate to duty cycle adjustment of a plurality of clocks which are time-multiplexed.
Clock circuits are useful because, typically, they provide synchronization and control signals to a system. Duty-cycle describes the ratio between the pulse duration (τ) and the period (T) of a rectangular waveform such as a clock signal. Duty-cycle of clock signals (for both transmitter and receiver) is important for the communication systems, including the Double Data Rate (DDR) memory interface. The duty-cycle of a clock signal can be adjusted and maintained by using a duty-cycle adjustment loop.
In an electronic integrated circuit (e.g., a memory device, memory controller or processor), if multiple clocks are present, there is typically an individual duty cycle adjustment circuit for each clock. The duty cycle adjustment circuit (excluding the clock generator) for a clock typically consumes considerable die area of the integrated circuit, and often much of this area is for the duty cycle detector circuit. Therefore the duty cycle adjustment circuits for multiple clocks consume or occupy correspondingly large amounts of die area of the integrated circuit.
Furthermore, in typical implementations it is desirable to make the duty-cycle adjustment circuit large to reduce transistor mismatch and improve accuracy. If multiple instances of the duty-cycle adjustment circuit are used on a die, they may be size limited to meet a size limitation on the die, which may limit accuracy of the duty-cycle adjustment circuits.
Various embodiments of the invention are disclosed in the following Description of Embodiments herein, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the figures.
In one aspect of the invention, clocking circuitry includes a first clock generator to generate a first clock signal and having a first duty cycle correction input, and a second clock generator to generate a second clock signal and having a second duty cycle correction input. Some embodiments have more than two clock generators. The circuitry also includes a duty cycle circuit to receive a clock input and to generate a duty cycle correction signal on an output of the duty cycle circuit. A multiplexer selects between the clock signals from the clock generators. The multiplexer has a first input coupled to the first clock signal and has a second input coupled to the second clock signal, and has a clock output coupled to a clock input of the duty cycle circuit.
In another aspect of the invention, clock circuitry includes a multiplexer having a first input and second input, a duty cycle circuit coupled to an output of the multiplexer, and a clock generator circuit. In some embodiments the multiplexer has more than two inputs, depending on the number of clock signals present. The duty cycle circuit generates a duty cycle correction signal for the clock signal selected by the multiplexer. The clock generator circuit includes a duty cycle shaping circuit, having an clock signal input and another input that is coupled to a correction signal output of the duty cycle circuit. The clock generator circuit also includes a transmit clock buffer and a receive clock buffer. The transmit clock buffer is coupled to the output of the duty cycle shaping circuit and has a transmit clock output coupled to the first input of the multiplexer. The receive clock buffer is coupled to the output of the duty cycle shaping circuit and has a receive clock output coupled to the second input of the multiplexer.
In another aspect of the invention, a method of adjusting the duty cycles of a plurality of clock signals is performed during distinct time periods for each clock signal of the plurality of clocks signals. During each of the distinct time periods, the following operations are performed. A respective clock signal of the plurality of clocks signals is provided to a duty cycle detector. An error signal is generated in response to an output of the duty cycle detector, and the duty cycle of the respective clock signal is adjusted in response to the error signal. In the method, the same duty cycle detector is used for processing all of the clock signals of the plurality of clock signals, in sequence, during the distinct time periods.
First clock generator 110 and second clock generator 120 each have an input coupled to a respective input clock signal 112 (ClockMixer1), 122 (ClockMixer2), and another input coupled to a respective output of a duty cycle correction circuit 142. Duty cycle correction signals 144, 146 produced by the duty cycle correction circuit 142 are coupled to the first and second clock generators. The first clock generator 110 uses the first input clock signal 112 and the first duty cycle correction signal 144 to generate a first output clock signal 114, and the second clock generator 120 uses the second input clock signal 122 and the second duty cycle correction signal 146 to generate a second output clock signal 124. Nth clock generator 130 has an input coupled to an nth input clock signal 132, and an input coupled to the duty cycle correction circuit 142. Nth clock generator 130 uses the Nth input clock signal and an Nth duty cycle correction signal 148 to generate a Nth output clock signal 134.
Circuitry 100 further includes a select control circuit 170. The select control circuit 170 receives a kickoff signal 178. When the select control circuit receives the kickoff signal 178, the select control circuit starts generating select signals which are provided to a multiplexer 140. The generated select signals include a first select signal 172, a second select signal 174, and an Nth select signal 176 respectively. In one embodiment, at any given time no more than one select signal is active.
Multiplexer 140 has N inputs coupled to the N clock output signals 114, 124, 134 respectively. Multiplexer 140 also has N select inputs coupled to select signals 172, 174, 176 respectively. Based upon the select input value, the multiplexer 140 selects the respective input clock and outputs it.
The duty cycle correction circuit 142 includes a duty cycle detector 150, which has an input coupled to the output of multiplexer 140. Thus, the clock signal selected by the multiplexer 140 in response to the select signals 172, 174, 176 is provided to the duty cycle detector 150. The duty cycle detector determines the duty cycle of the input clock, and generates a decision signal ‘DEC’, for instance ‘1’ when the duty-cycle of the input clock is more than 50% and ‘0’ when the duty-cycle less than 50%. In other embodiments, the decision signal may be made in response to other values. Duty cycle detector 150 has an input 152 which may in one embodiment be a program signal, or a reset signal, or another control signal, depending on the implementation. In one embodiment, the signal 152 may be used to reset the duty cycle detector each time that it begins to process a selected clock signal. In one embodiment, the signal 152 may be used to program a threshold or other parameter of the duty cycle detector 150 to a value specified by the signal 152.
The duty cycle correction circuit 142 also includes error accumulator 160, which has an input coupled to the decision output DEC of the duty cycle detector 150. According to the decision output, the error accumulator 160 generates control bits for the duty-cycle of the respective clock which is coupled to the duty cycle detector through the multiplexer 140. The control bits are provided to the respective clock and are used to adjust the duty cycle of that clock in the respective clock generator 110, 120, 130. The error accumulator 160 receives an input signal 162 which may in one embodiment be a program signal, or a reset signal, or another control signal, depending on the implementation. In one embodiment, the signal 162 may be used to reset the error accumulator 160. In some embodiments, the signal 162 may be used to program a parameter of the error accumulator 160 to a value specified by the signal 162.
Thus, when the select control circuit 170 enables first select signal 172, this causes the multiplexer 140 to provide first clock signal 114 to the duty cycle detector 150 and error accumulator 160. The error accumulator 160 provides control bits (e.g., a cumulative duty cycle error value) to register 180 enabled by a select signal 172 which then provides the control bits to first clock generator 110 to adjust the duty cycle of first clock 114. Similarly, control signal 174 controls the selection of the second clock 124 and the storage of control bits in register 182, and control signal 176 controls the selection of the Nth clock and the storage of control bits in the register 184.
In one embodiment, registers 180, 182 and 184 may be individual registers. In some embodiments, registers 180, 182 and 184 are part of the error accumulator 160. Alternately, registers 180, 182 and 184 are part of the respective clock generator circuits 110, 120, 130. In yet other embodiments, registers 180, 182 and 184 are placed in different circuit locations than stated above, or in any mix of the above locations.
The error accumulator 232 generates a control value (e.g., a duty cycle correction value) that it stores in register bank 236. The register bank 236 has a plurality of registers, including a distinct register for each of the clocks whose duty cycle is to be adjusted by the multiplexed duty cycle correction circuit 240. In one embodiment the registers may be grouped according to which clock signal they correspond to. In one embodiment the register in which the control value produced by error accumulator 232 is stored is controlled by select control 170, and corresponds to the clock selected by multiplexer 140 in response to select signal 170.
Multiplexer circuit 300 includes a second clock path comprising second clock signal 124, NAND gate 320, NAND gate 322 and second transistor 324, and is controlled by second select signal 174. Multiplexer circuit 300 further includes an Nth clock path comprising Nth clock signal 134, NAND gate 330, NAND gate 332 and Nth transistor 324, and is controlled by Nth select signal 176. The second clock path and Nth clock path operate in the same manner as the first clock path. The second clock path selectively passes second clock signal 124 to the multiplexer output only when the second select signal 174 is active, and the Nth clock path selectively passes Nth clock signal 124 to the multiplexer output only when the Nth select signal 176 is active.
Shift register circuit 420 operates in the following manner. When the Kickoff signal goes active, a logic high value is stored in first register, and all other registers in the shift register circuit store a logic low value. Then, on each rising edge of the shift register clock signal 430, the logic high value is propagated through the shift register, and thus enables (e.g. logic high) each select signal in turn while keeping all other select signals at disabled (e.g. logic low). In other embodiments using active low logic, the sets and resets could be reversed while maintaining functionality.
The reset signal 432 produced by pulse generator 550 can be used to reset the multiplexed duty cycle circuitry 142 each time it starts processing a newly selected clock signal. In some embodiments, the reset signal 432 produced by the pulse generator 550 is a pulse having a predefined duration that is much shorter than (e.g., less than one percent of) the period of time used to check and adjust the duty cycle of a selected clock signal.
Count filter 610 receives as inputs the current value signal 622, a count enable signal 604 indicating the occurrence of an incremental error voltage passing a threshold voltage to generate an incremental error signal, an up/down signal 602 indicating whether the error was positive or negative, and a filter information signal 606 providing status information. Count filter 610 generates the next value signal 612, which represents the filtered incremental error signal and outputs it to count register 620, which outputs the accumulated error signal (also called the current value signal 622).
The first select register 640 receives as an input a first select signal 172 as described earlier, and generates an output 644 representing the accumulated error corresponding to the first clock and the first select signal 172. Similarly, the second select register 650 generates an output 654 corresponding to the second clock and the second select signal 174, and the Nth select register generates an output 664 corresponding to the Nth clock and the Nth select signal 176.
Devices and circuits described herein can be implemented using computer aided design tools available in the art, and embodied by computer readable files containing software descriptions of such circuits, at behavioral, register transfer, logic component, transistor and layout geometry level descriptions stored on storage media or communicated by carrier waves. Data formats in which such descriptions can be implemented include, but are not limited to, formats supporting behavioral languages like C, formats supporting register transfer level RTL languages like Verilog and VHDL, and formats supporting geometry description languages like GDSII, GDSIII, GDSIV, CIF, MEBES and other suitable formats and languages. Data transfers of such files on machine readable media can be performed electronically over the diverse media on the Internet or through email, for example. Physical files can be implemented on machine readable storage media such as 4 mm magnetic tape, 8 mm magnetic tape, 3½ inch floppy media, CDs, DVDs, flash memory devices, and so on.
The foregoing descriptions of specific embodiments of the present embodiments are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Rather, it should be appreciated that many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated.
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|U.S. Classification||327/175, 327/172|
|Cooperative Classification||H03K5/1565, G06F1/06, G06F1/12|
|European Classification||G06F1/06, G06F1/12, H03K5/156D|
|Oct 19, 2010||AS||Assignment|
Owner name: RAMBUS INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, KUN-YUNG;WU, TING;SIGNING DATES FROM 20100823 TO 20101016;REEL/FRAME:025163/0185
|May 23, 2014||FPAY||Fee payment|
Year of fee payment: 4