|Publication number||US7842528 B2|
|Application number||US 12/254,560|
|Publication date||Nov 30, 2010|
|Filing date||Oct 20, 2008|
|Priority date||Oct 23, 2007|
|Also published as||CN101419945A, CN101419945B, US8048697, US20090111198, US20110065221|
|Publication number||12254560, 254560, US 7842528 B2, US 7842528B2, US-B2-7842528, US7842528 B2, US7842528B2|
|Inventors||Saishi Fujikawa, Kunio Hosoya, Yoko Chiba|
|Original Assignee||Semiconductor Energy Laboratory Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (26), Referenced by (11), Classifications (24), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a semiconductor device which has a circuit including a thin film transistor formed using a semiconductor film, and also relates to a manufacturing method thereof. Further, the present invention relates to a display device and a manufacturing method thereof.
2. Description of the Related Art
Display devices are widely spread as displays of televisions and personal computers, cellular phones, and the like, in many of which a liquid crystal display device which uses a thin film transistor including an amorphous silicon (hereinafter, referred to as an amorphous silicon TFT) as a switching element is used. The amorphous silicon TFT is conventionally formed over a glass substrate by a known photolithography process using five photomasks as disclosed in Patent Document 1.
Five photomasks described here include a first photomask for forming a gate electrode, a second photomask for separating a semiconductor layer, a third photomask for forming a source electrode and a drain electrode, a fourth photomask for providing an opening in a protective insulating film, and a fifth photomask for forming a pixel electrode.
[Patent Document 1] Japanese Published Patent Application No. 2001-53283.
A photolithography process using photomasks includes an application of photoresist, a prebake, a light exposure process using a photomask, a development process, a rinse process, a postbake process, an etching process, a resist removal process, and the like. In addition, multiple processes, for example, a cleaning process and an inspecting process, are included. Since such multiple processes are needed, a great deal of cost and time is needed to conduct one photolithography process.
Since a liquid crystal display has been improved in resolution and viewing angle, a pixel structure tends to be smaller, and a pattern which forms a pixel tends to be thinner. Accordingly, more advanced precision in a manufacturing process is needed. In particular, as the pattern which is formed using photomasks becomes more precise, a misalignment between photomasks brings larger effect on yield than ever.
The present invention provides a semiconductor device for which can reduce the number of photomasks and a manufacturing method thereof to solve the above-described problems.
The present invention relates to a semiconductor device which is formed using four or three photomasks in total and a backside light exposure technique to reduce the number of processes of conventional five-photomask process and a manufacturing method thereof.
A feature of the present invention is that a stacked layer of a transparent conductive layer and a metal layer is used as a first conductive layer, and the first conductive layer is used as a gate electrode and a pixel electrode by using a first multi-tone mask.
Further, in the present invention, a formation of a contact hole and a processing of a semiconductor layer are conducted by using a second multi-tone mask.
Furthermore, in the present invention, one photomask is eliminated by using a backside light exposure and a reflow technique. Note that a semiconductor device and a manufacturing method thereof of the present invention can be applied to manufacturing an EL display device.
By the present invention, advantageous effects described below can be realized.
By reducing the number of photomasks compared to that in the conventional manufacturing method which uses five photomasks, the number of alignments of photomasks is reduced, and reduction in yield caused by misalignment with another photomask is suppressed.
Further, by reducing the number of photomasks, a part of photolithography process can be omitted; therefore, manufacturing cost can be reduced and throughput can be improved.
Furthermore, by omitting a part of photolithography process, contamination (e.g., particle) which may be generated in the process can be prevented. Thus, yield and reliability are improved.
An object of the present invention is to reduce the number of photomasks in a manufacturing process of a semiconductor device. That is, by manufacturing a semiconductor device using a process of the present invention, time and cost for the process can be reduced. Although a conventional amorphous silicon TFT is generally manufactured using five photomasks, it is possible to manufacture a TFT using three photomasks or four photomasks, and reduce time and cost for manufacturing the TFT by the present invention.
Further, reliability of elements can be improved by covering the TFT with an insulating film completely. When a surface of a channel portion is exposed, impurities from the substrate and ambient atmosphere, such as boron and phosphorus, enter the channel portion. These may serve as donors, so off leakage current of TFT is increased and an adverse effect that threshold voltage of TFT is changed is expected. However, by covering the TFT with an insulating film completely, that effect can be suppressed. A protective film performs a function of preventing the source electrode and the drain electrode from oxidizing when the TFT is a bottom gate type. On the other hand, the protective film performs a function of preventing the gate electrode from oxidizing when the TFT is a top gate type.
Furthermore, in the present invention, a pixel electrode is positioned below the protective insulating film and a gate insulating film and at a bottom surface of an opening region whereas a conventional pixel electrode is formed in the top layer of stacked layers. Therefore, the gate insulating film and the protective insulating film function as partitions, and interaction of field effects between neighboring pixel electrodes is decreased, thereby suppressing crosstalk. In addition, only the protective film is formed as an interlayer film between the pixel electrode and a signal line conventionally. However, in the present invention, a gate protective film is also provided, so parasitic capacitance between a signal line and a pixel electrode can be reduced.
Hereinafter, embodiment modes of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention can be implemented with various modes. It is easily understood by those skilled in the art that the mode and the detail can be variously changed without departing from the scope and spirit of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiment modes.
Description is made using a liquid crystal display device which is one mode of display modes.
An inverted staggered TFT of the present invention, which is formed using four photomasks is illustrated in
Alternatively, since the transparent conductive layer 101 is formed below the metal layer 102 in a structure of the present invention, only the metal layer 102 can be formed by a sputtering method using a commercially available glass substrate provided with ITO.
As for a material of the transparent conductive layer 101, ITO (indium tin oxide) is used. A part of the transparent conductive layer 101 is to be a pixel electrode later. On the other hand, the metal layer 102 is preferably formed using a low resistant metal material such as aluminum since it is to be mainly an electrode or a wiring. Alternatively, a stacked structure with aluminum interposed between barrier layers using refractory metal and in which refractory metal is used as a barrier layer may be employed. For example, the following combination can be considered: the first layer is formed of molybdenum (Mo), the second layer is formed of aluminum (Al), and the third layer is formed of molybdenum (Mo); the first layer is formed of titanium (Ti), the second layer is formed of aluminum (Al), and the third layer is formed of titanium (Ti); the first layer is formed of molybdenum (Mo), the second layer is formed of aluminum (Al) containing a slight amount of neodymium (Nd), and the third layer is formed of molybdenum (Mo); and the like. In this manner, when the metal layer 102 has a stacked structure, formation of a hillock on aluminum can be suppressed.
Note that a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like may be formed as a base film between the substrate 100 and the transparent conductive layer 101 although not illustrated in diagrams. By forming the base film, diffusion of mobile ions, impurities, and the like from a glass substrate into an element can be suppressed, which is effective to prevent characteristic deterioration of the element.
As for a normal photomask, a pattern is formed of metal over a substrate which transmits light. Therefore, the pattern formed of metal serves as a light blocking portion. In addition, a portion where the pattern formed of metal is not formed serves as a transmissive portion. Note that the normal photomask has the transmittive portion and the light blocking portion. On the other hand, the multi-tone mask has a semi-transmissive portion in addition to them. Methods for forming the semi-transmissive portion are classified into a half-tone light exposure technique and a gray-tone light exposure technique.
A semi transmission is realized using the gray-tone light exposure technique by forming a slit equal to or smaller than the resolution in a transmissive portion, and blocking light partially by the slit. On the other hand, the semi transmission is realized using the half-tone light exposure technique by forming a semi-transmissive film in a semi-transmissive portion. The photoresist exposed through such a multi-tone mask is divided into an exposed portion, a semi-exposed portion, and an unexposed portion. When the semi-exposed portion of the photoresist is developed, the thickness of the photoresist is to be intermediate between the thickness of the exposed portion of the photoresist and the thickness of the unexposed portion of the photoresist.
Note that photoresists can be classified into a positive type and a negative type. If a positive photoresist is used, the exposed portion of the photoresist is removed, and the unexposed portion of the photoresist remains when developed. On the other hand, if a negative photoresist is used, the exposed portion of the photoresist remains, and the unexposed portion of the photoresist is removed. The positive type is preferable in terms of resolution, but it is needless to say that the pattern can be formed even if the negative type is used. Embodiment modes of the present invention are described using the positive photoresist.
The first multi-tone mask 201 includes a light blocking portion 201 a and a semi-transmissive portion 201 b, and the photoresist 103 which is developed has two different thicknesses. In a portion where the first conductive layer is made to remain, the first multi-tone mask 201 is designed so that the photoresist 103 is thick. On the other hand, in a portion where only the transparent conductive layer 101 is used, the first multi-tone mask 201 is designed so that the photoresist 103 b is thin. Here, the photoresist 103 a which is thick is formed in portions which are to be a gate electrode, a lower electrode of storage capacitor, and a wiring of terminal connection portion later. On the other hand, the photoresist 103 b which is thin is formed in portions which are to be the pixel electrode and the contact hole of the terminal connection portion later.
The first conductive layer is etched using the photoresist 103 a and the photoresist 103 b as resist masks. Methods for etching are classified into a dry etching method performed in a gas phase and a wet etching method performed in a liquid phase, and either of the methods may be used in this case.
Then, ashing is conducted on the photoresist 103. That is, as shown in
In a case where only the metal layer 102 is removed by wet etching whereas the transparent conductive layer 101 is left, an etchant of high selection ratio between the transparent conductive layer and the metal layer is used. In a case where a stacked layer in which the first layer is formed of molybdenum (Mo), the second layer is formed of aluminum (Al), and the third layer is formed of molybdenum (Mo); the first layer is formed of molybdenum (Mo), the second layer is formed of aluminum (Al) containing a slight amount of neodymium (Nd), and the third layer is formed of molybdenum (Mo); or the like is used as the metal layer 102, for example, mixed acid formed of phosphoric acid, nitric acid, acetic acid, and water can be used. Further, if the mixed acid is used, forward tapered shape which is uniform and favorable can be given. In this manner, the wet etching is a simple process in which an etching by an etchant, a rinse by pure water, and drying are performed whereas the throughput is high in addition to an improvement in coverage due to a tapered shape. Thus, a wet etching is suitable for etching of the above metal layer.
Then, as illustrated in
Note that the interface between the gate insulating film 109 and the i-type semiconductor layer 110 is needed to be controlled to stabilize the characteristics of TFT. In addition, the interface between the i-type semiconductor layer 110 and the n+ type semiconductor layer 111 is needed to obtain a favorable ohmic contact. Thus, it is preferable that successive film formation from the gate insulating film 109 to the n+ type semiconductor layer 111 are conducted by using a multi-chamber CVD apparatus while maintaining a vacuum state. In a case where the gate insulating film 109 has a stacked structure, successive film formation may be conducted while exposure to the atmosphere from the gate insulating film which is near to the i-type semiconductor layer 110 is not performed.
Then, as illustrated in
Dry etching is performed using the photoresist 112 as a resist mask. As a result, as illustrated in
Then, the photoresist 112 is ashed, and a photoresist 114 is formed. In this manner, by using a multi-tone mask, the photoresist 114 can be formed without using an additional photomask. The i-type semiconductor layer 110 and the n+ type semiconductor layer 111 are processed using the photoresist 114 as a resist mask. This process can be performed by an RIE type dry etching method using CF4 and O2, or SF6 and O2.
Then, a second conductive layer 116 is formed by a sputtering method, and a photoresist 117 is formed using a third photomask (not shown), which is illustrated in
Further, the n+ type semiconductor layer 111 is separated by dry etching using the photoresist 117 as a mask. Parts of the n+ type semiconductor layer, which are separated, form a source region 121 and a drain region 122.
When the source electrode 118 and the drain electrode 119 are etched by wet etching in this state, a step shape in which edge portions of the source electrode 118 and the drain electrode 119 are recessed than edge portions of the source region 121 and the drain region 122 is formed. Thus, effects that coverage with a protective insulating film 123 which is described later is improved and unnecessary parasitic capacitance which is generated between the gate electrode 107, and the source electrode 118 and the drain electrode 119 is reduced can be obtained without increasing the number of photomasks. Note that a shape other than a step shape can be formed by dry etching.
After the photoresist 117 which is used is removed by stripping, the protective insulating film 123 is deposited as illustrated in
In addition, a counter electrode 504 which is formed of a transparent conductive layer is formed so that an electric field is formed between the pixel electrode 105 and the counter electrode 504. A spacer 505 is formed to maintain a space between the substrates. A liquid crystal 510 is interposed between the counter substrate 500 and the substrate 100 over which the TFT is formed, and a sealing material 506 surrounds a periphery of the substrates and attaches a pair of substrates, thereby sealing the liquid crystal 510 between the substrates. Further, alignment films (not shown) are formed on surfaces which are in contact with the liquid crystal of the substrates. Here, a planarizing film 503 formed of organic resin is formed between the color filter 502 and the counter electrode 504 so that a space between the counter electrode 504 and the pixel electrode 105 is kept constant, thereby preventing uneven electric field due to unevenness of the electrode from being generated.
A terminal connection portion for an external circuit is formed in an edge portion of the substrate 100 over which the TFT is formed. A wiring 127 for the terminal connection portion which is connected to the pixel TFT can be formed using the first conductive layer. In addition, the contact hole 126 which is formed in the wiring 127 is filled with a resin adhesive 508 containing a conductive particle 507, and is electrically connected to an FPC 509 connecting to an external circuit. Note that the wiring 127 can be also formed as a wiring 128 which uses the second conductive layer as illustrated in
In this manner, by using the present invention, an active matrix substrate which includes a terminal connection portion connecting to an external circuit can be formed by a four-photomask process. Note that in this embodiment mode, an example of manufacturing a liquid crystal display device of
Here, a reflow treatment is a method for changing a shape of the photoresist by performing heat treatment or exposing to the vapor of organic solevant.
Note that it is needless to say that in a case where this embodiment mode is used, the terminal connection portion connecting to an external terminal can be formed as in Embodiment Mode 1.
In this manner, by using the present invention, an active matrix substrate which includes a terminal connection portion connecting to an external circuit can be formed using three photomasks. Note that in this embodiment mode, the same materials as those used in Embodiment Mode 1 can be used.
A process using three photomasks of a top gate type TFT using the present invention is described.
First, in the same manner as
Furthermore, after an i-type semiconductor layer 812 is formed over the entire surface of the substrate, a photoresist 813 is formed only in an upper portion of the pixel electrode using a normal photomask, and the n+ type semiconductor layer 808 and the i-type semiconductor layer 812 are processed to obtain a shape as
Then, a gate insulating film 814 and a conductive layer 815 are formed. In addition, a photoresist 816 which has two different thicknesses is formed using a multi-tone light exposure technique. In
Thereafter, the conductive layer 815 is etched using the photoresist 817, and a gate electrode 819 is formed. Then, a protective insulating film 818 is formed over the entire surface of the substrate, a photoresist is formed by a backside light exposure, and an opening region is formed by etching after the reflow treatment of the photoresist (FIG. 9C).
An example of a TFT using a microcrystalline semiconductor layer is shown in this embodiment mode whereas a TFT using an amorphous semiconductor layer is shown in Embodiment Mode 1.
The microcrystalline semiconductor layer 110 a serves as a channel. The microcrystalline semiconductor layer 110 a can be formed by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of megahertz or a microwave plasma CVD apparatus with a frequency of 1 GHz or more. The microcrystalline semiconductor layer 110 a can be typically formed using silicon hydride, such as SiH4 or Si2H6, which is diluted with hydrogen. With a dilution with one or plural kinds of rare gas elements selected from helium, argon, krypton, and neon in addition to silicon hydride and hydrogen, the microcrystalline semiconductor film can be formed. In that case, the flow rate ratio of hydrogen to silicon hydride is set to be 5:1 to 200:1, preferably, 50:1 to 150:1, more preferably, 100:1. Note that, in place of silicon hydride, SiH2CI2, SiHCl3, SiCl4, SiF4, or the like can be used. On the other hand, as for the amorphous semiconductor layer 110 b, the i-type semiconductor layer 110 shown in Embodiment Mode 1 may be used, which serves as a buffer layer to reduce off current of TFT, prevent oxidation of the microcrystalline semiconductor layer 110 a, form the source region or the drain region, and the like.
Alternatively, an n+ type microcrystalline semiconductor layer (not shown) can be used in place of the n+ type semiconductor layer 111 of Embodiment Mode 1. An improvement in on current can be realized because the parasitic resistance between the channel and source electrode or drain electrode can be suppressed.
Semiconductor devices and electronic devices according to the present invention include a television, a camera such as a video camera or a digital camera, a goggle-type display (a bead mounted display), a navigation system, a sound reproduction system (such as a car audio system, audio components), a notebook personal computer, a game machine, a portable information terminal (such as a mobile computer, a cellular phone, a portable game machine, or an electronic book reader), and an image reproducing device provided with a recording medium (specifically, a system provided with a display that can reproduce content of a recording medium such as a digital versatile disc (DVD) and display the image). Specific examples of those electronic devices are shown in
A cellular phone 3000 shown in
The specifications of the display panel (A) 3008 and the display panel (B) 3009 such as the number of pixels can be appropriately set in accordance with the function of the cellular phone 3000. For example, the display panel (A) 3008 and the display panel (B) 3009 can be used in combination so as to be used as a main display screen and a sub-display screen, respectively.
A potable information terminal which has a more inexpensive display portion and high reliability can be realized by the present invention.
The cellular phone 3000 according to this embodiment mode can be changed in various modes in accordance with the functions or applications thereof. For example, by incorporating an imaging element into the hinge 3010, a cellular phone equipped with a camera can be provided. In addition, also in a case where the operation switches 3004, the display panel (A) 3008, and the display panel (B) 3009 are incorporated into one chassis, the effect described above can be obtained. Further, a similar effect can be obtained when the structure of this embodiment mode is applied to an information display terminal provided with a plurality of display portions.
As described above, by carrying out the present invention, that is, by using any one of the manufacturing methods in Embodiment Modes 1 to 4, various electronic devices can be completed.
This application is based on Japanese Patent Application Serial No. 2007-275782 filed with Japan Patent Office on Oct. 23, 2007, the entire contents of which are hereby incorporated by reference.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6008065||Nov 21, 1996||Dec 28, 1999||Samsung Electronics Co., Ltd.||Method for manufacturing a liquid crystal display|
|US6485997||Dec 15, 2000||Nov 26, 2002||Hyundai Display Technology, Inc.||Method for manufacturing fringe field switching mode liquid crystal display device|
|US6493048 *||Oct 20, 1999||Dec 10, 2002||Samsung Electronics Co., Ltd.||Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same|
|US6635581||Apr 11, 2002||Oct 21, 2003||Au Optronics, Corp.||Method for forming a thin-film transistor|
|US7599014||May 31, 2006||Oct 6, 2009||Au Optronics Corp.||Method for fabricating pixel array substrate|
|US20010007779||Dec 15, 2000||Jul 12, 2001||Kyung Ha Lee||Method for manufacturing fringe field switching mode liquid crystal display device|
|US20050263768 *||May 26, 2005||Dec 1, 2005||Lg. Philips Lcd Co., Ltd.||Liquid crystal display device and fabricating method thereof|
|US20050270434 *||Jun 3, 2005||Dec 8, 2005||Jung Tae Y||Liquid crystal display device and fabricating method thereof|
|US20060290867 *||Jun 21, 2006||Dec 28, 2006||Ahn Byung C||Liquid crystal display and fabricating method thereof|
|US20070002249||Jun 21, 2006||Jan 4, 2007||Yoo Soon S||Liquid crystal display device and fabricating method thereof|
|US20070126969||Dec 1, 2006||Jun 7, 2007||Semiconductor Energy Laboratory Co., Ltd.||Liquid crystal display device|
|US20070146591||Dec 1, 2006||Jun 28, 2007||Semiconductor Energy Laboratory Co., Ltd.||Liquid crystal display device|
|US20070222936 *||May 31, 2006||Sep 27, 2007||Ming-Hung Shih||Method for fabricating pixel array substrate|
|US20090033818||Aug 27, 2008||Feb 5, 2009||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor Device and Method of Manufacturing the Semiconductor Device|
|US20090101906||Oct 20, 2008||Apr 23, 2009||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and method for manufacturing semiconductor device|
|US20090104723||Oct 20, 2008||Apr 23, 2009||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing display device|
|US20090108260 *||Mar 21, 2008||Apr 30, 2009||Au Optroncs Corp.||Pixel structure and method for manufacturing the same|
|US20090117691||Oct 21, 2008||May 7, 2009||Semiconductor Energy Laboratory Co., Ltd.||Method of manufacturing semiconductor device|
|US20090148970||Oct 21, 2008||Jun 11, 2009||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device|
|JP2001053283A||Title not available|
|JP2001235763A||Title not available|
|JP2007011340A||Title not available|
|JP2007011343A||Title not available|
|JP2007183583A||Title not available|
|JP2007183585A||Title not available|
|JP2007243144A||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7993991||Dec 2, 2008||Aug 9, 2011||Semiconductor Energy Laboratory Co., Ltd.||Manufacturing method of thin film transistor and manufacturing method of display device|
|US8101442||Feb 20, 2009||Jan 24, 2012||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing EL display device|
|US8148730||Oct 20, 2008||Apr 3, 2012||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and method for manufacturing semiconductor device|
|US8486773||Jun 29, 2011||Jul 16, 2013||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US8518762||Jun 29, 2011||Aug 27, 2013||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US9006050||Feb 17, 2012||Apr 14, 2015||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and method for manufacturing semiconductor device|
|US9153537||Jul 15, 2013||Oct 6, 2015||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US9620525||Nov 17, 2015||Apr 11, 2017||Semiconductor Energy Laboratory Co., Ltd.||Liquid crystal display device and electronic device|
|US20090101906 *||Oct 20, 2008||Apr 23, 2009||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and method for manufacturing semiconductor device|
|US20090152559 *||Dec 2, 2008||Jun 18, 2009||Semiconductor Energy Laboratory Co., Ltd.||Manufacturing method of thin film transistor and manufacturing method of display device|
|US20090224249 *||Feb 20, 2009||Sep 10, 2009||Semiconductor Energy Laboratory Co., Ltd.||Method For Manufacturing EL Display Device|
|U.S. Classification||438/30, 257/E21.415, 438/155, 257/72, 438/698|
|International Classification||H01L21/00, G09F9/30, H01L29/786, H01L21/336|
|Cooperative Classification||H01L27/1288, G02F2001/13606, G02F2001/136231, G02F2001/136236, G02F2001/13625, G02F2201/50, H01L21/0273, H01L21/31144, H01L21/32139, H01L27/1214|
|European Classification||H01L21/3213D, H01L21/311D, H01L21/027B6, H01L27/12, H01L27/12T|
|Dec 18, 2008||AS||Assignment|
Owner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUJIKAWA, SAISHI;HOSOYA, KUNIO;CHIBA, YOKO;REEL/FRAME:022002/0355;SIGNING DATES FROM 20081120 TO 20081125
Owner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUJIKAWA, SAISHI;HOSOYA, KUNIO;CHIBA, YOKO;SIGNING DATESFROM 20081120 TO 20081125;REEL/FRAME:022002/0355
|Apr 30, 2014||FPAY||Fee payment|
Year of fee payment: 4