|Publication number||US7843050 B2|
|Application number||US 11/863,425|
|Publication date||Nov 30, 2010|
|Filing date||Sep 28, 2007|
|Priority date||Jul 24, 2007|
|Also published as||CN101755336A, CN101755336B, EP2176885A1, US8198720, US8536702, US20090026600, US20110068454, US20120241957, WO2009014989A1|
|Publication number||11863425, 863425, US 7843050 B2, US 7843050B2, US-B2-7843050, US7843050 B2, US7843050B2|
|Inventors||Meow Koon Eng, Yong Poo Chia, Suan Jeung Boon|
|Original Assignee||Micron Technology, Inc.|
|Patent Citations (105), Non-Patent Citations (4), Referenced by (5), Classifications (21), Legal Events (1) |
|External Links: USPTO, USPTO Assignment, Espacenet|
Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US 7843050 B2
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.
1. A stacked system of microelectronic die packages, comprising:
a first die package having a bottom side and including a first microelectronic die, a first dielectric casing at least partially covering the first die and defining at least a portion of the bottom side, and individual first metal leads coupled to the first die and having a first exterior surface;
a second die package having a top side attached directly to the bottom side of the first package with an adhesive layer, the second die package including a second microelectronic die, a second dielectric casing at least partially covering the second die and defining at least a portion of the top side and a lateral side, and individual second metal leads coupled to the second die and having a second exterior surface and an interior surface region that generally faces the lateral side, wherein the individual second leads are at least generally aligned with the individual first leads and project, at least in part, towards the first package; and
external inter-package connectors coupling a first portion of individual first exterior surfaces with a second portion of individual second exterior surfaces.
2. The stacked system of claim 1 wherein the individual second leads have an L-shape and physically contact corresponding individual first leads.
3. The stacked system of claim 1 wherein the individual second leads have a C-shape and include a tiered portion that projects towards the lateral side of the second casing.
4. The stacked system of claim 1 wherein the individual second leads are coupled to a bottom side of the second casing.
5. The stacked system of claim 1 wherein a bottom side of the second die package further includes package bonds that are coupled to metal bump pads associated with an interposer substrate.
6. The stacked system of claim 1 wherein the connectors project laterally outward from the first portion of the first exterior surfaces and the second portion of the second exterior surfaces.
7. The stacked system of claim 6 wherein the connectors further extend in between the first and second die packages, towards the lateral side of the second casing.
8. The stacked system of claim 1 wherein the lateral side of the second casing has a sloped profile and the interior surface regions of the leads are spaced apart from the lateral side by a gap.
9. The stacked system of claim 1 wherein the individual second leads of the second die package are separated from corresponding individual first leads of the first die package by vertical gaps, and wherein individual connectors comprise solder links that bridge the vertical gaps between corresponding pairs of first and second leads.
10. The stacked system of claim 1 wherein the first die has a first lateral dimension and the second die has a second lateral dimension different than the first lateral dimension, and wherein the first and second casings have equal lateral dimensions.
11. A computing system, comprising at least one of a processor, a memory, and an input/output device, wherein the computing system includes the stacked system according to claim 1.
12. A stacked system of microelectronic die packages, comprising:
a first microelectronic die package including a first dielectric casing having a first bottom side and first metal leads attached to the first bottom side;
a second microelectronic die package having a top side attached directly to the bottom side with an adhesive layer, the second microelectronic die package including a second dielectric casing defining at least a portion of the top side, a lateral side, a second bottom side, the second microelectronic die package further including second metal leads coupled to the second bottom side, wherein individual second leads include a lateral portion that projects away from the lateral side, a bend, and an angled portion that projects from the bend towards a corresponding individual first lead; and
metal solder connectors attached to the individual first leads and a surface of individual angled portions of the second leads.
13. The stacked system of claim 12 wherein the angled portion is substantially sloped inward towards the lateral side of the second casing, and wherein the second leads directly contact corresponding first leads.
14. The stacked system of claim 12 wherein individual metal solder connectors attach individual angled portions to a surface of a corresponding first lead.
15. A stacked system of microelectronic devices, comprising:
a first microelectronic device having a first bottom side at least partially defined by a first dielectric casing and first metal leads coupled to the first bottom side;
a second microelectronic device having a second dielectric casing at least partially defining a top side, a lateral side, and a second bottom side, wherein the top side is attached directly to the first bottom side with an adhesive layer, and wherein the second microelectronic device further includes second metal leads coupled to the second bottom side, the second leads including a lateral portion that laterally projects away from the lateral side, a tiered portion that laterally projects towards the lateral side, and an angled portion between the lateral portion and the tiered portion that positions the tiered portion above the lateral portion; and
metal solder bumps between individual first leads and individual tiered portions of the second leads.
16. The stacked system of claim 15 wherein the metal solder bumps are further attached to the individual second leads of the second microelectronic device at a surface of the angled portion that generally faces away from the lateral side of the second casing.
17. The stacked system of claim 15 wherein the tiered portion is separated from a corresponding first lead by a vertical distance of up to 60 microns.
18. The stacked system of claim 15 wherein the angled portion is substantially perpendicular to the lateral portion.
CROSS-REFERENCE TO RELATED APPLICATION
This application claims foreign priority benefits of Singapore Application No. 200705422-4 filed Jul. 24, 2007, which is incorporated herein by reference in its entirety.
The present disclosure is directed generally to microelectronic die packages with metal leads, and more particularly to metal leads configured for stacked die packages.
Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic die mounted to a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and interconnecting circuitry. The die also typically includes bond pads electrically coupled to the functional features. The bond pads are electrically connected to pins or other types of terminals that extend outside the protective covering for connecting the die to busses, circuits, or other microelectronic assemblies.
In one conventional arrangement, the die is mounted to a supporting substrate (e.g., a printed circuit board), and the die bond pads are electrically coupled to corresponding bond pads of the substrate with wirebonds. After encapsulation, the substrate can be electrically connected to external devices with solder balls or other suitable connections. Accordingly, the substrate supports the die and provides an electrical link between the die and the external devices.
In other conventional arrangements, the die can be mounted to a lead frame that has conductive lead fingers connected to a removable frame. The frame temporarily supports the lead fingers in position relative to the die during manufacture. Each lead finger is coupled to a corresponding bond pad of a die (e.g., via a wire bond or a metal redistribution layer), and the assembly is encapsulated in such a way that the frame and a portion of each of the lead fingers extend outside the encapsulating material. The frame is then trimmed off, and the exposed portions of each lead finger connect the die to external components. In general, individual lead fingers can be bent and then coupled to a corresponding external bond pad.
Die manufacturers have come under increasing pressure to reduce the volume occupied by the dies and yet increase the capacity of the resulting encapsulated assemblies. To meet these demands, die manufacturers often stack multiple dies on top of each other to increase the capacity or performance of the device within the limited surface area on the circuit board or other element to which the dies are mounted.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional side view of a stacked system that includes microelectronic die packages configured and stacked in accordance with an embodiment of the disclosure.
FIG. 2A is a top view of a microelectronic assembly that includes a frame, a release layer, and a support substrate.
FIGS. 2B and 2C are partially exploded cross-sectional side views of the assembly of FIG. 2A.
FIG. 3A is a top view of the assembly of FIG. 2A having microelectronic dies positioned within openings of the frame.
FIGS. 3B and 3C are cross-sectional side views of the assembly of FIG. 3A.
FIG. 4A is a top view of the assembly of FIG. 3A encapsulated in a dielectric material.
FIGS. 4B and 4C are cross-sectional side views of the assembly of FIG. 4A.
FIGS. 5A and 5B are cross-sectional side and bottom views of the assembly of FIG. 4A after removing the support substrate.
FIG. 6 is a cross-sectional side view of the assembly of FIGS. 5A and 5B after forming a spacer layer.
FIG. 7 is a cross-sectional side view of the assembly of FIG. 6A after partial removal of the dielectric material.
FIG. 8A is a cross-sectional side view of the assembly of FIG. 7 after singulation and formation of metal leads.
FIG. 8B is a cross-sectional side view of the assembly of FIG. 7 after singulation and formation of metal leads in accordance with an alternative embodiment of the disclosure.
FIG. 9 is a cross-sectional side view of a stacked system that includes microelectronic die packages configured and stacked in accordance with an alternative embodiment of the disclosure.
FIG. 10 is a cross-sectional side view of a stacked system having microelectronic die packages that include dies of different sizes in accordance with an embodiment of the disclosure.
FIG. 11 is a cross-sectional side view of a stacked system having metal traces for selectively electrically coupling individual microelectronic die packages in accordance with an embodiment of the disclosure.
FIG. 12 is a schematic illustration of a system in which the microelectronic die packages and stacked systems may be incorporated.
Specific details of several embodiments of the disclosure are described below with reference to semiconductor devices and methods for fabricating semiconductor devices. The semiconductor components are manufactured on semiconductor wafers that can include substrates upon which or in which microelectronic devices, micromechanical devices, data storage elements, optics, read/write components, and other features are fabricated. For example, SRAM, DRAM (e.g., DDR/SDRAM), flash memory (e.g., NAND flash memory), processors, imagers, and other types of devices can be constructed on semiconductor wafers. Although many of the embodiments are described below with respect to semiconductor devices that have integrated circuits, other types of devices manufactured on other types of substrates may be within the scope of the invention. Moreover, several other embodiments of the invention can have different configurations, components, or procedures than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the invention may have other embodiments with additional elements, or the invention may have other embodiments without several of the features shown and described below with reference to FIGS. 1-12.
FIG. 1 is a cross-sectional side view of one embodiment of a stacked system 100 having a plurality of die packages 10 (identified individually by reference numbers 10 a-d). Individual die packages 10 can include a microelectronic die 12, a molded dielectric casing 14, and metal leads 16 (or metal contacts) that are laterally spaced apart from the casing 14. The casing 14 has lateral casing sides 21, a top casing side 22, and a bottom casing side 23, and the casing 14 encapsulates at least a portion of the die 12 and the leads 16. In the example shown in FIG. 1, individual leads 16 are coupled to the bottom casing side 23 and project, at least in part, towards an above-located die package or the top of the stacked system 100. Individual leads 16 can further include an exterior lead surface 25 and an interior lead surface 26 having a region 27 that generally faces an individual lateral casing side 21. The interior surface region 27 of the illustrated example is located on an angled lead portion 28 of an individual lead 16, which is spaced laterally apart from the lateral casing side 21 by a lateral lead portion 29 of the lead. The die packages 10 can further include metal traces 32 that electrically couple the leads 16 to the die 12 and a dielectric spacer layer 34 encasing the traces 32 and a portion of an active side of the die 12. The die packages 10 can also include package bond pads 36 coupled to the traces 32. The stacked system 100, for example, has an interposer substrate 102 with metal bump pads 104 electrically connected to the package bond pads 36 at the first die package 10 a by bond pad connections 106.
The embodiment of the stacked system 100 shown in FIG. 1 includes the four stacked die packages 10 a-d physically coupled together at corresponding top and bottom sides by adhesive layers 112 a-c, and the leads 16 of the die packages 10 a-d are electrically coupled together by external inter-package connectors 114. The connectors 114, for example, can be metal solder lines formed along portions of the exterior lead surfaces 25 corresponding to sets of vertically aligned leads 16 and optionally along portions of the interior lead surfaces 26. Thus, the metal pads 104 are electrically coupled to microelectronic dies within the die packages 10 a-d through conduction paths that include the leads 16 and the connectors 114. In many embodiments, and as shown in FIG. 1, the leads 16 corresponding to the die packages 10 a-c extend beyond the top casing side 22, contact a portion of the exterior lead surface 25 on an above-located die package 10, and are held to the portion of the exterior lead surface 25 by an individual connector 114. Additionally, the embodiment of the individual connectors 114 shown in FIG. 1 attach to portions of the exterior and interior lead surfaces 25-26 along the angled and lateral lead portions 28-29. In alternative embodiments, the connectors 114 may attach only to a portion of the exterior lead surface 25 along the angled lead portion 28 and, optionally, a portion of the exterior lead surface 26 along the lateral lead portion 29. Accordingly, several embodiments of the connectors 114 project at least laterally outward from the angled lead portions 28 and may optionally extend in between individual die packages 10 towards the lateral casing sides 21.
The stacked system 100 may be formed by a method that includes stacking the die packages 10 a-d and forming the connectors 114 at individual leads 16 of the die packages 10 a-d. Stacking and aligning the leads 16 may include stacking the die packages 10 a-d in sequence so that the leads 16 of one package are placed above or below corresponding leads on an adjacent die package and so that the leads 16 of a lower package project upwards towards the leads 16 of an upper package. The connectors 114 may be formed using wave or reflow soldering processes. In wave soldering processes, a pumped wave or cascade of liquid-phase metal solder can be applied across the angled lead portions 28. In reflow soldering processes, solder paste having metal powder particles can be applied across the angled lead portions 28 and then heated to melt the metal particles. In these or other soldering processes, the metal solder selectively wets (e.g., when heated) to at least a portion of the exterior lead surfaces 25 and optionally a portion of the interior lead surfaces 26, but the solder does not wet to the dielectric material of the casing 14. The connectors 114 are formed and individual leads 16 of an individual die package 10 are coupled with corresponding leads on an upper or lower die package when the metal solder cools. In other embodiments, some of the individual leads 16 may not physically contact a corresponding lead on an immediately adjacent die package such that only certain leads are interconnected with the adjacent die packages. In any these embodiments, the connectors 114 may bridge a vertical gap between vertically aligned leads 16 of adjacent dies (see, e.g., FIG. 9, reference 68). A vertical lead spacing distance of 60 microns or less, for example, may create adequate surface tension for forming a solder bridge between the individual leads 16.
In general, and in contrast to the stacked system 100, conventional methods of stacking packages or dies have been challenging and expensive. For example, because conventional leads are not arranged to face a dielectric casing or project towards an above-located die package, they can be difficult to position and can collapse underneath a package if not accurately aligned. In addition, attaching a conventional lead on one package to a conventional lead on a corresponding package is time-intensive and requires careful manual manipulation and inspection of each conventional lead-to-lead interconnection. For example, the conventional leads on an above-located die package are generally bent downward so that they project towards the lead on a below-located die package. When the conventional leads undergo an attachment process, the lead-to-lead connection needs to be inspected to verify that the bent lead is correctly positioned with the package below. Also, the process of stacking conventional packages is difficult to standardize because dies are made in a variety of sizes, and packages likewise vary in size. Thus, the process of stacking and interconnecting conventional packages needs to be tailored to an arrangement of a particular package type.
Several embodiments of microelectronic die packages 10 can be easy to stack and are robust. For example, after stacking and aligning the die packages 10 a-d, the leads 16 of corresponding die packages are automatically sufficiently aligned for the connectors 114 to intercouple the leads and do not require manual manipulation to align the individual leads with respect to one another. Further, because the leads 16 extend outwardly from the lateral sides of the casing 14, they provide a contact surface that is located on both lateral and angled portions of an individual lead; this enables the die packages 10 a-d to be intercoupled using a simple soldering process and creates reliable lead-to-lead interconnections that do not require stringent alignment tolerances. Also, the lateral casing sides 21 of the die package 10 can prevent the leads 16 from collapsing during die package stacking by providing a surface for an individual lead 16 to compress or spring back upon. In addition, the leads 16 can further establish the exterior package dimensions such that a standardized package size may be used to house a variety of differently sized dies as explained in further detail below with reference to FIG. 10.
FIGS. 2A-8B illustrate stages of forming a microelectronic die package in accordance with several embodiments of the disclosure. FIG. 2A is a top view of a microelectronic assembly 40 that includes a metal frame 41 situated on top of a release layer 45. The frame 41 comprises lead portions 42, openings 43, and dicing lanes 44. The openings 43 expose a portion of the release layer 45 for attaching and positioning a die 12 (FIG. 1) adjacent to the lead portions 42, and the dicing lanes 44 provide a cutting or cleavage path for singulating an individual die package from the frame 41 (described further with reference to FIGS. 8A and 8B). In one embodiment, the frame 41 may be made from copper and may include selective copper plating along the lead portions 42. In other embodiments, the frame 41 may comprise a variety of other metallic materials such as aluminum or an aluminum-copper alloy. The release layer 45 may be, for example, a thermal or UV release film.
FIGS. 2B and 2C are partially exploded cross-sectional side views of the assembly 40 showing the frame 41, the lead portions 42, the release layer 45, and a support substrate 47 (e.g., a silicon wafer or other type of structure having planar surface). FIG. 2B further shows an individual dicing lane 44, and FIG. 2C further shows gaps 48 between the individual lead portions 42. The gaps 48, along with the openings 43 and the support substrate 47, define bottom and lateral sides of a cavity, which will be subsequently filled with a dielectric material (described further with reference to FIGS. 4A-C). The individual lead portions 42 are spaced apart from each other by a spacing distance s1, which should be large enough to prevent the connectors 114 from laterally bridging across individual leads.
FIG. 3A is a top view of the assembly 40 after attaching microelectronic dies to the release layer 45. FIG. 3A, more specifically, shows the frame 41, the lead portions 42, and the openings 43 with individual dies 12 placed within the openings 43 and adjacent to the lead portions 42. FIGS. 3B and 3C are cross-sectional side views further showing the openings 43 and the lead portions 42, which are below a top-side surface of the dies 12 and have a thickness t1. In several embodiments, the lead portions 42 may have a thickness t1 in the range of about 50 to 250 microns.
FIG. 4A is a top view of the assembly 40 after a dielectric material 50 has been formed on a top side of the metal frame 41 and a top side of the dies 12. The dielectric material 50, for example, may be a polymer or plastic that is heated and subsequently deposited on top of and within the gaps of the frame 41. The dielectric material 50, for example, can be molded over the frame 41 and the top sides of the dies 12. FIGS. 4B and 4C are cross-sectional side views showing the dielectric material 50 filling the openings 43 around the dies 12 and the gaps 48 between the lead portions 42. After curing or cooling, the hardened dielectric material 50 should form a protective and electrically isolative covering over the dies 12, within gaps between lateral sides of the dies 12 and the lead portions 42, and within the gaps 48 between the lead portions 42. The dielectric material 50 may optionally extend above the dies 12 by a thickness t2 to completely encapsulate all of the dies 12 and lead portions 42.
FIGS. 5A and 5B are cross-sectional side and bottom views of the assembly 40 after removing the release layer 45 and the support substrate 47 to expose bottom-side surfaces 52 (e.g., active side) of the dies 12 and expose bottom-side surfaces 54 of the lead portions 42. The bottom-side surfaces 52 of the dies 12 include bond pads 56 (or active features) electrically coupled to an integrated circuit within the dies 12 (not shown). The dielectric material 50 holds the dies 12 in place and separates the dies 12 from the lead portions 42.
FIG. 6 is a cross-sectional side view of the assembly 40 after forming an embodiment of the dielectric spacer layer 34 at the bottom-side surfaces 52 of the dies 12. The spacer layer 34 includes the metal traces 32 electrically coupling the bond pads 56 to the lead portions 42 and the package bond pads 36. The spacer layer 34 may be made from a material such as a non-conductive oxide or polymer. The metal traces 32 and the package bond pads 36, for example, may be made from copper or aluminum. The spacer layer 34 can accordingly be a redistribution structure. It is also expected that in certain embodiments, the package bond pads 36 may be omitted. For example, in FIG. 1 the package bond pads of the die packages 10 b-d could be omitted because these pads are not electrically connected to any external bond pads.
FIG. 7 is a cross-sectional side view of the assembly 40 after removing a portion of the dielectric material 50 by a chemical etch, backgrinding, or chemical-mechanical polishing process to form the casings 14. The dielectric material 50, for example, can be etched to expose the interior lead surfaces 26 (FIG. 1) and to form the top sides 22 and lateral casing sides 21 of the casings 14. Additionally, although shown as having sloped surfaces, the lateral casing sides 21 may be formed in other embodiments so that they are generally perpendicular to the top casing side 22. It is expected, however, that sloped, curved, tapered, or otherwise graded profiles of the lateral casing sides 21 provide an individual lead with room to bend or compress underneath an above-situated lead or die package. Also, sloped lateral casing sides 21 may be used to increase a lateral spacing distance between an individual lead and an upper portion the lateral casing side 21 to provide more room for forming a connector on the interior lead surface 26.
FIG. 8A is a cross-sectional side view of an embodiment of the package 10 a after singulation through the dicing lanes 44 (e.g., by trim and form equipment) to yield separated dies 12 housed in the casings 14 and coupled to individual “L”-type leads 16. FIG. 8B shows an alternative embodiment after singulation of a die package 60 a that is formed to have individual “C”-type leads 66 that include a tiered lead portion 67 laterally extending toward the lateral casing sides 21. In both embodiments, the lateral lead portion 29 projects away from the lateral casing side 21, the angled lead portion 28 extends away from the lateral lead portion 29 so that the interior surface region 27 is generally aligned with a surface at the lateral casing side 21, and the exterior lead surface 25 generally faces away from the lateral casing side 21 and is arranged to receive an external inter-package connector. The angled lead portion 28 may include a variety of angled, curved, or otherwise sloped profiles, which can optionally include a profile that is substantially perpendicular to the lateral lead portion 29 or a profile that is substantially sloped toward the lateral casing side 21. In the embodiment of FIG. 8B, the angled lead portion 28 is substantially perpendicular with the lateral lead portion 29, and the angled lead portion 28 positions the tiered lead portion 67 above the lateral lead portion 29. This allows an individual lead 66 to accommodate additional types of external inter-package connectors, such as metal solder bumps (see, e.g., FIG. 9). Accordingly, the die package(s) 10 a or 60 a may be placed within a stacked system, such as the stacked system 100, and the connectors 114 can be formed along the die packages 10 a or 60 a at any of the exposed or otherwise accessible surfaces of the leads 16 or 66 at the angled lead portion 28, the lateral lead portion 29, or the tiered lead portion 67.
FIG. 9 is a cross-sectional side view of an embodiment of a stacked system 200 that includes the individual die package 60 a as well as die packages 60 b-d physically coupled together, at least in part, by adhesive layers 112 a-c. The leads 66 of the die packages 60 a-d are physically and electrically coupled together by external inter-package connectors 214. In this embodiment, the connectors 214 include metal solder bumps interposed between the tiered lead portions 67 and the lateral lead portions 29 on corresponding die packages. The leads 66 of the individual die packages 60 are vertically separated from each other by a gap 68 spanning a distance t3, which may be on the order of 60 microns or less. Individual connectors 214 bridge the gaps 68 and attach to portions of the exterior lead surfaces 25 along the tiered lead portions 67 as well as the angled and lateral lead portions 28-29. Similar to the stacked system 100, the stacked system 200 may be formed by a method that includes stacking the die packages 60 a-d such that the leads 66 of the die packages 60 a-d are aligned, and forming the connectors 214 at individual leads 66 of the die packages 60 a-d. The connectors 214 may be formed using a metal solder bump process that includes forming a dot of metal solder that attaches to portions of the exterior lead surfaces 25. As shown, the dot of solder may be configured to attach to the exterior lead surface 25 along the angled lead portions 28 such that the connectors 214 are positioned between the individual die packages 60 a-d and project outward from the lateral lead portions 29. In other embodiments, the connectors 214 may be further coupled to portions of the interior lead surfaces 26.
FIG. 10 is a cross-sectional side view showing an embodiment of a stacked system 300 that includes microelectronic die packages 72 a-c having corresponding microelectronic dies 74 a-c. The die packages 72 a-c share a common lateral dimension d1, but the microelectronic dies 74 a-c have different lateral dimensions d2, d3, and d4 (not in that order). In one embodiment, the stacked system 300 may be a memory module that includes an interface circuit at the die 74 a, a control circuit at the die 74 b, and a memory at the die 74 c. Because the packages 72 a-c share the common lateral dimension d1, a myriad of different types of stacked systems may be created by stacking preferred die packages or exchanging certain die packages. For example, an alternative embodiment of the DRAM-based memory module could be assembled by using smaller magnetoresistive RAM (MRAM) based dies housed in die packages having the lateral dimension d1. Accordingly, DRAM-based die packages 72 b-c could be exchanged for MRAM-based die packages.
FIG. 11 is a cross-sectional side view showing an embodiment of a stacked system 400 that includes microelectronic die packages 82 a-d separated by dielectric spacer layers 84 a-d and having corresponding first metal leads 86 a-d and second metal leads 88 a-d respectively coupled together by first and second connectors 414 a-b. In this view, the spacer layer 84 a includes corresponding metal traces 90 a-b, the spacer layer 84 c includes corresponding metal traces 91 a-b, the spacer layer 84 d includes a single metal trace 92, but the spacer layer 84 b does not have any corresponding metal traces along this view of the second package 82 b (i.e., the die packages 82 a-d may have a different arrangement of metal traces in other cross-sectional views such that the second package 82 b does not have metal traces along the illustrated cross-section). The first connector 414 a is applied across the first leads 86 a-d to selectively electrically couple first, third, and fourth packages 82 a, 82 c, and 82 d; and the second connector 414 b is applied across the second leads 88 a-d to selectively electrically couple the first and third packages 82 a and 82 c. Thus, one side of the die package 82 d and both sides of the die package 82 b are electrically isolated from the connectors 414 a-b. The process of stacking the die packages 82 a-d can be the same as the process described with reference to FIGS. 1 and 9. The process of forming the die packages 82 a-d can be similar to the method of manufacturing described with reference to FIGS. 2A-8B, but instead of connecting a metal trace to every metal lead, individual metal trace-lead couplings have been omitted.
Many other types of variations may be made to the above described stacked systems, including various combinations of certain features associated with these systems. For example, in lieu of the bond pad connections 106 (FIGS. 1 and 9), wire bonds may electrically couple a stacked system to an interposer substrate. In some embodiments, the adhesive layers interposed between the stacked packages may be omitted. The external inter-package connectors alone, for example, could be used to hold individual die packages together by temporarily clamping the packages until metal solder is applied and the connectors are formed. In other embodiments, the connectors can be configured to selectively route individual sets of the leads by applying metal solder across a limited number of leads. Leads that are not soldered remain electrically isolated from the stacked system. In one specific embodiment, a stacked system includes die packages that house the same type of die. For example, a stacked system could be a memory, such as a static dynamic access memory (SRAM). In this embodiment, individual leads would provide word and bit line access to individual SRAM dies housed in the individual die packages. Accordingly, the aggregated individual SRAM dies form a large SRAM, which has a reduced footprint relative to a conventional SRAM of the same size. Also, the stacked system may include any number of individual microelectronic die packages having more or fewer packages than those presented in the illustrated embodiments.
Any one of the microelectronic devices described above with reference to FIGS. 1-11 can be incorporated into any of a myriad of larger or more complex systems 490, a representative one of which is shown schematically in FIG. 12. The system 490 can include a processor 491, a memory 492 (e.g., SRAM, DRAM, Flash, or other memory device), input/output devices 493, or other subsystems or components 494. Microelectronic devices may be included in any of the components shown in FIG. 12. The resulting system 490 can perform any of a wide variety of computing, processing, storage, sensor, imaging, or other functions. Accordingly, representative systems 490 include, without limitation, computers or other data processors, for example, desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants), multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Other representative systems 490 include cameras, light or other radiation sensors, servers and associated server subsystems, display devices, or memory devices. In such systems, individual dies can include imager arrays, such as CMOS imagers. Components of the system 490 may be housed in a single unit or distributed over multiple, interconnected units, e.g., through a communications network. Components can accordingly include local or remote memory storage devices and any of a wide variety of computer-readable media.
From the foregoing, it will be appreciated that specific embodiments have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the foregoing embodiments. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is inclusive and is used throughout to mean including at least the recited feature(s) such that any greater number of the same feature or additional types of other features are not precluded. It will also be appreciated that specific embodiments have been described herein for purposes of illustration, but that various modifications may be made without deviating from the inventions. For example, many of the elements of one embodiment can be combined with other embodiments in addition to, or in lieu of, the elements of the other embodiments. Accordingly, the invention is not limited except as by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3746934||May 6, 1971||Jul 17, 1973||Siemens Ag||Stack arrangement of semiconductor chips|
|US5107328||Feb 13, 1991||Apr 21, 1992||Micron Technology, Inc.||Packaging means for a semiconductor die having particular shelf structure|
|US5128831||Oct 31, 1991||Jul 7, 1992||Micron Technology, Inc.||High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias|
|US5138434||Jan 22, 1991||Aug 11, 1992||Micron Technology, Inc.||Packaging for semiconductor logic devices|
|US5145099||Nov 4, 1991||Sep 8, 1992||Micron Technology, Inc.||Method for combining die attach and lead bond in the assembly of a semiconductor package|
|US5252857||Aug 5, 1991||Oct 12, 1993||International Business Machines Corporation||Stacked DCA memory chips|
|US5356838||Oct 25, 1993||Oct 18, 1994||Samsung Electronics Co., Ltd.||Manufacturing method of a semiconductor device|
|US5518957||Mar 28, 1994||May 21, 1996||Samsung Electronics Co., Ltd.||Method for making a thin profile semiconductor package|
|US5554886||Feb 7, 1995||Sep 10, 1996||Goldstar Electron Co., Ltd.||Lead frame and semiconductor package with such lead frame|
|US5593927||Dec 1, 1995||Jan 14, 1997||Micron Technology, Inc.||Method for packaging semiconductor dice|
|US5677566||May 8, 1995||Oct 14, 1997||Micron Technology, Inc.||Semiconductor chip package|
|US5760471 *||Feb 3, 1997||Jun 2, 1998||Fujitsu Limited||Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package|
|US5801439||Feb 21, 1997||Sep 1, 1998||Fujitsu Limited||Semiconductor device and semiconductor device unit for a stack arrangement|
|US5807762 *||Mar 12, 1996||Sep 15, 1998||Micron Technology, Inc.||Multi-chip module system and method of fabrication|
|US5811877||Mar 31, 1997||Sep 22, 1998||Hitachi, Ltd.||Semiconductor device structure|
|US5826628||Jun 6, 1997||Oct 27, 1998||Micron Technology, Inc.||Form tooling and method of forming semiconductor package leads|
|US5835988||Oct 24, 1996||Nov 10, 1998||Mitsubishi Denki Kabushiki Kaisha||Packed semiconductor device with wrap around external leads|
|US5851845||Dec 18, 1995||Dec 22, 1998||Micron Technology, Inc.||Process for packaging a semiconductor die using dicing and testing|
|US5879965||Jun 19, 1997||Mar 9, 1999||Micron Technology, Inc.||Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication|
|US5883426||Apr 18, 1997||Mar 16, 1999||Nec Corporation||Stack module|
|US5891797||Oct 20, 1997||Apr 6, 1999||Micron Technology, Inc.||Method of forming a support structure for air bridge wiring of an integrated circuit|
|US5894218||Aug 7, 1996||Apr 13, 1999||Micron Technology, Inc.||Method and apparatus for automatically positioning electronic dice within component packages|
|US5933713||Apr 6, 1998||Aug 3, 1999||Micron Technology, Inc.||Method of forming overmolded chip scale package and resulting product|
|US5938956||Sep 10, 1996||Aug 17, 1999||Micron Technology, Inc.||Circuit and method for heating an adhesive to package or rework a semiconductor die|
|US5946553||Sep 25, 1995||Aug 31, 1999||Micron Technology, Inc.||Process for manufacturing a semiconductor package with bi-substrate die|
|US5986209||Jul 9, 1997||Nov 16, 1999||Micron Technology, Inc.||Package stack via bottom leaded plastic (BLP) packaging|
|US5990566||May 20, 1998||Nov 23, 1999||Micron Technology, Inc.||High density semiconductor package|
|US5994784||Dec 18, 1997||Nov 30, 1999||Micron Technology, Inc.||Die positioning in integrated circuit packaging|
|US6002167||Sep 20, 1996||Dec 14, 1999||Hitachi Cable, Ltd.||Semiconductor device having lead on chip structure|
|US6004867||Dec 12, 1997||Dec 21, 1999||Samsung Electronics Co., Ltd.||Chip-size packages assembled using mass production techniques at the wafer-level|
|US6008070||May 21, 1998||Dec 28, 1999||Micron Technology, Inc.||Wafer level fabrication and assembly of chip scale packages|
|US6018249||Dec 11, 1997||Jan 25, 2000||Micron Technolgoy, Inc.||Test system with mechanical alignment for semiconductor chip scale packages and dice|
|US6020624||Apr 1, 1998||Feb 1, 2000||Micron Technology, Inc.||Semiconductor package with bi-substrate die|
|US6020629||Jun 5, 1998||Feb 1, 2000||Micron Technology, Inc.||Stacked semiconductor package and method of fabrication|
|US6028352 *||Jun 10, 1998||Feb 22, 2000||Irvine Sensors Corporation||IC stack utilizing secondary leadframes|
|US6028365||Mar 30, 1998||Feb 22, 2000||Micron Technology, Inc.||Integrated circuit package and method of fabrication|
|US6030858||Nov 19, 1997||Feb 29, 2000||Lg Semicon Co., Ltd.||Stacked bottom lead package in semiconductor devices and fabricating method thereof|
|US6048744||Sep 15, 1997||Apr 11, 2000||Micron Technology, Inc.||Integrated circuit package alignment feature|
|US6051878||Jan 19, 1999||Apr 18, 2000||Micron Technology, Inc.||Method of constructing stacked packages|
|US6064194||Dec 17, 1996||May 16, 2000||Micron Technology, Inc.||Method and apparatus for automatically positioning electronic dice within component packages|
|US6066514||Nov 3, 1997||May 23, 2000||Micron Technology, Inc.||Adhesion enhanced semiconductor die for mold compound packaging|
|US6072233||May 4, 1998||Jun 6, 2000||Micron Technology, Inc.||Stackable ball grid array package|
|US6072236||Mar 7, 1996||Jun 6, 2000||Micron Technology, Inc.||Micromachined chip scale package|
|US6089920||May 4, 1998||Jul 18, 2000||Micron Technology, Inc.||Modular die sockets with flexible interconnects for packaging bare semiconductor die|
|US6097087||Oct 31, 1997||Aug 1, 2000||Micron Technology, Inc.||Semiconductor package including flex circuit, interconnects and dense array external contacts|
|US6103547||Jan 17, 1997||Aug 15, 2000||Micron Technology, Inc.||High speed IC package configuration|
|US6104086||Apr 13, 1998||Aug 15, 2000||Nec Corporation||Semiconductor device having lead terminals bent in J-shape|
|US6107122||Aug 4, 1997||Aug 22, 2000||Micron Technology, Inc.||Direct die contact (DDC) semiconductor package|
|US6111312||Jun 2, 1999||Aug 29, 2000||Fujitsu Limited||Semiconductor device with leads engaged with notches|
|US6124634||Sep 17, 1998||Sep 26, 2000||Micron Technology, Inc.||Micromachined chip scale package|
|US6130474||Oct 12, 1999||Oct 10, 2000||Micron Technology, Inc.||Leads under chip IC package|
|US6133068||Mar 8, 1999||Oct 17, 2000||Micron Technology, Inc.||Increasing the gap between a lead frame and a semiconductor die|
|US6133622||Dec 31, 1997||Oct 17, 2000||Micron Technology, Inc.||High speed IC package configuration|
|US6146919||Jun 21, 1999||Nov 14, 2000||Micron Technology, Inc.||Package stack via bottom leaded plastic (BLP) packaging|
|US6148509||Aug 26, 1998||Nov 21, 2000||Micron Technology, Inc.||Method for supporting an integrated circuit die|
|US6150710||Apr 29, 1999||Nov 21, 2000||Micron Technology, Inc.||Transverse hybrid LOC package|
|US6150717||Jun 16, 1998||Nov 21, 2000||Micron Technology, Inc.||Direct die contact (DDC) semiconductor package|
|US6153924||Dec 13, 1999||Nov 28, 2000||Micron Technology, Inc.||Multilayered lead frame for semiconductor package|
|US6159764||Jul 2, 1997||Dec 12, 2000||Micron Technology, Inc.||Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages|
|US6175149||Feb 13, 1998||Jan 16, 2001||Micron Technology, Inc.||Mounting multiple semiconductor dies in a package|
|US6184465||Nov 12, 1998||Feb 6, 2001||Micron Technology, Inc.||Semiconductor package|
|US6187615||Dec 28, 1998||Feb 13, 2001||Samsung Electronics Co., Ltd.||Chip scale packages and methods for manufacturing the chip scale packages at wafer level|
|US6188232||Jun 29, 1998||Feb 13, 2001||Micron Technology, Inc.||Temporary package, system, and method for testing semiconductor dice and chip scale packages|
|US6198172||Feb 20, 1997||Mar 6, 2001||Micron Technology, Inc.||Semiconductor chip package|
|US6201304||Oct 10, 1997||Mar 13, 2001||Micron Technology, Inc.||Flip chip adaptor package for bare die|
|US6212767||Aug 31, 1999||Apr 10, 2001||Micron Technology, Inc.||Assembling a stacked die package|
|US6214716||Sep 30, 1998||Apr 10, 2001||Micron Technology, Inc.||Semiconductor substrate-based BGA interconnection and methods of farication same|
|US6225689||Aug 14, 2000||May 1, 2001||Micron Technology, Inc.||Low profile multi-IC chip package connector|
|US6228548||Feb 11, 2000||May 8, 2001||Micron Technology, Inc.||Method of making a multichip semiconductor package|
|US6228687||Jun 28, 1999||May 8, 2001||Micron Technology, Inc.||Wafer-level package and methods of fabricating|
|US6229202||Jan 10, 2000||May 8, 2001||Micron Technology, Inc.||Semiconductor package having downset leadframe for reducing package bow|
|US6232666||Dec 4, 1998||May 15, 2001||Mciron Technology, Inc.||Interconnect for packaging semiconductor dice and fabricating BGA packages|
|US6235552||Jan 12, 2000||May 22, 2001||Samsung Electronics Co., Ltd.||Chip scale package and method for manufacturing the same using a redistribution substrate|
|US6235554||May 24, 1999||May 22, 2001||Micron Technology, Inc.||Method for fabricating stackable chip scale semiconductor package|
|US6239489||Jul 30, 1999||May 29, 2001||Micron Technology, Inc.||Reinforcement of lead bonding in microelectronics packages|
|US6246108||Aug 12, 1999||Jun 12, 2001||Micron Technology, Inc.||Integrated circuit package including lead frame with electrically isolated alignment feature|
|US6246110||Oct 12, 1999||Jun 12, 2001||Micron Technology, Inc.||Downset lead frame for semiconductor packages|
|US6247629||Feb 5, 1999||Jun 19, 2001||Micron Technology, Inc.||Wire bond monitoring system for layered packages|
|US6252772||Feb 10, 1999||Jun 26, 2001||Micron Technology, Inc.||Removable heat sink bumpers on a quad flat package|
|US6258623||Jul 8, 1999||Jul 10, 2001||Micron Technology, Inc.||Low profile multi-IC chip package connector|
|US6258624||May 1, 2000||Jul 10, 2001||Micron Technology, Inc.||Semiconductor package having downset leadframe for reducing package bow|
|US6259153||Jul 12, 2000||Jul 10, 2001||Micron Technology, Inc.||Transverse hybrid LOC package|
|US6261865||Oct 6, 1998||Jul 17, 2001||Micron Technology, Inc.||Multi chip semiconductor package and method of construction|
|US6265766||Jan 14, 2000||Jul 24, 2001||Micron Technology, Inc.||Flip chip adaptor package for bare die|
|US6271580||Apr 29, 1999||Aug 7, 2001||Micron Technology, Inc.||Leads under chip in conventional IC package|
|US6281042||Aug 31, 1998||Aug 28, 2001||Micron Technology, Inc.||Structure and method for a high performance electronic packaging assembly|
|US6281577||Apr 22, 1997||Aug 28, 2001||Pac Tech-Packaging Technologies Gmbh||Chips arranged in plurality of planes and electrically connected to one another|
|US6284571||May 25, 1999||Sep 4, 2001||Micron Technology, Inc.||Lead frame assemblies with voltage reference plane and IC packages including same|
|US6285204||Jun 3, 2000||Sep 4, 2001||Micron Technology, Inc.||Method for testing semiconductor packages using oxide penetrating test contacts|
|US6291894||Aug 31, 1998||Sep 18, 2001||Micron Technology, Inc.||Method and apparatus for a semiconductor package for vertical surface mounting|
|US6294839||Aug 30, 1999||Sep 25, 2001||Micron Technology, Inc.||Apparatus and methods of packaging and testing die|
|US6297547||May 19, 2000||Oct 2, 2001||Micron Technology Inc.||Mounting multiple semiconductor dies in a package|
|US6303981||Sep 1, 1999||Oct 16, 2001||Micron Technology, Inc.||Semiconductor package having stacked dice and leadframes and method of fabrication|
|US6303985||Nov 12, 1998||Oct 16, 2001||Micron Technology, Inc.||Semiconductor lead frame and package with stiffened mounting paddle|
|US6310390||Apr 8, 1999||Oct 30, 2001||Micron Technology, Inc.||BGA package and method of fabrication|
|US6313998||Apr 2, 1999||Nov 6, 2001||Legacy Electronics, Inc.||Circuit board assembly having a three dimensional array of integrated circuit packages|
|US6320251||Jan 18, 2000||Nov 20, 2001||Amkor Technology, Inc.||Stackable package for an integrated circuit|
|US6326697||Dec 10, 1998||Dec 4, 2001||Micron Technology, Inc.||Hermetically sealed chip scale packages formed by wafer level fabrication and assembly|
|US6326698||Jun 8, 2000||Dec 4, 2001||Micron Technology, Inc.||Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices|
|US6329222||Dec 20, 1999||Dec 11, 2001||Micron Technology, Inc.||Interconnect for packaging semiconductor dice and fabricating BGA packages|
|US6329705||May 20, 1998||Dec 11, 2001||Micron Technology, Inc.||Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes|
|US6487078 *||Mar 13, 2000||Nov 26, 2002||Legacy Electronics, Inc.||Electronic module having a three dimensional array of carrier-mounted integrated circuit packages|
|US6717275 *||Apr 30, 2002||Apr 6, 2004||Renesas Technology Corp.||Semiconductor module|
|US7145227 *||Jul 29, 2004||Dec 5, 2006||Nec Toshiba Space Systems, Ltd.||Stacked memory and manufacturing method thereof|
|USRE36469||Sep 26, 1995||Dec 28, 1999||Micron Technology, Inc.||Packaging for semiconductor logic devices|
|1||International Search Report and Written Opinion issued Dec. 11, 2008 for International Application No. PCT/US2008/070325.|
|2||Search Report and Written Opinion issued Feb. 16, 2009 in Singapore Application No. 200705422-4.|
|3||U.S. Appl. No. 11/923,290, filed Oct. 24, 2007.|
|4||Written Opinion (corrected version) issued Jul. 1, 2009 in Singapore Application No. 200705422-4.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8012802 *||Feb 4, 2010||Sep 6, 2011||Headway Technologies, Inc.||Method of manufacturing layered chip package|
|US8410603 *||Jun 24, 2011||Apr 2, 2013||SK Hynix Inc.||Semiconductor device and package|
|US20110058342 *||Aug 25, 2010||Mar 10, 2011||Hitachi, Ltd.||Semiconductor Device|
|US20120007236 *||Jun 24, 2011||Jan 12, 2012||Hynix Semiconductor Inc.||Semiconductor device and package|
|US20130168875 *||Feb 27, 2013||Jul 4, 2013||SK Hynix Inc.||Semiconductor device and package|
| || |
|U.S. Classification||257/686, 438/109, 257/724, 438/110, 257/E23.18, 257/723|
|Cooperative Classification||H01L2225/1058, H01L2225/1064, H01L2225/1029, H01L24/18, H01L25/105, H01L23/49555, H01L23/3121, H01L2924/01079, H01L2224/16, H01L23/49861, H01L2924/01078|
|European Classification||H01L23/495G4B6, H01L25/10J, H01L23/498L|
|Sep 28, 2007||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ENG, MEOW KOON;CHIA, YONG POO;BOON, SUAN JEUNG;REEL/FRAME:019894/0296
Effective date: 20070828