|Publication number||US7849339 B2|
|Application number||US 11/690,659|
|Publication date||Dec 7, 2010|
|Filing date||Mar 23, 2007|
|Priority date||Mar 23, 2007|
|Also published as||CN101641866A, CN101641866B, EP2135354A1, EP2135354A4, US20080235526, WO2008118821A1|
|Publication number||11690659, 690659, US 7849339 B2, US 7849339B2, US-B2-7849339, US7849339 B2, US7849339B2|
|Original Assignee||Silicon Image, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Non-Patent Citations (2), Referenced by (10), Classifications (13), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
In electronics, a phase-locked loop (PLL) is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input (“reference”) signal. A PLL circuit responds to both the frequency and the phase of the input signal, automatically adjusting the frequency and phase of a controlled oscillator until the frequency and phase match that of the reference signal. This type of mechanism is widely used in radio, telecommunications, computers, and other electronic applications where it is desirable to stabilize a generated signal or to detect signals in the presence of noise. Since an integrated circuit can hold a complete phase-locked loop building block, the technique is widely used in modern electronic devices, with signal frequencies from a fraction of a cycle per second up to several gigahertz (GHz).
Circuit designers often use digital PLL circuits as master clock synthesizers for microprocessors and key components of universal asynchronous receiver transmitters (UARTs). PLLs generally contain a phase detector, low pass filter, and voltage-controlled oscillator (VCO) placed in a negative feedback configuration. There may be a frequency divider in the feedback path or in the reference path, or both, in order to make the output clock of the PLL a rational multiple of the reference frequency. The oscillator generates a periodic output signal. Depending on the application, either the output of the controlled oscillator or the control signal to the oscillator provides the useful output of the PLL system.
PLLs are widely used for synchronization purposes. Circuits commonly send some data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream using a PLL. This process is referred to as clock data recovery (CDR). Another use for PLLs is clock multiplication. Most electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency of the processor is multiple gigahertz and the reference clock is just tens or hundreds of megahertz.
While PLLs are very broadly used, unfortunately they are not suitable for some applications because the large number of components in a PLL cause the PLL to consume a significant amount of power. For example, mobile device manufacturers might prefer the functionality of a PLL to perform CDR and clock multiplication for high-speed data transfers. The battery drain inherent in a PLL, however, and the impact on battery life of a mobile device often mean that manufacturers must elect to use other technologies or end up compromising the device performance.
A method and system for providing a clock signal having reduced power consumption is provided (the “hybrid clock system”). The hybrid clock system operates in a normal mode of operation and a power-saving mode of operation. In the normal mode of operation, the hybrid clock system uses a PLL for high-speed data transfers. A reference clock that operates at a low frequency (e.g., 30 MHz) is connected to the input of the PLL. The PLL multiplies the reference clock frequency to a much higher frequency (e.g., 3 GHz), and supplies the clock signal to a data transfer circuit. When the hybrid clock system detects low-speed activity in the data transfer circuit, the hybrid clock system switches (or transitions) to the power-saving mode. In the power-saving mode of operation, the hybrid clock system turns off the PLL and connects the reference clock directly to the data transfer circuit. Because of the slower clock speed, in the power-saving mode the data transfer circuit transfers data at a lower rate than when the hybrid clock system is in the normal mode. For many applications, such as mobile phones, the lower transfer speed of the power-saving mode provides adequate data transfer capabilities for some data transfer requests, thereby minimizing the amount of time that the device operates in the normal mode. In this way, the hybrid clock system reduces the power consumed by a device, while still offering high-speed data transfer capabilities.
In some embodiments, the hybrid clock system uses the power-saving mode temporarily while restarting the PLL. For example, when the hybrid clock system is in the power-saving mode and a high-speed data transfer is requested, the hybrid clock system may initiate the transfer in the power-saving mode, and signal the PLL to restart. Once the PLL is restarted, the hybrid clock system switches to the normal mode having full high-speed data transfer capabilities. In some embodiments, the user may see the transfer begin and progressively get faster, providing a better user experience than if the user had to wait for the PLL to restart to begin data transfer.
In some embodiments, the hybrid clock system accelerates the reference clock in the power-saving mode. For example, the reference clock frequency may be increased (e.g., to 150 MHz) to provide the fastest signal available from the reference clock. The circuit used for the reference clock is often capable of faster speeds, but a lower speed is selected to match a multiplication factor of the chosen PLL circuit. When the PLL is turned off, the hybrid clock system may run the reference clock at its maximum speed to provide as much speed as possible without the PLL. Users therefore do not see an appreciable reduction in speed by increasing the clock frequency limits while in the power-saving mode.
Various embodiments of the invention will now be described. The following description provides specific details for a thorough understanding and an enabling description of these embodiments. One skilled in the art will understand, however, that the invention may be practiced without many of these details. Additionally, some well-known structures or functions may not be shown or described in detail, to avoid unnecessarily obscuring the relevant description of the various embodiments. The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific embodiments of the invention.
During operation, the reference clock 105 provides the base clock signal. In normal mode, the reference clock provides a clock signal to the PLL 105. The PLL 105 multiplies the reference clock 105 signal and provides a high-speed clock signal to the serializer circuit 125 and deserializer circuit 135 (the latter through the CDR circuit 130). In power-saving mode, the reference clock 105 is adjusted to a produce a higher frequency clock signal and the PLL 110 is turned off. Instead of driving the PLL, the reference clock signal is divided by the clock divider 115 to provide an appropriate clock frequency to the serializer circuit 125 and deserializer circuit 135. In the power-saving mode, the deserializer circuit 135 and serializer circuit 125 operate at a lower frequency than during the normal mode of operation.
In some embodiments, the reference clock is a time base that may be adjusted to produce a clock signal that varies between 30 MHz and 150 MHz, the PLL is able to multiply the clock signal by a factor of 25, and the clock divider can divide the clock signal by a factor of two. In this configuration, the hybrid clock system is able to output a clock signal of 750 MHz during a normal mode of operation with a 30 MHz reference clock and a clock signal of 75 MHz during a power-saving mode of operation with a 150 MHz reference clock. Those skilled in the art will appreciate that other component values may be utilized in the hybrid clock system to produce a clock signal having different frequencies.
The device in which the system is implemented may include a central processing unit, memory, input devices (e.g., keyboard and pointing devices), output devices (e.g., display devices), and storage devices (e.g., disk drives). The memory and storage devices are computer-readable media that may be encoded with computer-executable instructions that implement parts of the system, which means a computer-readable medium that contains the instructions. In addition, the data structures and message structures may be stored or transmitted via a data transmission medium, such as a signal on a communication link. Various communication links may be used, such as a serial transfer link, the Internet, a local area network, a wide area network, a point-to-point dial-up connection, a cell phone network, and so on.
Embodiments of the system may be implemented in various operating environments that include personal computers, server computers, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, programmable consumer electronics, digital cameras, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and so on. The computer systems may be cell phones, personal digital assistants, smart phones, personal computers, programmable consumer electronics, digital cameras, and so on.
From the foregoing, it will be appreciated that specific embodiments of the hybrid clock system have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
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|U.S. Classification||713/322, 327/156, 713/600, 713/323, 713/324, 327/117|
|Cooperative Classification||Y02B60/32, G06F1/324, Y02B60/1217, G06F1/3215|
|European Classification||G06F1/32P5F, G06F1/32P1C|
|Jul 9, 2007||AS||Assignment|
Owner name: SILICON IMAGE, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, DONGYUN;REEL/FRAME:019533/0378
Effective date: 20070701
|Jun 9, 2014||FPAY||Fee payment|
Year of fee payment: 4
|Mar 19, 2015||AS||Assignment|
Owner name: JEFFERIES FINANCE LLC, NEW YORK
Free format text: SECURITY INTEREST;ASSIGNORS:LATTICE SEMICONDUCTOR CORPORATION;SIBEAM, INC.;SILICON IMAGE, INC.;AND OTHERS;REEL/FRAME:035226/0147
Effective date: 20150310
|Aug 21, 2015||AS||Assignment|
Owner name: LATTICE SEMICONDUCTOR CORPORATION, OREGON
Free format text: MERGER;ASSIGNOR:SILICON IMAGE, INC.;REEL/FRAME:036419/0792
Effective date: 20150513
|Oct 28, 2015||AS||Assignment|
Owner name: LATTICE SEMICONDUCTOR CORPORATION, OREGON
Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC;REEL/FRAME:036905/0327
Effective date: 20151028