Publication number | US7849423 B1 |
Publication type | Grant |
Application number | US 11/781,108 |
Publication date | Dec 7, 2010 |
Filing date | Jul 20, 2007 |
Priority date | Jul 21, 2006 |
Fee status | Paid |
Publication number | 11781108, 781108, US 7849423 B1, US 7849423B1, US-B1-7849423, US7849423 B1, US7849423B1 |
Inventors | Bayram Yenikaya, Devendra Joshi, Paul A. Fornari, Jesus O. Carrero, Abdurrahman Sezginer |
Original Assignee | Cadence Design Systems, Inc. |
Export Citation | BiBTeX, EndNote, RefMan |
Patent Citations (12), Non-Patent Citations (16), Referenced by (15), Classifications (5), Legal Events (3) | |
External Links: USPTO, USPTO Assignment, Espacenet | |
This application claims benefit of U.S. Provisional Application No. 60/807,967 filed Jul. 21, 2006, the entire disclosure of which is incorporated herein by reference.
This invention relates to the general field of optical lithography. In particular, this invention relates to verifying that a given photomask data set will meet a set of design targets.
Layers of semiconductor devices are patterned using lithography and etch processes. Both of these processes distort the pattern that is being transferred from a photomask to a layer on a semiconductor wafer.
The pattern to be formed on the wafer will be called the target pattern for the purposes of this application. The target pattern is produced by design steps that include considerations of circuit function, electrical parameters of devices, placement of components on an integrated circuit, routing of connections, parasitic electrical parameters of interconnections, and timing analysis of the circuit. The target pattern comprises a set of polygons. It is usually stored and transmitted in a file that is in GDS-II or OASIS format.
A photomask is manufactured according to a photomask data set, which comprises a set of polygons. The photomask data set is what is sent to a mask shop when a photomask is ordered. The photomask data is derived from the target pattern. The process that starts with the target pattern, and that yields the photomask data, can include: insertion of assist features, assigning phase-shifts to transparent apertures on the photomask, applying rule-based or model-based optical proximity correction (OPC), or process proximity compensation (PPC; See: Apo Sezginer, Franz X. Zach, Bayram Yenikaya, Jesus Carrero, Hsu-Ting Huang, Proc. SPIE Vol. 6156, March 2006, SPIE Press, Bellingham, Wash.)
The goal of OPC is to render the pattern formed on a wafer similar to a target pattern. In the prior art, OPC algorithms have not always met this goal. OPC users therefore resorted to verifying the OPC output by a model-based simulation. Verification is the art of checking, using a mathematical model of a manufacturing process, whether a given photomask data set will result in a sufficiently close approximation of the target pattern on the wafer. Prior art of verification includes these documents:
U.S. Pat. No. 7,117,477, Ye et al.
U.S. Pat. No. 7,114,145, Ye et al.
U.S. Pat. No. 7,111,277, Ye et al.
U.S. Pat. No. 7,003,758, Ye et al.
U.S. Pat. No. 7,191,428, Tang et al.
U.S. Pat. No. 7,155,689, Pierrat et al.
U.S. Pat. No. 6,944,844, Liu et al.
Mason et al., Proc. SPIE Vol. 6349, p. 63491X-1, SPIE, Bellingham, Wash., 2006
Kang et al., Proc. SPIE Vol. 6154, p. 61543J-1, SPIE, Bellingham, Wash., 2006
Ogino et al., Proc. SPIE Vol. 6151, p. 615129-1, SPIE, Bellingham, Wash., 2006
Hung et al., Proc. SPIE Vol. 5992, p. 59922Z-1, SPIE, Bellingham, Wash., 2005
Kim et al., Proc. SPIE Vol. 5853, p. 599, SPIE, Bellingham, Wash., 2005
Kim et al., Proc. SPIE Vol. 5992, p. 599922U-1, SPIE, Bellingham, Wash., 2005
Tones et al., Proc. SPIE Vol. 5992, p. 59923L-1, SPIE, Bellingham, Wash., 2005
Graur et al., Proc. SPIE Vol. 5379, p. 202, SPIE, Bellingham, Wash., 2004
Belledent et al., Proc. SPIE Vol. 5377, p. 1184, SPIE, Bellingham, Wash., 2004
Shang et al., Proc. SPIE Vol. 5040, p. 431, SPIE, Bellingham, Wash., 2003
van Adrichem et al., SPIE Vol. 5038, p. 1019, SPIE, Bellingham, Wash., 2003
Beale et al., SPIE Vol. 4889, p. 896, SPIE, Bellingham, Wash., 2002
A deficiency in the prior art is that verification has been performed using an optical model. Plasma etching imparts a proximity effect to the pattern formed on the wafer because the access of plasma to the side-wall of the pattern that is being etched, depends on the pattern. The access of the plasma to the side wall has not been taken into account in the prior art of verification.
According to a first aspect of the present invention there is provided a method of verifying a photomask dataset corresponding to a target-pattern, the method comprising (a) simulating a resist-pattern that will be formed in a resist layer by a lithography process; and (b) simulating an etched-pattern that will be etched in a layer by a plasma process wherein said simulation comprises calculating a flux of particles impacting a feature; and (c) determining whether the etched-pattern substantially conforms to the target-pattern.
According to a second aspect of the present invention there is provided a method of verifying a photomask data set corresponding to a target-pattern, the method comprising the following steps in the given order: (a) obtaining a lithography-target from the target-pattern using a mathematical model of the etch-process; and (b) calculating a lithographic image intensity at a point on the lithography-target; and (c) determining if the image intensity is in an acceptable range of values.
The present invention, in accordance with one or more various embodiments, is described in detail with reference to the following figures.
It will be appreciated that the invention is not restricted to the particular embodiments that have been described or illustrated, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims, as interpreted in accordance with principles of prevailing law, including the doctrine of equivalents or any other principle that enlarges the enforceable scope of the claims beyond the literal scope.
Photolithography transfers pattern(s) from one or more photomasks to a photoresist film coated on a semiconductor wafer. The pattern that is formed in photoresist acts as a mask, or a stencil, during a subsequent etching process. Critical features of integrated circuits are usually etched by so called plasma-etch or dry-etch processes. The dimensions of a feature in photoresist are different from the dimensions of the same feature, etched into a layer on the wafer. This difference between an etched dimension and the corresponding resist dimension is called: etch-bias or etch-skew. The etch-bias depends on the local details of the pattern and on the surrounding pattern density. In other words, the etch bias depends on some aspects of the pattern that is being etched. To be valid, verification has to account for the etch bias. For this purpose, we introduce the concepts of etch-target and litho-target.
Etch-target is a set of polygons or a set of curves that describe the desired result of wafer etch. Points on the etch target curves or polygons are etch target points. Etch-target is the same as the target pattern or target layout described in the Background Section above.
Litho-target is a set of polygons or a set of curves that describe the desired edges of resist features formed by photolithography. The etched pattern is determined by the pattern in photoresist. The litho target is such that, if the resist pattern substantially conforms to the litho-target, the resulting etch-pattern substantially conforms to the etch-target. Litho target points are points on the litho-target curves or polygons.
According to an embodiment of this invention, verification comprises the following high-level steps, which are explained in reference to
The etch model was described by Zach et al. in Utility application Ser. No. 11/541,921, filed Oct. 2, 2006, which is incorporated by reference.
Upon etching, the edge of a pattern is displaced in the plane of the wafer, in the direction that is normal (perpendicular) to the edge, by a lateral etch bias ΔEdge, which can be positive or negative. The mathematical model for the lateral etch bias is:
The term “lateral etch bias,” or “etch bias” for short, refers to changes in the dimensions in the plane of the wafer. It is not to be confused by etch depth or a bias in the etch depth.
In equation (3), a_{0 }is a constant etch-bias. The term Ω_{SKY }is equal or related to a solid angle that subtends the visible part of the sky (plasma above the wafer) from a view point at a point on a sidewall of the etched pattern. Assuming the sidewall is impacted by plasma particles that are equally likely to travel in any direction, the rate of particles that impact the sidewall is proportional to the solid angle of the sky. Similarly, reaction products that are formed at the bottom (floor) of trenches that are being etched can sputter on to the sidewalls and form a polymer that protects the sidewall from further etching. The rate of such sputtering is governed by a similar “solid angle of the floor.” The term a_{N+1}Ω_{SKY }is intended to approximately account for the combined effect of the plasma particles incident from the sky and the polymer deposition by particles sputtered from the floor. The view point on the sidewall is taken to be a distance h below the top surface of the etched pattern. In a preferred embodiment, the depth parameter h is adjusted by fitting the predictions of the model to measured etch biases. Alternatively, the depth h can be set to be a fixed fraction of the etch depth, such as half of the etch depth.
The function (resist pattern) (x,y) in Equation (3) takes the value 1 where there is resist on the wafer, and 0 where the resist has been removed. The symbol * indicates two-dimensional convolution. The summation on the right-hand-side of Equation (3) is a point-spread-function that accounts for pattern density effects in etching the wafer. Changes in the pattern density affect the rate at which reactants are consumed and reaction products are generated. Local variations in the densities of reactants and reaction products are partially equalized by diffusion processes which are not instantaneous. The point-spread-function is a linear superposition of Gaussians with length parameters σ_{1}, σ_{2}, . . . , σ_{N}, which describes a combination of diffusion processes with various diffusion rates. According to certain embodiments, σ_{1}, σ_{2}, . . . , σ_{N }are assigned logarithmically spaced values between the minimum and maximum diffusion lengths that can be probed by the test patterns that are used to calibrate the etch model. In an alternative embodiment, the parameters σ_{1}, σ_{2}, . . . , σ_{N }are determined by minimizing the difference between predictions of the model and measured etch biases of test patterns. The amplitudes, or coefficients, a_{0}, a_{1}, a_{2}, . . . , a_{N+1 }are adjustable, and a priori unknown, parameters of the etch model. The coefficient a_{N+1 }is the weight of the solid angle term, which accounts for deposition or ablation of material on the sidewall. Each of the coefficients a_{0}, a_{1}, a_{2}, . . . , a_{N+1 }can be positive or negative.
Calibration of the Etch Model
A multitude of test patterns are printed on a wafer to calibrate the etch model. According to certain embodiments, the test patterns include line gratings. Dimensions of the photoresist pattern on the wafer are measured by electron microscopy (CD-SEM), or atomic force microscopy, or optical scatterometry. Then, the wafer is etched following the same etch process that will be used in the manufacturing of a semiconductor device. The dimensions of the etched patterns are measured. Care is exercised to take measurements at the same locations in the pattern before and after etch. The etch bias ΔEdge is calculated from the difference of the resist and post-etch measurements. For example, for line gratings:
ΔEdge=(CD _{ETCH} −CD _{LITHO})/2 (4)
CD_{LITHO }and CD_{ETCH }are dimensions of the same feature in a test pattern before and after etching, respectively. They are also know as the develop inspection (DI) and final inspection (FI) critical dimensions, respectively. The parameters a_{1}, a_{2}, . . . , a_{N+1 }of the model are obtained from ΔEdge for a plurality of test targets with various line and space widths. The parameters a_{0}, a_{1}, a_{2}, . . . , a_{N+1 }are obtained by linear regression, i.e., by solving a system of linear equations in the least-squares sense. For line-space targets, the linear system of equations is as follows:
In Equation (5), the index m labels a multitude of line grating test targets. Each line grating has different combination of line and space widths. The parameters of the line gratings are as follows:
K _{m,1} +K _{m,2}+1=number of lines in the m^{th }line grating target (6)
K _{m,1}+1=line number in the m^{th }grating on which the measurement is taken
L_{m}=line width in the m^{th }line grating target
S_{m}=space width in the m^{th }line grating target
P _{m} =L _{m} +S _{m}=pitch of the m^{th }line grating target
The first N coefficients in Equation (5) are convolutions of Gaussian kernels with
The last term in Equation (5) is the solid angle of the sky seen from a point on the side wall of the K_{m,1}+1^{st }line in the m^{th }line grating target, a distance h from the top of the line:
In an alternative embodiment, Ω_{m }is replaced by Ω_{m} ^{(l) }where:
The angle θ is the angle between the surface normal of the sidewall and the line segment from the observation point on the sidewall to a point on the integration surface. The integral is taken on an imaginary surface, parallel to the plane of the wafer, at the top of the etched features. The integral is taken over only the part of this plane at which the sky (plasma) is visible from the observation point on the sidewall. In a preferred embodiment, l=1. In the embodiment of Equation (8), l=0.
FIGS. 3.a-3.f show measured etch biases that make up the calibration data; the etch biases calculated according to the best fitting model; and the differences between the measurements and the model, which are labeled “un-modeled.” The horizontal axes indicate pitches (line width+space width) of line gratings. Each point on these figures corresponds to a line grating having a distinct combination of line and space widths. The measurements in FIGS. 3.a-3.c are widths of lines. The measurements in FIGS. 3.d-3.f are widths of spaces. Spaces are regions that are etched and lines are regions that are protected by a photoresist. Model parameters were determined by fitting the model to 169 measured etch biases in the least-squares sense. That is, the model parameters minimize the sum of squares of fit errors over 169 test patterns. In this example, the line gratings were printed using a lithography projector with a 193 nm exposure wavelength and a numerical aperture of NA=0.75. The layer that is etched is a poly-silicon gate layer with a hard mask. The hard mask and the poly-silicon are etched with two separate etch processes. The model is fitted to the final result etched in poly-silicon.
Once equation (5) is solved, the model has been calibrated and it can be used to predict etch bias of arbitrary 2-dimensional patterns. According to certain embodiments, the model is verified on one-dimensional and two-dimensional test patterns that were not used to calibrate the model. Verification is done by recording CD-SEM images or CD measurements of the verification pattern before and after etching, and comparing the etch bias to the predictions of the model.
Providing a Target Layout Having Polygons
The target layout is generated by circuit layout, routing, timing, and possibly, manufacturability considerations. The target layout is described by the union of a set of polygons. The polygons are typically specified by the coordinates of their vertices and stored in a file in GDS or OASIS format. The target layout is input to the method described in the invention.
Etch Target Points
Target polygons most commonly have 90° angles, in some cases 135° angles, at their vertices. Such sharp corners are impossible to produce reliably with a combination of photolithography and etching. According to certain embodiments, we round the corners of the target polygons to render them realizable. A practical advantage of rounding corners is: the direction that is perpendicular to the edge of a polygon is not well defined at the vertices of a polygon, but the normal direction is always unambiguous for a smooth closed curve that doesn't intersect itself. There are many ways of rounding the corners of a polygon: one approach is to replace the corners of the polygon with segments of circles or ellipses that are tangent to the edges of the polygon. A preferred embodiment of generating etch target points comprises the following steps which are explained referring to
This method replaces a target polygon 110 with a set of etch-target points 130 that lie on a smooth curve 120. The smooth curve 120 is not explicitly defined but it is represented by points p_{1} ^{(K)}, p_{2} ^{(K)}, . . . (130 in
What we mean by curvature of the smooth curve at a point p on the curve is the magnitude of the vector d^{2}p(s)/(ds)^{2 }where p(s) is the parametric representation of a point on the curve, wherein the parameter s is the path length along the curve measured from an arbitrary point on the curve. In practice, since we only have a set of points p_{1}, p_{2}, . . . , p_{N }on the smooth curve, we numerically calculate the curvature at p_{n }according to:
In this discussion, p_{n }refers to one of many points on a curve that are sequentially labeled. The points p_{n−1 }and p_{n+1 }are adjacent to p_{n}. It is understood that p_{n+1 }stands for p_{1 }if n=N is the last point. Similarly, p_{n−1 }is understood to stand for p_{N }if n=1 is the first point.
Obtaining Litho Target Points from Etch Target Points
Etch target points 130 are selected on etch target curves 120. The outward unit normal {right arrow over (n)} of each curve is calculated at each target point 130. The outward normal vector (180 in
The unit vector {circumflex over (z)} is normal to the plane of the wafer. The normal vector {right arrow over (n)}_{m }at a point p_{m }on a smooth, closed curve that passes through the points p_{1}, p_{2}, . . . , p_{N }is numerically calculated as follows:
The corresponding litho target point 140 is displaced by −{right arrow over (n)}ΔEdge from 130 where ΔEdge is the etch bias calculated by the etch model. The solid angle and the convolutions in (3) are calculated for the pattern defined by the etch target points.
In the preferred embodiment, the model of Equation (5) is fitted to required corrections that are experimentally observed. In this embodiment, (5) is an approximation to the inverse of the etch model. The etch compensation, that is, the inverse of the etch model, can be rapidly calculated by this method.
Calculation of the Optical Lithography Image Intensity
The intensity of the latent image in a photoresist film deposited on a wafer can be expressed as:
(See: N. Cobb et al., “Mathematical and CAD Framework for Proximity Correction,” Proc. SPIE Vol. 2726, p. 208, 1996) In (13), which is derived from the Kirchhoff approximation, μ_{1}, μ_{2}, . . . , μ_{N }are positive-valued eigenvalues and V_{1}, V_{2}*, . . . , V_{N}* are complex conjugate of eigenfunctions of a Hermitian, positive-semidefinite operator; and m(x, y) is the complex transmission coefficient of the mask at the point (x, y). For binary masks, m(x, y)=1 in clear areas, and m(x, y)=0 in opaque areas. In 180° phase-shifted windows on the photomask, m(x, y)=−1. In general, in a φ-radian phase-shifted window, m(x, y)=e^{iφ}. For an attenuated phase-shift feature with power transmission coefficient T, the mask function takes the value: m(x, y)=e^{iφ}√{square root over (T)} wherein the nominal value of the phase shift is: φ=π. For reflective masks, m(x, y) is the complex reflection coefficient of the mask at the position (x, y). The focus variable z, denotes the position of the wafer with respect to best focus. The variable z is not to be confused with the vertical position inside the photoresist.
The intensity in the Equation (13) can also be computed in frequency domain as;
In Equation (14), {circumflex over (V)}_{n }and {circumflex over (m)} represent the 2-dimensional spatial Fourier transforms of V_{n}, and m, respectively. The IFT refers to the Inverse Fourier Transform. In a preferred embodiment the intensities are computed on a grid, with Nyquist Sampling rate or denser, and the values at the points of interest are interpolated from the values at the grid points.
According to an embodiment of this invention, verification comprises the following high-level steps, which are explained in reference to
It will be appreciated that the invention is not restricted to the particular embodiment that has been described, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims, as interpreted in accordance with principles of prevailing law, including the doctrine of equivalents or any other principle that enlarges the enforceable scope of the claims beyond the literal scope. Unless the context indicates otherwise, a reference in a claim to the number of instances of an element, be it a reference to one instance or more than one instance, requires at least the stated number of instances of the element but is not intended to exclude from the scope of the claim a structure or method having more instances of that element than stated.
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U.S. Classification | 716/55 |
International Classification | G06F9/45, G06F17/50 |
Cooperative Classification | G03F1/36 |
European Classification | G03F1/36 |
Date | Code | Event | Description |
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Oct 10, 2007 | AS | Assignment | Owner name: CADENCE DESIGN SYSTEMS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YENIKAYA, BAYRAM;JOSHI, DEVENDRA;FORNARI, PAUL A.;AND OTHERS;SIGNING DATES FROM 20071002 TO 20071004;REEL/FRAME:019939/0641 |
Jun 19, 2008 | AS | Assignment | Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INVARIUM, INC.;REEL/FRAME:021122/0328 Owner name: CADENCE DESIGN SYSTEMS, INC, CALIFORNIA Effective date: 20080604 |
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