US 7852019 B2
An electronic circuit exhibiting synchronization with an external synchronization signal, the electronic circuit comprising: an input connection arranged to receive a synchronization input signal; a triangular waveform oscillator operatively associated with the synchronization signal input connection and responsive to a condition of the received synchronization input signal to initiate a triangular waveform; and a pulse train generator operatively associated with the triangular waveform oscillator, the pulse train generator arranged to generate a plurality of pulse trains having a fixed non-zero phase relationship between them and a frequency responsive to the condition of the synchronization input signal.
1. A method of synchronizing the operation of at least one electronic circuit, the method comprising:
generating a triangular waveform signal responsive to a synchronization signal, said triangular waveform signal exhibiting a fundamental first frequency, said synchronization signal exhibiting a second frequency;
generating a plurality of pulse trains having a fixed non-zero phase relationship between them, wherein said pulse trains exhibit one of said first frequency and said second frequency; and
modulating a received control signal with said generated plurality of pulse trains to generate a plurality of modulated pulse trains exhibiting said fixed non-zero phase relationship and a synchronization with the synchronization signal.
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11. An electronic circuit exhibiting synchronization comprising:
an input connection arranged to receive a synchronization input signal;
a triangular waveform oscillator operatively associated with said synchronization signal input connection and responsive to a condition of said received synchronization input signal to initiate a triangular waveform;
a pulse train generator operatively associated with said triangular waveform oscillator, said pulse train generator arranged to generate a plurality of pulse trains having a fixed non-zero phase relationship between them and a frequency substantially equivalent to one of the free running frequency of said triangular waveform oscillator and the frequency of the received synchronization input signal; and
a signal modulator operatively associated with said pulse train generator and arranged to generate a plurality of modulated pulse trains exhibiting said fixed non-zero phase relationship and said frequency responsive to said condition of said synchronization input signal.
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The present invention relates to synchronization of disparate electronic circuits, and more particularly, to synchronization of a plurality of phased signals to an external synchronization input.
Cold Cathode Fluorescent Lamps (CCFL) are extensively used today as backlights for computer liquid crystal displays (LCD) and LCD televisions. CCFL lamps are typically driven in a push pull configuration such that current flows alternatively in each direction to ensure long life and uniform operation. A CCFL driver thus must provide a pair of complementary drive signals which are out of phase with each other. Typically, a CCFL driver requires a pair of driving signals which are 180° out of phase with each other, however this is not meant to be limiting in any way and 90° phase difference is also required in some particular applications.
Systems that use a plurality of CCFL lamps for a single display require synchronization between the CCFL drivers so as to avoid interference caused by non-synchronized operation. Further synchronization is often required with a system display signal, such as a video scanning signal, associated with a horizontal scanning frequency, so as to avoid a water wave effect. Such synchronization is required for single and multiple CCFL driver systems.
U.S. Pat. No. 5,615,093 issued Mar. 25, 1997 to Nalbant, the entire contents of which is incorporated herein by reference, is addressed to a power converter circuit for driving a CCFL lamp comprising a controller circuitry. The controller circuitry includes an oscillator capable of self synchronizing to the resonant frequency of the components, and exhibits a sawtooth timing circuit for the oscillator. The clock frequency driving the CCFL is half the frequency of the sawtooth timing circuit. Thus, in order to synchronize a plurality of CCFL controller circuits of the type described by Nalbant, a clock signal double the driving frequency must be propagated or a frequency doubler circuit provided thereby allowing for synchronization from the CCFL driving output.
U.S. Pat. No. 5,923,129 issued Jul. 13, 1999 to Henry, the entire contents of which is incorporated herein by reference, is addressed to a power conversion circuit driving a CCFL. The clock oscillating circuit operates at twice the frequency of the direct drive network and provides the fundamental frequency of operation. Thus, in order to synchronize a plurality of CCFL controller circuits of the type described by Henry, a clock signal double the driving frequency must be propagated, or a frequency doubler circuit provided, thereby allowing for synchronization from the CCFL driving output.
In order to synchronize a plurality of CCFL controller circuits among themselves and/or with a video horizontal scanning frequency, a plurality of connections is typically required including a synchronization signal, a phase signal, and a connection indicating if the CCFL controller circuit is a master or slave. If the operating frequency of the CCFL controller circuit is to be equal to the video horizontal scanning frequency, a frequency doubler is also required since, as described above, the clock is typically double the operating frequency.
These additional circuitry and pins will inevitably increase the complexity and cost of the controller IC or the inverter control circuit.
Accordingly, it is a principal object of the present invention to supply a method and system for synchronizing one or more electronic circuits with an external synchronizing signal. In one embodiment a triangular waveform generator is provided, initiated by a condition of the external synchronizing signal. A pulse train generator receives the triangular waveform and generates a plurality of pulse trains exhibiting a non-zero phase difference there between, the plurality of pulse trains being synchronized to the external synchronizing signal. Optionally, a pulse width modulation (PWM) signal is further received and modulates each of the plurality of pulse trains thereby generating a plurality of synchronized modulated pulse trains with a non-zero phase difference there between.
In one particular embodiment the synchronizing circuit comprises: a triangular waveform oscillator operatively associated with a pulse train generator that is operatively associated with a signal modulator. The triangular waveform oscillator is initiated by a synchronization signal. The pulse train generator is configured to generate two pulse trains synchronized with the synchronization signal and having a 180 degrees phase shift between them. The pulse trains preferably exhibit a frequency associated with one of the synchronization signal and the triangular waveform oscillator. The signal modulator is configured to modulate an incoming signal on the pulse trains resulting in an output signal exhibiting two phases synchronized with the synchronization signal.
In one embodiment, the use of a triangular waveform is used as a master clock signal in a CCFL controller circuit. The triangular waveform is configured such that its frequency is less than, but close to, the frequency of the synchronization signal. The triangular waveform contains the information required to generate a plurality of pulse trains having a fixed non-zero phase difference between them. Preferably, the non-zero phase difference is about 180°. A modulation circuit is preferably further provided arranged to modulate the pulse trains with a PWM signal thereby generating two out of phase outputs modulated by the PWM signal.
Thus, less wiring required and specifically in an integrated circuit (IC) implementation the pin count is reduced—because there is no need to deliver the phase information separately. Since the triangular waveform may have the same frequency of the clock instead half of the frequency as in the traditional saw tooth waveform, the use of a frequency doubler is eliminated, thus saving wafer space.
Advantageously, the circuit according to the disclosure may be used in some embodiments in CCFL implementation, but is not limited thereto.
The subject matter regarded as the invention will become more clearly understood in light of the ensuing description of embodiments herein, given by way of example and for purposes of illustrative discussion of the present invention only, with reference to the accompanying drawings (Figures, or simply “FIGS.”), wherein:
The drawings together with the description make apparent to those skilled in the art how the invention may be embodied in practice.
In electronic circuit diagrams, conventional electronic components are labeled with conventional reference letters followed by a number indication the iteration of that element in the circuit. For example, R indicates a resistor, C indicates a capacitor, A indicates an amplifier (that may be configured in several ways such as a comparator, differential amplifier and the like) and M indicates a Metal Oxide Substrate Field Effect Transistor (MOSFET). Each electronic component has a plurality of terminals (inputs and outputs) through which it is connected to wires and other components. However the use of the word ‘terminal’, ‘input’ or ‘output’ does not imply an implementation based on discrete components only, and any circuit described may be implemented as an integrated circuit (IC). Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, it will be understood by those skilled in the art that the teachings of the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the teachings of the present disclosure.
According to some embodiments, the synchronization method may be incorporated into a CCFL controller. This implementation may be particularly effective for the TV market as well as monitors and thin displays.
In response to triangular waveform 240, pulse train generator 220 generates a plurality of pulse trains having a non-zero phase shift between them and having the same frequency as one of triangular waveform oscillator 210 and synchronization signal 270. In a preferred embodiment, synchronization signal 270 is periodic with a frequency slightly greater than the fundamental frequency of triangular waveform oscillator 210, and thus the pulse trains exhibit the frequency of synchronization signal 270. In an exemplary embodiment two pulse trains, i.e. first pulse train 250 and second pulse train 260, 180° out of phase with each other, are generated. First pulse trains 250 and 260 are synchronized with the condition of synchronization signal 270. Signal modulator 230 is operative to modulate an incoming signal 280, which if preferably PWM signal, on to the pulse trains. This results in two phases 290 and 295 of the PWM signal, each having the same steering frequency, and synchronized with synchronization signal 270.
The synchronization circuit comprises a triangular waveform oscillator 210 generating a triangular waveform 240. Triangular waveform 240 is characterized by nearly symmetrical rising and falling slopes, ideally having a linear form. According to a non-limiting example, triangular waveform oscillator 210 is implemented by charging and discharging a capacitor C1 by a current source. In the illustrated embodiment, capacitor constant current source I1 is charged by a constant current source I1 and discharged by a constant current source I2 via an N-channel MOSFET transistor M1 to ground. Constant current source I1 and constant current source I2 are preferably of identical amplitude.
Triangular waveform 240 is fed into a first comparator A1 and a second comparator A2. Specifically, triangular waveform 240 is fed into the positive input of comparator A1 and to the negative input of comparator A2. The negative input of comparator A1 is fed with a logic “High” reference signal (REFH) whereas the positive input of comparator A2 is fed with a logic “Low” reference signal (REFL). Thus, comparator A1 is configured to detect the peak point of the triangular waveform, whereas comparator A2 is configured to detect the valley point of the triangular waveform.
The output of comparator A1 is connected to the SET input of an RS flip-flop 320, and the output of the comparator A2 is connected in turn to the RESET input of RS flip-flop 320. Synchronizing signal 270 is fed into the first input of an AND gate 350, while a synchronizing Sync-Enable signal 370 is fed to the second input of AND gate 350. The output of the AND gate 350 is connected to an additional SET input of RS flip-flop 320, which is preferably edge triggered. The Q output of RS flip flop 320 is fed back to the gate of N-channel MOSFET transistor M1 of triangular waveform oscillator 210.
The positive Q output of RS flip flop 320 is further connected to a first input of an AND gate 330. The negative Q output of RS flip flop 320 is connected to a first input of an AND gate 340. A PWM control signal 280 is fed into the second input of AND gate 330 and to the second input of AND gate 340 respectively.
In operation, Sync-Enable signal 370, enables over-ride of the synchronization and is preferably from a control system. In the event that Sync-Enable signal 370 is active, thus allowing for synchronization, synchronizing signal 270 is passed through AND gate 350 and appears at the second Set input of RS flip-flop 320. Second Set input of RS flip-flop 320 is preferably edge triggered, as described above, and thus when a positive going edge of synchronizing signal 270 is presented at second Set input of RS flip-flop 320, RS flip-flop 320 is set and the positive Q output of RS flip-flop 320 becomes active which switches on MOSFET M1 causing capacitor C1 to discharge through current source I2 and initiates the falling slope of triangle waveform 240. Thus, the edge of synchronizing signal 270 initiates the falling slope of triangle waveform 240.
When comparator A2 detects the valley point of triangular waveform 240, i.e. triangular waveform 240 is more negative than REFL, the output of comparator A2 goes positive thereby resetting RS flip flop 320. It is to be understood that the output of comparator A1 is low, since the valley point of triangular waveform 240 is more negative than REFH. Consequently a logic “Low” appears on the positive Q output of RS flip flop 320, and a logic “High” on the negative Q output of RS flip-flop 320. The logic “Low” on the positive Q output of RS flip flop 320 turns off MOSFET transistor M1 thus enabling the charging of capacitor C1 by constant current source I1, and thereby initiating the rising slope of triangular waveform 240. In the event another condition of synchronizing signal 270 is not received, comparator A1 will detect the peak point of triangular waveform 240, and reset RS flip flop 320 to output a logic “High” at the positive Q output.
Thus the positive Q output is positive responsive to a condition of synchronizing signal 270, and the negative Q output is positive responsive to ½ the fundamental cycle time of triangular waveform oscillator 210. Thus, the output of RS flip-flop 320 exhibit two pulse trains having a 180 degree phase shift between them and a frequency responsive to one of triangular waveform oscillator 210 and synchronizing signal 270. Notably, the pulse trains have the same frequency as the triangular waveform oscillator 210 instead of half of it. Such pulse trains are the base signal of the contemporary double-ended switching power converter topology, preferably utilized to drive a CCFL lamp load.
These pulse trains are then used by AND gates 330 and 340 in the configuration depicted above to generate the two phase outputs of PWM control signal 280. Thus, the output of AND gate 330, denoted AOUT, exhibits PWM control signal 280 when the positive Q output of RS flip-flop 320 is positive, and the output of AND gate 340, denoted BOUT, exhibits PWM control signal 280 when the negative Q output of RS flip-flop 320 is positive. These two modulated PWM control signals exhibit a fixed phase relationship, are synchronized with synchronization signal 270 and exhibit a frequency reflective thereof, or reflective of the frequency of triangular waveform oscillator 210.
According to some embodiments, synchronization signal 270 may be of any type of pulse as long as its amplitude meets the high-low logic signal level requirements of the AND gate 350, and the state duration is sufficient for the set/reset time requirement of the RS flip-flop 320. Sync-Enable signal 370 of the AND gate 350 is driven from a timing circuit of a control system (not shown) that may disable the synchronization function when it is not required.
The inter-inverter synchronization signal can also be derived from the triangle waveform of triangular waveform oscillator 210 directly as illustrated in
In-phase operation can be achieved by inverting the square wave derived from the triangular waveform using an inverter 440 for the derived signal and applying the inverted signal to the SYNC input of slave controller 420 as shown in
Advantageously, the synchronization circuit and the synchronization method described in the disclosure may be effectively applied to any kind of multi-inverter operations where the frequency or phase of the inverters needs to be synchronized either internally among them or externally with an external synchronizing signal.
Any publications, including patents, patent applications and articles, referenced or mentioned in this specification are herein incorporated in their entirety into the specification, to the same extent as if each individual publication was specifically and individually indicated to be incorporated herein. In addition, citation or identification of any reference in the description of some embodiments of the invention shall not be construed as an admission that such reference is available as prior art to the present invention.
While the invention has been described with respect to a limited number of embodiments, these should not be construed as limitations on the scope of the invention, but rather as exemplifications of some of the preferred embodiments. Those skilled in the art will envision other possible variations, modifications, and applications that are also within the scope of the invention. Accordingly, the scope of the invention should not be limited by what has thus far been described, but by the appended claims and their legal equivalents.