|Publication number||US7853233 B2|
|Application number||US 11/180,957|
|Publication date||Dec 14, 2010|
|Filing date||Jul 13, 2005|
|Priority date||Sep 16, 2004|
|Also published as||CN101053149A, CN101053149B, US20060057989, WO2006034021A1|
|Publication number||11180957, 180957, US 7853233 B2, US 7853233B2, US-B2-7853233, US7853233 B2, US7853233B2|
|Original Assignee||Qualcomm Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (30), Non-Patent Citations (2), Referenced by (2), Classifications (25), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Priority is hereby claimed to U.S. Provisional Application No. 60/611,203 filed Sep. 16, 2004.
This patent document contains information subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent, as it appears in the US Patent and Trademark Office files or records, but otherwise reserves all copyright rights whatsoever.
Aspects of the disclosure relate to the suppression of signal distortion in RF communication systems, for example, wireless handsets.
A RF receiver mixes an incoming signal thereby changing its carrier frequency. In a heterodyne receiver, the mixer changes the incoming signal's carrier frequency to an intermediate frequency. In a direct conversion RF receiver, otherwise called a zero IF RF receiver, the mixer changes the incoming signal's carrier frequency to a frequency of zero.
A given mixer may generate distortion components, including a distortion referred to as the “second order IM2 distortion.” This distortion is at a relatively low frequency, and thus generally does not have a large impact on the signal-to-noise ratio of a mixed signal in a heterodyne receiver. In contrast, in the zero IF RF receiver, the second order IM2 distortion more closely coincides with the down converted (mixed) signal. The IM2 distortion is at a low frequency, and the mixed signal with a carrier frequency of zero is also at a low frequency. Therefore, with the zero IF RF receiver, the second order IM2 distortion has much more of an impact on the mixed signal's signal-to-noise ratio.
An embodiment is directed to a zero IF down converter circuit. The circuit comprises a voltage-to-current converter, a mixer, and a suppression circuit. The voltage-to-current converter converts an RF voltage signal to an RF current signal. The mixer changes a frequency of the current signal to a lower frequency current signal. The suppression circuit removes a lower frequency distortion component from the RF current signal before sending the RF current signal to the mixer.
Embodiments will be described with reference to the following drawing figures, in which like numerals represent like items throughout the figures, and in which:
The RF receiver 22 and its components are illustrated schematically; other components (not shown) may be included. In general, front-end component 24 processes a voltage at a pre-selected RF frequency, and inputs the voltage to a zero IF down-converter 26. Front-end component 24 may comprise an amplifier, a filter, and/or an oscillator (which for simplicity, are not specifically shown in
The zero IF down-converter may be followed by or coupled to any number of components; a filter 34, an analog-to-digital converter 36, and a digital signal processor (DSP) 38 are illustrated in
Zero IF down-converter 26 may comprise a voltage-to-current converter 30 and a mixer core 32. In general terms, Zero IF down-converter 26 is a voltage device in and a current device out. Voltage-to-current converter 30 converts the input voltage signal into an output current signal, and sends the current signal to the mixer core 32. Mixer core 32 mixes the current signal from voltage-to-current converter 30 with an oscillator signal.
A goal of an RF receiver of a wireless handset (e.g., a mobile phone) is to provide a clear signal to the wireless handset. As mentioned above, elements of a voltage-to-current converter 30 of a zero IF down-converter 26 may produce an even-order non-linearity that generates a low frequency inter-modulation component (referred to above as a “second order IM2 distortion”). The inter-modulation component overlaps with the desired output signal of the voltage-to-current converter 30, which is passed through the mixer core 32. Mismatching of the signals in the mixer core 32 causes the inter-modulation component to interfere with the mixer core's 32 output signal; in effect the inter-modulation component cannot be distinguished from the desired signal. As a result, the inter-modulation component causes a distortion in the mixer's output signal.
To address the above-identified phenomena, voltage-to-current converter 30 of
Voltage-to-current converter 30 comprises a voltage-to-current circuit 200 and a suppression circuit 150. In this embodiment, the voltage-to-current circuit 200 and the suppression circuit 150 are implemented with the same type of transistor devices. Voltage-to-current circuit 200 comprises a pair of n-channel MOSFET transistors 50, 52, a pair of inductors 62, 64, a pair of resistors 58, 60, and a pair of capacitors 70, 72. RFin nodes 76, 74 are the voltage input terminals of the voltage to current converter. The voltage-to-current circuit 200 converts the RF input voltage signal 76, 74 into a current for subsequent signal processing in the mixer core 32. Vg1 and Vg2 are DC bias voltages.
The suppression circuit 150 suppresses the low frequency inter-modulation component generated by an even-order non-linearity produced by transistor 50 and transistor 52 of the voltage-to-current circuit 200. As shown in
Another example embodiment is shown in
The voltage-to-current circuit 200 converts the RF input voltage signal 76, 74 into a current for subsequent signal processing in the mixer core 32. The components 50, 52, 62, 64, 58, 60, 70, 72 of voltage-to-current circuit 200 may be the same or similar to the components illustrated in
The suppression circuit 150 is added to voltage-to-current circuit 200 for suppression of the inter-modulation component generated by an even-order non-linearity (e.g., a second order harmonic) produced by transistor 50 and transistor 52 of the voltage-to-current circuit 200. As shown in this embodiment, suppression circuit 150 includes a pair of n-channel MOSFET transistors 54, 56, a capacitor 68, and an operational amplifier 90. Transistor 54 and transistor 56 provide a low frequency resistance to the voltage-to-current circuit 200. Capacitor 68 is an AC bypass capacitor that grounds the RF frequency components of inductor 64. Thus with this arrangement, the noise from transistor 54 and from transistor 56 are shunted to ground. The operational amplifier 90 increases the low frequency impedance of transistor 54 and transistor 56 by an amount equal to its gain. The RF input is coupled to the voltage-to-current circuit 200 through capacitor 70 and capacitor 72. In conjunction, these components generate high impedance at the inter-modulation frequency to the source terminal of transistor 50 and to the source terminal of transistor 52. As a result of generating high impedance at a low frequency to the source terminal of transistor 50 and to the source terminal of transistor 52, the low frequency inter-modulation component generated by voltage-to-current circuit 200 is suppressed.
While certain illustrated embodiments have been described, the words which have been used are words of description rather than words of limitation. Changes may be made, e.g., within the purview of the appended claims.
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|US8401511 *||Nov 9, 2010||Mar 19, 2013||Realtek Semiconductor Corp.||Current-mode wireless receiver and reception method thereof|
|US20110111717 *||Nov 9, 2010||May 12, 2011||Realtek Semiconductor Corp.||Current-mode wireless receiver and reception method thereof|
|U.S. Classification||455/323, 327/551, 455/66.1, 327/356, 455/333, 455/67.11, 327/113, 330/254, 455/118, 455/550.1, 327/552, 455/326, 327/359, 455/78|
|Cooperative Classification||H03D7/1483, H03D7/1458, H04B1/109, H03D1/2272, H03D7/1441, H04B1/30|
|European Classification||H03D1/22F, H04B1/30, H04B1/10S, H03D7/14C2|
|Sep 20, 2005||AS||Assignment|
Owner name: QUALCOMM INCORPORATED, A DELWARE CORPORATION, CALI
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WU, YUE;REEL/FRAME:016828/0325
Effective date: 20050907
|May 28, 2014||FPAY||Fee payment|
Year of fee payment: 4