|Publication number||US7877652 B1|
|Application number||US 10/404,573|
|Publication date||Jan 25, 2011|
|Filing date||Mar 31, 2003|
|Priority date||Mar 31, 2003|
|Publication number||10404573, 404573, US 7877652 B1, US 7877652B1, US-B1-7877652, US7877652 B1, US7877652B1|
|Inventors||Robert John Schuelke|
|Original Assignee||Qualcomm Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Non-Patent Citations (1), Classifications (6), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to electronic circuits. More particularly, the present invention relates to a circuit for the detection of manufacturing defects in an integrated circuit and/or in an integrated circuit board assembly.
The detection of circuit board manufacturing defects is a long-established and standardized industry practice. The industry standard practices for these methods are described in IEEE Standard 1149. This standard method of testing is often referred to as JTAG in reference to the Joint Test Action Group standards committee from which it originated. That standard stipulates the test methodology and interface protocols for implementing different types of test functions that allow a board manufacturer to verify that circuit boards and associated integrated circuits (“ICs”) are manufactured properly. The JTAG standard is specific to CMOS logic circuits—unfortunately, the JTAG standard does not address in detail the testing of analog or AC coupled circuitry.
One aspect of the standard involves the verification of the board level interconnect between ICs. In the methodology described in the standard it is assumed that the connection between the ICs is a DC coupled connection and that the signal levels are commensurate with standard CMOS logic. In these instances the standard calls for a boundary scan cell to be placed at the input and output (“I/O”) pins of the interconnect. The dedicated test interface then allows the tester to force a specified DC logic level out of the driving IC and to determine the logic level received at the input end of the connection. If the correct anticipated pattern is received, then the interconnect is deemed to be manufactured correctly and to be viable.
There are, however, a significant number of instances where interconnect signals between ICs are AC coupled and do not conform to CMOS logic levels. AC coupled circuits typically require a coupling capacitor between circuits to block DC current during the transmission of AC signals. An example would be an AC coupled high-speed differential current mode logic (“CML”) level interface between a physical media dependent (“PMD”) device and a physical layer (“PHY”) device in a data communication link. In this situation the prescribed DC CMOS logic test methodologies would not be successful in verifying the connection. Consequently, a different approach is required for testing the AC interconnection between CMOS logic circuits or CMOS ICs.
One recent proposal has been made for adaptation or modification of the JTAG standard to permit the introduction of an alternating AC signal into non-CMOS logic level AC coupled interconnects. This proposal may be termed “ACJTAG”. The signal is synchronously sampled on the receiver side at intervals to determine if the signal was appropriate to the anticipated interconnect. If the received pattern is consistent with expectations, the interconnect is deemed correct. Otherwise, the assumption is made that there is a defect in the interconnect between the ICs under test. However, this proposal has not set forth a means and mode for interconnection of the test logic to high speed AC coupled signal lines.
Our invention enables the detection and interfacing of high-speed AC coupled non-CMOS logic level signals into ACJTAG logic by allowing an alternating AC signal to be driven onto non-CMOS logic level AC coupled interconnects; it is applicable as well to non-CMOS level single-ended and differential signals with or without AC coupling. This AC signal is synchronously sampled on the receiver side at intervals to determine if the signal is appropriate to the anticipated interconnect. If the received pattern is consistent with expectations, the interconnect is deemed correct. Otherwise it is assumed that there is an issue with the manufacturing process.
While the above proposal outlines the digital portion of the test methodology, it does not define how to interface the logic to the high-speed AC coupled signal lines.
An integrated circuit architecture and methodology according to the present invention provides a means to detect manufacturing defects in an AC coupled circuitry interconnect. The techniques of the present invention are compatible with existing standard test methodologies, such as the JTAG standard.
A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in conjunction with the following Figures, wherein like reference numbers refer to similar elements throughout the Figures.
The present invention may be described herein in terms of functional block components and various processing steps. It should be appreciated that such functional blocks may be realized by any number of hardware, software, and/or firmware components configured to perform the specified functions. For example, the present invention may employ various integrated circuit components, e.g., amplifiers, logic elements, look-up tables, clock elements, and the like, which may carry out a variety of functions under the control of one or more microprocessors or other control devices. In addition, those skilled in the art will appreciate that the present invention may be practiced in conjunction with any number of integrated circuits and that the specific functionality of such integrated circuits is unimportant.
It should be appreciated that the particular implementations shown and described herein are illustrative of the invention and its best mode and are not intended to otherwise limit the scope of the invention in any way. Indeed, for the sake of brevity, conventional techniques related to digital logic and control, multiplexer operation, boundary scan cells, JTAG testing methodologies, and other functional aspects of the circuits (and the individual operating components of the circuits) may not be described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in a practical embodiment.
The following description and claims may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits are not adversely affected).
As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, or the like at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).
The circuit and methodology described herein provides a solution to detecting and interfacing high-speed AC coupled non-CMOS logic level signals into logic that is compliant with the JTAG boundary scan testing standard. In addition, this approach is equally applicable to non-CMOS level, single-ended, and differential signals with or without AC coupling. One typical high-speed interface that could be addressed by this approach is one that employs differential 50 Ohm terminated CML signals.
To facilitate testing of manufacturing defects, many ICs now incorporate the JTAG boundary scan architecture set forth in “IEEE Standard Test Access Port and Boundary-Scan Architecture” (IEEE Standard 1149.1-1990, Institute of Electrical and Electronic Engineers, Inc., 1993). The content of this document is incorporated by reference herein.
If IC 100 is compliant with the JTAG boundary scan structure, then it will include (among other features) a test data input (“TDI”) node 112, and a test data output (“TDO”) node 114. The boundary scan cells 110 are coupled together to form a chain beginning at TDI node 112 and ending at TDO node 114. During testing, the TDI and TDO nodes receive the data input and output signals for the boundary scan chain. The test data output received at the TDO node 114 is ultimately analyzed to determine the extent of manufacturing defects such as continuity and interconnection faults.
All of the above manufacturing faults can be detected with an activity detection circuit that is coupled in parallel with the inputs of the data receiver inputs.
The first input node 218 of amplifier stage 212 is connected to one end of a resistor 220. The second end of the resistor 220 is connected to a supply voltage. In the example embodiment, the resistor 220 is a 50 Ohm resistor. Similarly, the second input node 222 of amplifier stage 212 is connected to one end of a resistor 224. The second end of the resistor 224 is also connected to the supply voltage. In the example embodiment, the resistor 224 is also a 50 Ohm resistor.
The differential output of the first amplifier stage 212 is utilized as a differential input to a second amplifier stage 226. The differential output of the second amplifier stage may be routed in a suitable manner for use as a high-speed signal path.
The first input node 218 is also connected to a first input node 228 of the activity detector circuit 202, and the second input node 222 is also connected to a second input node 230 of the activity detector circuit 202. The activity detector circuit 202 is configured to receive a channel enable signal at an enable I/O pin 232. A first output (labeled “OR” in
The flip-flop circuit 238, which operates in a conventional manner, also receives the AC_SYNC signal as a clock signal. The data output of the flip-flop circuit 238 is connected to the second input node 240 of the multiplexer 236. In the example embodiment, the data present at the first input node 234 of the multiplexer 236 is output at the multiplexer output node 242 when the multiplexer select signal 244 is a logic high state. On the other hand, the data present at the second input node 240 of the multiplexer 236 is passed to the multiplexer output node 242 when the multiplexer select signal 244 is a logic low state. In the illustrated embodiment, the multiplexer select signal 244 corresponds to the NOT_AC_TEST_RAN signal present at an I/O pin 246.
The output node 242 of multiplexer 236 is connected to one input node 248 of a multiplexer 250. The other input node 252 of the multiplexer 250 is connected to an I/O pin 254 to receive the scan/test pattern data from the previous scan cell. The output of multiplexer 250 is controlled by a select signal 256, which corresponds to the ShiftDR signal present at an I/O pin 258. In the example embodiment, the data present at the input node 248 of the multiplexer 250 is output at the multiplexer output node 253 when the multiplexer select signal 256 is a logic low state. On the other hand, the data present at the input node 252 of the multiplexer 250 is passed to the multiplexer output node 253 when the multiplexer select signal 256 is a logic high state.
The output of multiplexer 250 is connected to the “data” input of another flip-flop circuit 260. The flip-flop circuit 260 also receives the ClockDR signal 262 (present at an I/O pin 264) at its clock input node. The data output of the flip-flop circuit 260 is connected to a first input node 266 of a multiplexer 268. The data from the previous scan cell is also provided at a second input node 270 of the multiplexer 268. The output of the multiplexer 268 represents the output of the scan cell 200, which is passed on the next scan cell. Of course, if the scan cell 200 is the last cell in the chain, then the output of the multiplexer 268 corresponds to the test data output signal. The multiplexer 268 is controlled by a select signal 274. In this example, the select signal 274 corresponds to the channel enable signal present at I/O pin 232. In the example embodiment, the data present at the first input node 266 of the multiplexer 268 is output at the multiplexer output node 272 when the multiplexer select signal 274 is a logic high state. On the other hand, the data present at the second input node 270 of the multiplexer 268 is passed to the multiplexer output node 272 when the multiplexer select signal 274 is a logic low state.
A reset (“RST”) signal 276 is received at an I/O pin 278. The RST signal 276 is connected to the clear (“CLR”) input of the flip-flop circuit 260, and to one input of an OR gate 280. The NOT_AC_TEST_RAN signal serves as the other input to the OR gate 280, as shown in
Referring again to the example circuit of
This logical OR signal can also be used to enable other receiver circuitry to realize a power savings in the absence of an input signal or to indicate a detected signal in the JTAG EXTEST mode. In this regard, the OR signal output of the activity detection circuit is also connected to the enable inputs of the first amplifier stage 212 and the second amplifier stage 226.
Referring again to
AND=activity_on_noninverting_input & activity_on_inverting_input & input_equivalent_logical_state
According to this expression, if a known AC data pattern is driven into the data receiver inputs (218,222) the activity circuit 202 will produce a signal on its AND output that replicates those patterns on the condition that there is a viable connection driving those inputs. Otherwise, a zero output will always exist, indicating or corresponding to a fault. Other encoding formats for the AND signal are possible as well.
In view of these considerations, the invention enables the detection of any of the defects illustrated in
The present invention has been described above with reference to a preferred embodiment. However, those skilled in the art having read this disclosure will recognize that changes and modifications may be made to the preferred embodiment without departing from the scope of the present invention. These and other changes or modifications are intended to be included within the scope of the present invention, as expressed in the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4839878 *||Mar 11, 1988||Jun 13, 1989||Nec Corporation||Apparatus for controlling the writing of data in disk sectors|
|US5673130 *||Jan 2, 1996||Sep 30, 1997||Motorola, Inc.||Circuit and method of encoding and decoding digital data transmitted along optical fibers|
|US6662134 *||Nov 1, 2001||Dec 9, 2003||Agilent Technologies, Inc.||Method and apparatus for enabling extests to be performed in AC-coupled systems|
|US6691269 *||Jan 25, 2001||Feb 10, 2004||Logicvision, Inc.||Method for scan controlled sequential sampling of analog signals and circuit for use therewith|
|US6763486 *||May 9, 2001||Jul 13, 2004||Agilent Technologies, Inc.||Method and apparatus of boundary scan testing for AC-coupled differential data paths|
|US6877121 *||Jul 19, 2001||Apr 5, 2005||Cisco Technology, Inc.||Boundary scan cell for testing AC coupled line using phase modulation technique|
|US20030229835 *||Feb 11, 2003||Dec 11, 2003||Whetsel Lee D.||High speed interconnect circuit test method and apparatus|
|1||*||IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE Std 1149.1-1990.|
|Cooperative Classification||G01R31/318577, G01R31/318541|
|European Classification||G01R31/3185S2, G01R31/3185S11|
|Apr 18, 2003||AS||Assignment|
Owner name: APPLIED MICRO CIRCUITS CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SOHUELKE, ROBERT J.;REEL/FRAME:013583/0247
Effective date: 20030327
|Nov 21, 2008||AS||Assignment|
Owner name: QUALCOMM INCORPORATED, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:APPLIED MICRO CIRCUITS CORPORATION;REEL/FRAME:021876/0013
Effective date: 20080715
|Sep 9, 2009||AS||Assignment|
Owner name: APPLIED MICRO CIRCUITS CORPORATION, CALIFORNIA
Effective date: 19870327
Free format text: MERGER;ASSIGNOR:APPLIED MICRO CIRCUITS CORPORATION;REEL/FRAME:023196/0950
|Jun 24, 2014||FPAY||Fee payment|
Year of fee payment: 4